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21. 发明授权

US06808981B2 Method for fabricating 6F2 trench DRAM cell with double-gated vertical MOSFET and self-aligned STI 失效
标题翻译：用于制造具有双门控垂直MOSFET和自对准STI的6F2沟槽DRAM单元的方法
公开(公告)号：US06808981B2
公开(公告)日：2004-10-26
申请号：US10375654
申请日：2003-02-27
申请人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Gary B. Bronner
发明人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Gary B. Bronner
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L21/823481 , H01L21/823487
摘要： A memory cell containing double-gated vertical metal oxide semiconductor field effect transistors (MOSFETs) and isolation regions such as shallow trench isolation, STI, regions that are self-aligned to the wordlines and bitlines of the cell are provided. The inventive memory cell substantially eliminates the backgating problem and floating well effects that are typically present in prior art memory cells. A method of fabricating the inventive memory cell is also provided.
摘要翻译：提供了包含双门控垂直金属氧化物半导体场效应晶体管（MOSFET）和隔离区域（诸如浅沟槽隔离，STI，与单元的字线和位线自对准的区域）的存储单元。本发明的存储单元基本上消除了现有技术的存储单元中通常存在的背景问题和漂浮阱效应。还提供了制造本发明的存储单元的方法。

22. 发明授权

US06570208B2 6F2 Trench EDRAM cell with double-gated vertical MOSFET and self-aligned STI 失效
标题翻译： 6F2沟槽EDRAM单元，具有双门控垂直MOSFET和自对准STI
公开(公告)号：US06570208B2
公开(公告)日：2003-05-27
申请号：US09766013
申请日：2001-01-18
申请人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Gary B. Bronner
发明人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Gary B. Bronner
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L21/823481 , H01L21/823487
摘要： A memory cell containing double-gated vertical metal oxide semiconductor field effect transistors (MOSFETs) and isolation regions such as shallow trench isolation, STI, regions that are self-aligned to the wordlines and bitlines of the cell are provided. The inventive memory cell substantially eliminates the backgating problem and floating well effects that are typically present in prior art memory cells. A method of fabricating the inventive memory cell is also provided.
摘要翻译：提供了包含双门控垂直金属氧化物半导体场效应晶体管（MOSFET）和隔离区域（诸如浅沟槽隔离，STI，与电池的字线和位线自对准的区域）的存储单元。本发明的存储单元基本上消除了现有技术的存储单元中通常存在的背景问题和漂浮阱效应。还提供了制造本发明的存储单元的方法。

23. 发明授权

US06501117B1 Static self-refreshing DRAM structure and operating mode 失效
标题翻译：静态自刷新DRAM结构和工作模式
公开(公告)号：US06501117B1
公开(公告)日：2002-12-31
申请号：US10007846
申请日：2001-11-05
申请人： Carl J. Radens , Gary B. Bronner , Ramachandra Divakaruni , Jack A. Mandelman
发明人： Carl J. Radens , Gary B. Bronner , Ramachandra Divakaruni , Jack A. Mandelman
IPC分类号： H01L27108
CPC分类号： H01L27/11 , G11C11/404 , H01L27/10841 , H01L27/10864 , H01L27/10867 , H01L29/945
摘要： A DRAM cell storage capacitor is formed above the bottom of a deep trench (DT) below an FET transistor. The DT has upper, central and lower portions with sidewalls. A capacitor plate electrode, surrounding the lower DT portion that is doped with a first dopant type, is separated by an interface from a well region surrounding the upper and central portions of the DT that are doped with an opposite dopant type. A source/drain region formed at the top of the cell is doped with the first dopant type. A node dielectric layer that covers the sidewalls and bottom of the lower and central portions of the DT is filled with a node electrode of the capacitor, doped with the first dopant type, fills the space inside the node dielectric layer in the lower part of the DT. Above a recessed node dielectric layer a strap region space is filled with a buried-strap conductor. An oxide (TTO) layer is formed over the node electrode and the buried-strap in the DT. A peripheral gate oxide layer, which coats sidewalls of the DT above the TTO, defines a space which is filled with the FET gate electrode. An outdiffusion region, doped with the first dopant type, is formed in the well region near the buried-strap. The cell has a first state and an opposite state of operation. A punch-through device, formed in the well between the outdiffusion region and the interface, provides a self-refreshing punchthrough current in the cell between the well and the plate in the first state of cell operation. A reverse bias junction leakage current occurs in the cell between the buried-strap and the P-well to refresh the opposite state of cell operation.
摘要翻译：在FET晶体管下方的深沟槽（DT）的底部形成DRAM单元存储电容器。 DT具有具有侧壁的上部，中部和下部。围绕掺杂有第一掺杂剂类型的下部DT部分的电容器平板电极通过界面与围绕掺杂有相反掺杂剂类型的DT的上部和中部的阱区隔开。形成在电池顶部的源极/漏极区掺杂有第一掺杂剂类型。覆盖DT的下部和中心部分的侧壁和底部的节点电介质层填充有掺杂有第一掺杂剂类型的电容器的节点电极，填充第一掺杂剂类型的下部的节点电介质层内部的空间 DT。在凹陷节点电介质层上方，带区域空间填充有埋地导体。在DT上的节点电极和掩埋带上形成氧化物（TTO）层。在TTO上方覆盖DT的侧壁的外围栅极氧化物层限定了用FET栅电极填充的空间。在掩埋带附近的阱区中形成掺杂有第一掺杂剂类型的扩散区。电池具有第一状态和相反的操作状态。形成在扩散区域和界面之间的井中的穿通装置在电池操作的第一状态下在孔和板之间的电池单元中提供自刷新穿透电流。在埋层和P阱之间的电池中产生反向偏置结漏电流，以刷新电池操作的相反状态。

24. 发明授权

US06284593B1 Method for shallow trench isolated, contacted well, vertical MOSFET DRAM 失效
标题翻译：浅沟槽隔离方法，接触良好，垂直MOSFET DRAM
公开(公告)号：US06284593B1
公开(公告)日：2001-09-04
申请号：US09705652
申请日：2000-11-03
申请人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens
发明人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L27/10867
摘要： A process of forming a hybrid memory cell which is scalable to a minimum feature size, F, of about 60 nm at an operating voltage of Vblh of about 1.5 V and substantially free of floating-well effects is provided.
摘要翻译：提供了形成混合存储器单元的过程，该混合存储器单元在约1.5V的Vblh的工作电压下可扩展到约60nm的最小特征尺寸F，并且基本上没有浮动阱效应。

25. 发明申请

US20090047756A1 DUAL PORT GAIN CELL WITH SIDE AND TOP GATED READ TRANSISTOR 失效
标题翻译：双端口增益单元与侧面和顶部读取晶体管
公开(公告)号：US20090047756A1
公开(公告)日：2009-02-19
申请号：US12254960
申请日：2008-10-21
申请人： Jack A. Mandelman , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Geng Wang
发明人： Jack A. Mandelman , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Geng Wang
IPC分类号： H01L21/84 , H01L21/8242
CPC分类号： H01L27/108 , H01L27/10829 , H01L27/10867 , H01L27/1203
摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.
摘要翻译：使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。各种增益单元布局在本领域中是已知的。本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

26. 发明授权

US07459743B2 Dual port gain cell with side and top gated read transistor 有权
标题翻译：双端口增益单元，具有侧和顶栅控读取晶体管
公开(公告)号：US07459743B2
公开(公告)日：2008-12-02
申请号：US11161962
申请日：2005-08-24
申请人： Jack A. Mandelman , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Geng Wang
发明人： Jack A. Mandelman , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Geng Wang
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/108 , H01L27/10829 , H01L27/10867 , H01L27/1203
摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.
摘要翻译：使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。各种增益单元布局在本领域中是已知的。本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

27. 发明授权

US06693041B2 Self-aligned STI for narrow trenches 失效
标题翻译：用于窄沟槽的自对准STI
公开(公告)号：US06693041B2
公开(公告)日：2004-02-17
申请号：US09885790
申请日：2001-06-20
申请人： Ramachandra Divakaruni , Jack A. Mandelman , Carl J. Radens
发明人： Ramachandra Divakaruni , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L21311
CPC分类号： H01L27/10867 , H01L21/76232 , H01L21/76235 , H01L27/0207 , H01L27/10864
摘要： A self-aligned shallow trench isolation region for a memory cell array is formed by etching a plurality of vertical deep trenches in a substrate and coating the trenches with an oxidation barrier layer. The oxidation barrier layer is recessed in portions of the trenches to expose portions of the substrate in the trenches. The exposed portions of the substrate are merged by oxidization into thermal oxide regions to form the self-aligned shallow trench isolation structure which isolates adjacent portions of substrate material. The merged oxide regions are self-aligned as they automatically aligned to the edges of the deep trenches when merged together to define the location of the isolation region within the memory cell array during IC fabrication. The instant self-aligned shallow trench isolation structure avoids the need for an isolation mask to separate or isolate the plurality of trenches within adjacent active area rows on a single substrate.
摘要翻译：通过蚀刻衬底中的多个垂直深沟槽并用氧化阻挡层涂覆沟槽，形成用于存储单元阵列的自对准浅沟槽隔离区。氧化阻挡层凹陷在沟槽的部分中以暴露沟槽中的衬底的部分。衬底的暴露部分通过氧化合并成热氧化物区域，以形成隔离衬底材料的相邻部分的自对准浅沟槽隔离结构。合并的氧化物区域是自对准的，因为它们在合成时自动对准深沟槽的边缘，以在IC制造期间限定存储单元阵列内的隔离区域的位置。瞬时自对准浅沟槽隔离结构避免了需要隔离掩模以在单个衬底上的相邻有效区域行内分离或隔离多个沟槽。

28. 发明授权

US06426526B1 Single sided buried strap 失效
标题翻译：单面埋地带
公开(公告)号：US06426526B1
公开(公告)日：2002-07-30
申请号：US09870068
申请日：2001-05-30
申请人： Ramachandra Divakaruni , Jack A. Mandelman , Gary B. Bronner , Carl J. Radens
发明人： Ramachandra Divakaruni , Jack A. Mandelman , Gary B. Bronner , Carl J. Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10864
摘要： An easily manufactured connecting structure from a node conductor of trench capacitor device is characterized at least in part by the presence of an isolation collar located above the node conductor, at least a portion of the collar having an exterior surface which is substantially conformal with at least a portion of an adjacent wall of the trench, a buried strap region in the trench above the node conductor, the strap region being bounded laterally by the isolation collar except at an opening in the collar. The connecting structure is preferably formed by a method involving clearing an isolation collar from a first interior surface of a deep trench at a location above a storage capacitor while leaving the isolation collar at other surfaces of the deep trench.
摘要翻译：至少部分地由位于节点导体上方的隔离套管的存在而将来自沟槽电容器装置的节点导体的容易制造的连接结构的特征在于，所述套环的至少一部分具有至少基本上保形的外表面沟槽的相邻壁的一部分，在节点导体上方的沟槽中的掩埋带区域，除了在套环的开口处之外，带区域被隔离套环侧向限定。连接结构优选地通过一种方法来形成，该方法包括在存储电容器上方的位置处从深沟槽的第一内表面清除隔离套环，同时将隔离套环留在深沟槽的其他表面。

29. 发明授权

US06376324B1 Collar process for reduced deep trench edge bias 失效
标题翻译：用于减小深沟槽边缘偏置的套圈过程
公开(公告)号：US06376324B1
公开(公告)日：2002-04-23
申请号：US09602969
申请日：2000-06-23
申请人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Ulrike Gruening , Akira Sudo
发明人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Ulrike Gruening , Akira Sudo
IPC分类号： H01L2120
CPC分类号： H01L27/10867
摘要： Disclosed is a method to provide a new deep trench collar process which reduces encroachment of strap diffusion upon array metal oxide semiconductor field effect transistors (MOSFET's) in semiconductor devices. The invention allows a reduced effective deep trench edge bias at the top of the deep trench, without compromising storage capacitance, by maximizing the distance between the MOSFET gate conductor and the deep trench storage capacitor.
摘要翻译：公开了一种提供新的深沟槽套环工艺的方法，其减少了半导体器件中的阵列金属氧化物半导体场效应晶体管（MOSFET）上带扩散的侵入。通过使MOSFET栅极导体和深沟槽存储电容器之间的距离最大化，本发明允许在深沟槽顶部减少有效的深沟槽边缘偏压，而不损害存储电容。

30. 发明授权

US06348374B1 Process for 4F2 STC cell having vertical MOSFET and buried-bitline conductor structure 失效
标题翻译：具有垂直MOSFET和埋地位线导体结构的4F2 STC电池的工艺
公开(公告)号：US06348374B1
公开(公告)日：2002-02-19
申请号：US09597887
申请日：2000-06-19
申请人： Satish D. Athavale , Gary B. Bronner , Ramachandra Divakaruni , Ulrike Gruening , Jack A. Mandelman , Carl J. Radens
发明人： Satish D. Athavale , Gary B. Bronner , Ramachandra Divakaruni , Ulrike Gruening , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L218242
CPC分类号： H01L27/10876 , H01L27/10814 , H01L27/10823 , H01L27/10885
摘要： A method of forming a vertical transistor. A pad layer is formed over a semiconductor substrate. A trough is formed through the pad layer and in the semiconductor substrate. A bit line is formed buried in the trough. The bit line is enclosed by a dielectric material. A strap is formed extending through the dielectric material to connect the bit line to the semiconductor substrate. The trough is filled above the bit line with a conductor. The conductor is cut along its longitudinal axis such that the conductor remains on one side of the trough. Wordline troughs are formed, substantially orthogonal to the bit line, above the semiconductor substrate. A portion of the conductor is removed under the wordline trough to separate the conductor into separate gate conductors. Wordlines are formed in the wordline trough connected to the separate gate conductors.
摘要翻译：一种形成垂直晶体管的方法。在半导体衬底上形成衬垫层。通过焊盘层和半导体衬底形成槽。埋在槽中的位线形成。位线被电介质材料包围。形成延伸穿过介电材料的带，以将位线连接到半导体衬底。槽被填充在位线上方的导体。导体沿其纵向轴线切割，使得导体保持在槽的一侧。在半导体衬底之上形成基本上与位线正交的字线槽。导体的一部分在字线槽下移除，以将导体分离成单独的栅极导体。字线形成在连接到单独的栅极导体的字线槽中。

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