专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US6002169A Thermally enhanced tape ball grid array package 失效
标题翻译：热增强胶带球栅阵列封装
公开(公告)号：US6002169A
公开(公告)日：1999-12-14
申请号：US97883
申请日：1998-06-15
申请人： Chok J. Chia , Seng-Sooi Lim , Owai H. Low
发明人： Chok J. Chia , Seng-Sooi Lim , Owai H. Low
IPC分类号： H01L23/31 , H01L23/48 , H01L23/053 , H01L23/12
CPC分类号： H01L23/3128 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/181
摘要： A semiconductor package (110) includes a tape substrate (135) having a top surface, a bottom surface, a plurality of conductive metal traces (115) formed on the top surface and a plurality of holes (130) arraigned in an array pattern formed through the tape substrate (135) exposing the conductive traces (115) from the bottom surface. A nonconductive metal plate or stiffener frame (155) attached to the bottom surface of the tape substrate (135) to support the tape substrate (135) during assembly. The stiffener frame (155) having through holes (160) corresponding to the holes (130) in the tape substrate (135) and being made from anodized aluminum, thus making it electrically nonconductive. An integrated circuit (IC) chip (120) is mounted on the top surface, opposite the stiffener frame (155). The IC chip (120) is in electrical connection to the traces (115) and a plurality of solder balls (125) are attached to the traces (115) through the holes (130 and 160), electrically connecting the semiconductor package (110) to a printed circuit board (170). Along with providing support for the tape substrate (135) during assembly, the stiffener frame (155) is used to improve the thermal performance of the semiconductor package (110) by dissipating the heat generated by the IC die (120) and improving the flatness of the finished semiconductor package (110).
摘要翻译：半导体封装（110）包括具有顶表面，底表面，形成在顶表面上的多个导电金属迹线（115）的带基片（135）和形成阵列图形的多个孔（130）通过从底表面暴露导电迹线（115）的带基片（135）。附接到带基片（135）的底表面以在组装期间支撑带基片（135）的非导电金属板或加强框架（155）。加强框架（155）具有对应于带基材（135）中的孔（130）的通孔（160）并且由阳极氧化的铝制成，从而使其不导电。集成电路（IC）芯片（120）安装在与加强框架（155）相对的顶表面上。 IC芯片（120）与迹线（115）电连接，并且多个焊球（125）通过孔（130和160）附接到迹线（115），电连接半导体封装（110）到印刷电路板（170）。随着在组装期间提供对带基板（135）的支撑，加强框架（155）用于通过消散IC模具（120）产生的热量来提高半导体封装（110）的热性能并提高其平坦度的成品半导体封装（110）。

22. 发明授权

US5744084A Method of improving molding of an overmolded package body on a substrate 失效
标题翻译：改善在基材上包覆成型的封装体成型的方法
公开(公告)号：US5744084A
公开(公告)日：1998-04-28
申请号：US506164
申请日：1995-07-24
申请人： Chok J. Chia , Seng-Sooi Lim , Maniam Alagaratnam
发明人： Chok J. Chia , Seng-Sooi Lim , Maniam Alagaratnam
IPC分类号： B29C45/14 , H01L21/56 , H01L23/31 , B29C70/70
CPC分类号： B29C45/14418 , B29C45/14655 , H01L21/565 , H01L23/3121 , B29C2045/14934 , B29C70/72 , B29C70/78 , H01L2924/0002
摘要： Substrates having a wide range of thickness, and intended to be overmolded with a plastic package body, are accommodated in a common mold. The top surface of the substrate is provided with a dam structure, which may be formed as an additional layer on the substrate, and which is preferably in the form of a square ring. A groove (channel) is machined (e.g., by routing) into the surface of the dam structure. The top mold half, having a cavity for forming the package body, is provided with a sealing structure at the periphery of the cavity. The sealing structure has a ridge fitting into the channel of the dam structure. The depth of the groove in the dam structure is readily adjusted to ensure uniform clamping pressure of the top mold half on the substrate, so that liquid molding compound is contained within the cavity and so that undue pressure is not exerted on the substrate.
摘要翻译：具有宽范围厚度并且旨在用塑料封装体包覆成型的基板容纳在共同的模具中。衬底的顶表面设置有坝结构，其可以在衬底上形成为附加层，并且其优选地为正方形环的形式。槽（通道）被加工（例如通过路由）到坝结构的表面中。具有用于形成封装主体的空腔的顶部模具半部在空腔的周边处设置有密封结构。密封结构具有嵌入坝结构通道的脊。容易调节坝结构中槽的深度，以确保上模半部在基板上的均匀夹紧压力，使得液体模塑料被包含在空腔内，从而不会对衬底施加过大的压力。

23. 发明授权

US5643835A Process for manufacturing and mounting a semiconductor device leadframe having alignment tabs 失效
标题翻译：用于制造和安装具有对准翼片的半导体器件引线框架的工艺
公开(公告)号：US5643835A
公开(公告)日：1997-07-01
申请号：US602896
申请日：1996-02-16
申请人： Chok J. Chia , Seng-Sooi Lim
发明人： Chok J. Chia , Seng-Sooi Lim
IPC分类号： H01L23/495 , H05K3/30 , H05K3/34 , H01L21/56 , H01L21/58 , H01L21/60
CPC分类号： H05K3/303 , H01L23/49541 , H01L2224/48091 , H01L2224/48247 , H05K2201/10303 , H05K2201/10659 , H05K2201/10689 , H05K2201/10962 , H05K2203/167 , H05K3/3421 , Y02P70/613 , Y10S438/975 , Y10T29/49121 , Y10T29/49133
摘要： A process of mounting a semiconductor device and leadframe to a printed circuit board are described. The device has a body, and a plurality of leads extending from the body. One or more alignment features are formed on the exterior of the package body, for maintaining precise alignment of the device with respect to a printed wiring board. The alignment feature is a tab formed as part of portion of the leadframe external to the package body. The tab may have various shapes, and may be provided with a hole for registering with a pin on an underlying substrate, such as a printed wiring board. The pin and the tab may be electrically connected.
摘要翻译：描述了将半导体器件和引线框架安装到印刷电路板的工艺。该装置具有主体和从主体延伸的多个引线。一个或多个对准特征形成在包装体的外部上，以保持装置相对于印刷线路板的精确对准。对准特征是形成为包装体外部的引线框架的一部分的突片。突片可以具有各种形状，并且可以设置有用于与诸如印刷线路板的下面的基板上的销对准的孔。引脚和突片可以电连接。

24. 发明授权

US5594626A Partially-molded, PCB chip carrier package for certain non-square die shapes 失效
标题翻译：部分模制，PCB芯片载体封装，用于某些非正方形模具形状
公开(公告)号：US5594626A
公开(公告)日：1997-01-14
申请号：US432535
申请日：1995-05-02
申请人： Michael D. Rostoker , Chok J. Chia , Seng-Sooi Lim
发明人： Michael D. Rostoker , Chok J. Chia , Seng-Sooi Lim
IPC分类号： G03F7/20 , H01L23/31 , H01L23/495 , H01L23/498 , H01L29/06 , H05K1/11
CPC分类号： G03F7/70433 , H01L23/3121 , H01L23/315 , H01L23/49503 , H01L23/49517 , H01L23/49541 , H01L23/49558 , H01L23/49861 , H01L24/06 , H01L24/49 , H01L2224/04042 , H01L2224/05554 , H01L2224/05599 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/49109 , H01L2224/49175 , H01L24/48 , H01L29/0657 , H01L2924/00014 , H01L2924/01014 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/10155 , H01L2924/14 , H01L2924/15151 , H01L2924/15787 , H01L2924/181 , H01L2924/18301
摘要： A dambar-less leadframe is sandwiched between two printed circuit boards (PCBs). The PCBs form a major portion of the package body, and isolate the leadframe leads from plastic molding compound. In one embodiment, an upper PCB (substrate) is formed as a ring, having an opening containing a heat sink element. A lower PCB is also formed as a ring, and has a smaller opening for receiving a die. The back face of the die is mounted to the heat sink. The exposed front face of the die is wire bonded to inner ends of conductive traces on the exposed face of the lower PCB. The outer ends of the traces are electrically connected to the leadframe leads by plated-through vias extending through the two PCBs. The plated-through vias additionally secure the sandwich structure together. Plastic molding compound is injection/transfer molded over the front face of the die and the bond wires, forming a partially-molded package. In another embodiment, the upper PCB is a solid planar element. The back face of the die is mounted to the inside surface of the upper PCB. The die, die-receiving area, and/or package body shape have a "certain non-square" shape (i.e., triangle, trapezoid, parallelogram, greatly-elongated rectangle, etc.).
摘要翻译：两个印刷电路板（PCB）之间夹有无阻挡引线框架。 PCB形成封装主体的主要部分，并将引线框引线与塑料模塑料隔离。在一个实施例中，上PCB（基板）形成为环，具有包含散热元件的开口。下部PCB也形成为环，并且具有用于接收管芯的较小开口。模具的背面安装在散热片上。模具的暴露的前表面被焊接到下PCB的暴露表面上的导电迹线的内端。迹线的外端通过延伸穿过两个PCB的镀通孔电连接到引线框引线。电镀通孔另外将夹层结构固定在一起。塑料模塑料在模具的前表面和接合线上注射/转移模塑，形成部分模塑包装。在另一实施例中，上PCB是固体平面元件。模具的背面安装到上PCB的内表面。模具，模具接收区域和/或包装体形状具有“一定的非正方形”形状（即，三角形，梯形，平行四边形，大大细长的矩形等）。

25. 发明授权

US06963138B2 Dielectric stack 有权
标题翻译：电介质堆
公开(公告)号：US06963138B2
公开(公告)日：2005-11-08
申请号：US10357142
申请日：2003-02-03
申请人： Qwai H. Low , Chok J. Chia , Ramaswamy Ranganathan , Tauman T. Lau
发明人： Qwai H. Low , Chok J. Chia , Ramaswamy Ranganathan , Tauman T. Lau
IPC分类号： H01L23/485 , H01L23/532 , H01L23/48
CPC分类号： H01L24/05 , H01L23/53295 , H01L2224/05093 , H01L2224/05556 , H01L2224/05624 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/04953 , H01L2924/14 , H01L2924/181 , H01L2924/30105 , H01L2924/00
摘要： An integrated circuit with a pressure resistant current carrying structure having electrically conductive layers for carrying current. A first electrically nonconductive material at least partially surrounds the electrically conductive layers, and provides electrical insulation between the electrically conductive layers. The first electrically nonconductive material has a first degree of fragility and a first dielectric constant. A second electrically nonconductive material is disposed in a pattern within the first electrically nonconductive material and between the electrically conductive layers, and provides structural support for the first electrically nonconductive material between the electrically conductive layers. The second electrically nonconductive material has a second degree of fragility that is less than the first degree of fragility and a second dielectric constant that is greater than the first dielectric constant.
摘要翻译：一种具有耐压载流结构的集成电路，其具有用于承载电流的导电层。第一非导电材料至少部分地围绕导电层，并且在导电层之间提供电绝缘。第一非导电材料具有第一程度的脆性和第一介电常数。第二非导电材料以第一非导电材料内部和导电层之间的图案设置，并为导电层之间的第一非导电材料提供结构支撑。第二非导电材料具有小于第一脆性程度的第二脆性程度和大于第一介电常数的第二介电常数。

26. 发明授权

US08963310B2 Low cost hybrid high density package 有权
标题翻译：低成本混合高密度封装
公开(公告)号：US08963310B2
公开(公告)日：2015-02-24
申请号：US13216918
申请日：2011-08-24
申请人： Kishor Desai , Qwai H. Low , Chok J. Chia , Charles G. Woychik , Huailiang Wei
发明人： Kishor Desai , Qwai H. Low , Chok J. Chia , Charles G. Woychik , Huailiang Wei
IPC分类号： H01L23/495 , H01L23/02 , H01L23/48 , H01L23/498 , H01L21/56 , H01L23/31 , H01L23/00
CPC分类号： H01L23/49575 , H01L21/568 , H01L23/3128 , H01L23/3135 , H01L23/481 , H01L23/4951 , H01L23/4952 , H01L23/49531 , H01L23/49541 , H01L23/49548 , H01L23/49551 , H01L23/49811 , H01L23/49827 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L25/50 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/48247 , H01L2224/48464 , H01L2224/73215 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06558 , H01L2225/06562 , H01L2225/06568 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A microelectronic assembly includes a substrate, a first and second microelectronic elements, a lead finger, electrical connections extending between contacts of the second microelectronic element and the lead fingers, and an encapsulant overlying at least portions of the first and second microelectronic elements, lead finger and electrical connections. The substrate has contacts at a first surface and terminals at an opposed second surface that are electrically connected with the substrate contacts. The first microelectronic element has contacts exposed at its front face. The front face of the first microelectronic element is joined to the substrate contacts. The second microelectronic element overlies the first microelectronic element and has contacts at a front face facing away from the substrate. The lead frame has lead fingers, wherein the second surface of the substrate and the lead fingers define a common interface for electrical interconnection to a component external to the microelectronic assembly.
摘要翻译：微电子组件包括衬底，第一和第二微电子元件，引线指，在第二微电子元件的触点和引线指之间延伸的电连接，以及覆盖第一和第二微电子元件的至少一部分的引线指和电气连接。基板在第一表面具有接触，在相对的第二表面具有与基板触点电连接的端子。第一微电子元件在其前面具有暴露的触点。第一微电子元件的正面连接到基板触点。第二微电子元件覆盖第一微电子元件并且在面向背离衬底的前面具有接触。引线框架具有引线指，其中基板的第二表面和引线指限定用于与微电子组件外部的部件的电互连的公共接口。

27. 发明申请

US20130049179A1 LOW COST HYBRID HIGH DENSITY PACKAGE 有权
公开(公告)号：US20130049179A1
公开(公告)日：2013-02-28
申请号：US13216918
申请日：2011-08-24
申请人： Kishor Desai , Qwai H. Low , Chok J. Chia , Charles G. Woychik , Huailiang Wei
发明人： Kishor Desai , Qwai H. Low , Chok J. Chia , Charles G. Woychik , Huailiang Wei
IPC分类号： H01L23/495 , H01L21/60
CPC分类号： H01L23/49575 , H01L21/568 , H01L23/3128 , H01L23/3135 , H01L23/481 , H01L23/4951 , H01L23/4952 , H01L23/49531 , H01L23/49541 , H01L23/49548 , H01L23/49551 , H01L23/49811 , H01L23/49827 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L25/50 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/48247 , H01L2224/48464 , H01L2224/73215 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06558 , H01L2225/06562 , H01L2225/06568 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A microelectronic assembly includes a substrate, a first and second microelectronic elements, a lead finger, electrical connections extending between contacts of the second microelectronic element and the lead fingers, and an encapsulant overlying at least portions of the first and second microelectronic elements, lead finger and electrical connections. The substrate has contacts at a first surface and terminals at an opposed second surface that are electrically connected with the substrate contacts. The first microelectronic element has contacts exposed at its front face. The front face of the first microelectronic element is joined to the substrate contacts. The second microelectronic element overlies the first microelectronic element and has contacts at a front face facing away from the substrate. The lead frame has lead fingers, wherein the second surface of the substrate and the lead fingers define a common interface for electrical interconnection to a component external to the microelectronic assembly.

28. 发明授权

US06743979B1 Bonding pad isolation 有权
标题翻译：粘接垫隔离
公开(公告)号：US06743979B1
公开(公告)日：2004-06-01
申请号：US10652453
申请日：2003-08-29
申请人： Michael J. Berman , Aftab Ahmad , Qwai H. Low , Chok J. Chia , Ramaswamy Ranganathan
发明人： Michael J. Berman , Aftab Ahmad , Qwai H. Low , Chok J. Chia , Ramaswamy Ranganathan
IPC分类号： H05K506
CPC分类号： H01L24/06 , H01L24/05 , H01L2224/04042 , H01L2224/05554 , H01L2224/05556 , H01L2224/05599 , H01L2224/48091 , H01L2224/48227 , H01L2224/48463 , H01L2224/49431 , H01L2224/85399 , H01L2924/00014 , H01L2924/01033 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2224/45099 , H01L2924/00012
摘要： An integrated circuit, including a substrate with circuitry formed therein, where the substrate has a peripheral edge. Also included are a top most electrically conductive layer and an underlying electrically conductive layer. Outer bonding pads are disposed in an outer ring, and are formed within the top most layer. Inner bonding pads are disposed in an inner ring, and are formed within the top most layer. Inner connectors electrically connect the inner bonding pads to the circuitry. The inner connectors are formed within the underlying layer, and have a width that is less than the width of the inner bonding pads, thereby defining a gap between the inner connectors. Outer connectors electrically connect the outer bonding pads to the circuitry. The outer connectors are formed within the underlying layer, and have a width that is less than the width of the gap between the inner connectors.
摘要翻译：一种集成电路，包括其中形成有电路的衬底，其中衬底具有外围边缘。还包括最顶层的导电层和底层导电层。外部接合焊盘设置在外圈中，并形成在最上层。内部接合焊盘设置在内圈中，并且形成在最顶层内。内部连接器将内部接合焊盘电连接到电路。内部连接器形成在下面的层中，并且具有小于内部焊盘的宽度的宽度，由此限定内部连接器之间的间隙。外部连接器将外部接合焊盘电连接到电路。外部连接器形成在下面的层中，并且具有小于内部连接器之间的间隙的宽度的宽度。

29. 发明授权

US06489571B1 Molded tape ball grid array package 有权
标题翻译：成型带球网格阵列包装
公开(公告)号：US06489571B1
公开(公告)日：2002-12-03
申请号：US09703199
申请日：2000-10-31
申请人： Chok J. Chia , Qwai H. Low , Patrick Variot
发明人： Chok J. Chia , Qwai H. Low , Patrick Variot
IPC分类号： H05K109
CPC分类号： H01L23/3128 , H01L23/49816 , H01L23/4985 , H01L24/48 , H01L24/49 , H01L2224/05599 , H01L2224/32225 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/14 , H01L2924/15173 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： A molded tape ball grid array package includes a molding compound and a tape substrate having a top surface for mounting a die thereon, a bottom surface for attaching solder balls, and vias for forming connections between the solder balls and the die wherein the molding compound surrounds the die and the tape substrate.
摘要翻译：模塑带状球栅阵列封装包括模塑料和具有用于在其上安装模具的顶表面的带基材，用于附接焊球的底表面和用于形成焊球和模之间的连接的通孔，其中模塑料围绕模具和胶带基材。

30. 发明授权

US6143586A Electrostatic protected substrate 失效
标题翻译：静电保护基材
公开(公告)号：US6143586A
公开(公告)日：2000-11-07
申请号：US97882
申请日：1998-06-15
申请人： Chok J. Chia , Patrick Variot , Qwai H. Low
发明人： Chok J. Chia , Patrick Variot , Qwai H. Low
IPC分类号： H01L23/60 , H01L21/44 , H01L21/331 , H01L21/336 , H01L21/48 , H01L21/50 , H01L21/82 , H01L31/479
CPC分类号： H01L23/60 , H01L2224/05599 , H01L2224/48091 , H01L2224/48227 , H01L2224/85399 , H01L24/48 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/14
摘要： An electrostatic protected integrated circuit (IC) substrate and a method of making an integrated circuit package with the electrostatic protected IC substrate includes an IC substrate, having a plurality of electrical traces formed on the top of the IC substrate with the electrical traces extending from an IC chip mounting area near the center to the periphery of the IC substrate. Electrically shorting the electrical traces together with a conductive material such as conductive tape or epoxy, thereby, protecting the IC substrate against the accumulation of static charges during the assembly of the IC chip on the IC substrate. The IC chip is mounted in the mounting area on the IC substrate and the conductive material is removed before final testing.
摘要翻译：静电保护集成电路（IC）衬底和制造具有静电保护IC衬底的集成电路封装的方法包括IC衬底，其具有形成在IC衬底的顶部上的多个电迹线，电迹线从 IC芯片安装区域靠近IC基板周围的中心。将导电电路与导电胶带或环氧树脂等导电材料电气短路，从而在集成电路芯片集成在IC基板上时，保护IC基板免受静电荷的积累。 IC芯片安装在IC基板上的安装区域，导电材料在最终测试之前被去除。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式