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21. 发明申请

US20080032513A1 INTEGRATED CIRCUIT SYSTEM INCLUDING NITRIDE LAYER TECHNOLOGY 有权
标题翻译：集成电路系统，包括氮化层技术
公开(公告)号：US20080032513A1
公开(公告)日：2008-02-07
申请号：US11428618
申请日：2006-07-05
申请人： Sripad Sheshagiri Nagarad , Hwa Weng Koh , Dong Kyun Sohn , Xiaoyu Chen , Louis Lim , Sung Mun Jung , Chiew Wah Yap , Pradeep Ramachandramurthy Yelehanka , Nitin Kamat
发明人： Sripad Sheshagiri Nagarad , Hwa Weng Koh , Dong Kyun Sohn , Xiaoyu Chen , Louis Lim , Sung Mun Jung , Chiew Wah Yap , Pradeep Ramachandramurthy Yelehanka , Nitin Kamat
IPC分类号： H01L21/31
CPC分类号： H01L21/3185 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02271 , H01L27/105 , H01L27/11568 , H01L27/11573
摘要： An integrated circuit system including loading a wafer into a processing chamber and pre-purging the processing chamber with a first ammonia gas. Depositing a first nitride layer over the wafer and purging the processing chamber with a second ammonia gas. Depositing a second nitride layer over the first nitride layer that is misaligned with the first nitride layer. Post-purging the processing chamber with a third ammonia gas and purging the processing chamber with a nitrogen gas.
摘要翻译：一种集成电路系统，包括将晶片装载到处理室中并用第一氨气预处理室。在晶片上沉积第一氮化物层并用第二氨气吹扫处理室。在与第一氮化物层不对准的第一氮化物层上沉积第二氮化物层。用第三氨气对处理室进行后吹扫，并用氮气吹扫处理室。

22. 发明授权

US07029976B1 Method for SONOS EFLASH integrated circuit 失效
标题翻译： SONOS EFLASH集成电路方法
公开(公告)号：US07029976B1
公开(公告)日：2006-04-18
申请号：US11041051
申请日：2005-01-21
申请人： Sripad Sheshagiri Nagarad , Dong Kyun Sohn , Yoke Leng Louis Lim , Siow Lee Chwa , Hsiang Fang Lim
发明人： Sripad Sheshagiri Nagarad , Dong Kyun Sohn , Yoke Leng Louis Lim , Siow Lee Chwa , Hsiang Fang Lim
IPC分类号： H01L21/8247
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573 , Y10S438/954
摘要： A method of manufacturing a charge storage layer for a SONOS memory device. A feature of the embodiment is the first gate layer is formed over the charge storing layer (ONO) before the charge storing layer is patterned. The first gate layer protects the charge storing layer (ONO) from various etches used in the process to pattern the various gate dielectric layers on other regions of substrate.
摘要翻译：一种制造用于SONOS存储器件的电荷存储层的方法。本实施例的特征是在对电荷存储层进行图案化之前，在电荷存储层（ONO）上形成第一栅极层。第一栅极层保护电荷存储层（ONO）免受在该工艺中使用的各种蚀刻，以对衬底的其它区域上的各种栅极电介质层进行图案化。

23. 发明申请

US20130034954A1 INTEGRATED CIRCUIT SYSTEM INCLUDING NITRIDE LAYER TECHNOLOGY 审中-公开
标题翻译：集成电路系统，包括氮化层技术
公开(公告)号：US20130034954A1
公开(公告)日：2013-02-07
申请号：US13647339
申请日：2012-10-08
申请人： Sripad Sheshagiri Nagarad , Hwa Weng Koh , Dong Kyun Sohn , Xiaoyu Chen , Louis Lim , Sung Mun Jung , Chiew Wah Yap , Pradeep Ramachandramurthy Yelehanka , Nitin Kamat
发明人： Sripad Sheshagiri Nagarad , Hwa Weng Koh , Dong Kyun Sohn , Xiaoyu Chen , Louis Lim , Sung Mun Jung , Chiew Wah Yap , Pradeep Ramachandramurthy Yelehanka , Nitin Kamat
IPC分类号： H01L21/283
CPC分类号： H01L21/3185 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02271 , H01L27/105 , H01L27/11568 , H01L27/11573
摘要： An integrated circuit method for manufacturing an integrated circuit system including loading a wafer into a processing chamber and pre-purging the processing chamber with a first ammonia gas. Depositing a first nitride layer over the wafer and purging the processing chamber with a second ammonia gas. Depositing a second nitride layer over the first nitride layer that is misaligned with the first nitride layer. Post-purging the processing chamber with a third ammonia gas and purging the processing chamber with a nitrogen gas.
摘要翻译：一种用于制造集成电路系统的集成电路方法，该集成电路系统包括将晶片装载到处理室中并用第一氨气预处理室。在晶片上沉积第一氮化物层并用第二氨气吹扫处理室。在与第一氮化物层不对准的第一氮化物层上沉积第二氮化物层。用第三氨气对处理室进行后吹扫，并用氮气吹扫处理室。

24. 发明授权

US08283263B2 Integrated circuit system including nitride layer technology 有权
标题翻译：集成电路系统包括氮化层技术
公开(公告)号：US08283263B2
公开(公告)日：2012-10-09
申请号：US11428618
申请日：2006-07-05
申请人： Sripad Sheshagiri Nagarad , Hwa Weng Koh , Dong Kyun Sohn , Xiaoyu Chen , Louis Lim , Sung Mun Jung , Chiew Wah Yap , Pradeep Ramachandramurthy Yelehanka , Nitin Kamat
发明人： Sripad Sheshagiri Nagarad , Hwa Weng Koh , Dong Kyun Sohn , Xiaoyu Chen , Louis Lim , Sung Mun Jung , Chiew Wah Yap , Pradeep Ramachandramurthy Yelehanka , Nitin Kamat
IPC分类号： H01L21/469
CPC分类号： H01L21/3185 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02271 , H01L27/105 , H01L27/11568 , H01L27/11573
摘要： An integrated circuit method for manufacturing an integrated circuit system including loading a wafer into a processing chamber and pre-purging the processing chamber with a first ammonia gas. Depositing a first nitride layer over the wafer and purging the processing chamber with a second ammonia gas. Depositing a second nitride layer over the first nitride layer that is misaligned with the first nitride layer. Post-purging the processing chamber with a third ammonia gas and purging the processing chamber with a nitrogen gas.
摘要翻译：一种用于制造集成电路系统的集成电路方法，该集成电路系统包括将晶片装载到处理室中并用第一氨气预处理室。在晶片上沉积第一氮化物层并用第二氨气吹扫处理室。在与第一氮化物层不对准的第一氮化物层上沉积第二氮化物层。用第三氨气对处理室进行后吹扫，并用氮气吹扫处理室。

25. 发明申请

US20100230744A1 RELIABLE MEMORY CELL 有权
标题翻译：可靠的内存单元
公开(公告)号：US20100230744A1
公开(公告)日：2010-09-16
申请号：US12401622
申请日：2009-03-11
申请人： Timothy Phua , Bangun Indajang , Dong Kyun Sohn
发明人： Timothy Phua , Bangun Indajang , Dong Kyun Sohn
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/7881 , H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/42332 , H01L29/66825
摘要： A method of forming a semiconductor device is presented. A substrate prepared with a second gate is provided. The second gate is processed to form a second gate with a rounded corner and a first gate is formed on the substrate. The first gate is adjacent to and overlaps a portion of the second gate and the rounded corner.
摘要翻译：提出了一种形成半导体器件的方法。提供了用第二栅极制备的衬底。处理第二栅极以形成具有圆角的第二栅极，并且在基板上形成第一栅极。第一门与第二门和圆角的一部分相邻并重叠。

26. 发明授权

US06528401B2 Method for fabricating polycide dual gate in semiconductor device 有权
标题翻译：在半导体器件中制造多晶硅双栅极的方法
公开(公告)号：US06528401B2
公开(公告)日：2003-03-04
申请号：US09735544
申请日：2000-12-14
申请人： Jong Uk Bae , Ji Soo Park , Dong Kyun Sohn
发明人： Jong Uk Bae , Ji Soo Park , Dong Kyun Sohn
IPC分类号： H01L214763
CPC分类号： H01L21/823842 , H01L21/823835
摘要： Method for fabricating a polycide dual gate in a semiconductor device fabricates a dual gate having polycide gate electrodes. The polycide can be a cobalt polycide, for example. The method can include forming polysilicon pattern layers on a first and a second regions of a semiconductor substrate, forming a blocking layer to expose top surfaces of the polysilicon pattern layers and mask the substrate, and forming a metal layer on an entire surface and then is annealed to form a gate electrode having a stack of the polysilicon pattern layer under a silicide layer. Impurity ions of opposite conductivities in the first and second regions can be respectively deposited and diffused to form source/drain regions in surfaces of the substrate on both sides of the gate electrode. The implanted impurity ions can further implant ions in the silicide/polysilicon pattern layer gate to reduce fabrication steps or simplify the fabrication process.
摘要翻译：在半导体器件中制造多晶硅双栅极的方法制造具有多晶硅栅极电极的双栅极。例如，多硅化物可以是多硅化钴。该方法可以包括在半导体衬底的第一和第二区域上形成多晶硅图案层，形成阻挡层以暴露多晶硅图案层的顶表面并掩蔽衬底，并在整个表面上形成金属层，然后是退火以形成在硅化物层下方具有多晶硅图案层的堆叠的栅电极。第一和第二区域中相反电导率的杂质离子可以分别沉积并扩散，以在栅电极两侧的衬底表面形成源/漏区。注入的杂质离子可以在硅化物/多晶硅图案层栅极中进一步注入离子以减少制造步骤或简化制造工艺。

27. 发明授权

US07888214B2 Selective stress relaxation of contact etch stop layer through layout design 有权
标题翻译：通过布局设计，接触蚀刻停止层的选择性应力松弛
公开(公告)号：US07888214B2
公开(公告)日：2011-02-15
申请号：US11302035
申请日：2005-12-13
申请人： Lee Wee Teo , Elgin Quek , Dong Kyun Sohn
发明人： Lee Wee Teo , Elgin Quek , Dong Kyun Sohn
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/76816 , H01L21/76829 , H01L21/823814 , H01L21/823871 , H01L27/0207 , H01L29/665 , H01L29/6659 , H01L29/7843
摘要： A structure and method of fabrication of a semiconductor device, where a stress layer is formed over a MOS transistor to put either tensile stress or compressive stress on the channel region. The parameters such as the location and area of the contact hole thru the stress layer are chosen to produce a desired amount of stress to improve device performance. In an example embodiment for a tensile stress layer, the PMOS S/D contact area is larger than the NMOS S/D contact area so the tensile stress on the PMOS channel is less than the tensile stress on the NMOS channel. In an example embodiment for a compressive stress layer, the NMOS contact area is larger than the PMOS contact area so that the compressive stress on the NMOS channel is less than the compressive stress on the PMOS channel.
摘要翻译：一种制造半导体器件的结构和方法，其中在MOS晶体管上形成应力层以在沟道区域上施加拉伸应力或压应力。选择诸如通过应力层的接触孔的位置和面积的参数以产生期望量的应力以改善器件性能。在拉伸应力层的示例实施例中，PMOS S / D接触面积大于NMOS S / D接触面积，因此PMOS沟道上的拉伸应力小于NMOS沟道上的拉伸应力。在压应力层的示例实施例中，NMOS接触面积大于PMOS接触面积，使得NMOS沟道上的压应力小于PMOS沟道上的压应力。

28. 发明授权

US07585746B2 Process integration scheme of SONOS technology 有权
标题翻译： SONOS技术的过程集成方案
公开(公告)号：US07585746B2
公开(公告)日：2009-09-08
申请号：US11485949
申请日：2006-07-12
申请人： Sung Mun Jung , Yoke Leng Louis Lim , Sripad Nagarad , Dong Kyun Sohn , Dong Hua Liu , Xiao Yu Chen , Rachel Low
发明人： Sung Mun Jung , Yoke Leng Louis Lim , Sripad Nagarad , Dong Kyun Sohn , Dong Hua Liu , Xiao Yu Chen , Rachel Low
IPC分类号： H01L21/76
CPC分类号： H01L27/115 , H01L27/11568
摘要： In an non-limiting example, we provide a substrate having a cell region, and non-cell regions. We form a tunneling dielectric layer, a charge storing layer, a top insulating layer (e.g., ONO), over the substrate. Then we form a conductive pad layer over the top insulating layer. We form isolation trenches in the pad layer, the charge storing layer and the tunneling dielectric layer and into the substrate. We form isolation regions in the isolation trenches. We remove the pad layer, charge storing layer and the tunneling dielectric layer in the non-cell regions. We form a gate layer over the pad layer and the substrate surface. We complete to form the memory (e.g., SONOS) device in the cell region and other devices in the non-cell regions of the substrate.
摘要翻译：在非限制性实例中，我们提供具有细胞区域和非细胞区域的底物。我们在衬底上形成隧道介电层，电荷存储层，顶部绝缘层（例如ONO）。然后我们在顶部绝缘层上形成导电焊盘层。我们在焊盘层，电荷存储层和隧道电介质层中形成隔离沟槽并进入衬底。我们在隔离沟中形成隔离区。我们去除非单元区域中的焊盘层，电荷存储层和隧道介电层。我们在衬垫层和衬底表面上形成栅极层。我们完成以形成单元区域中的存储器（例如SONOS）器件和衬底的非单元区域中的其他器件。

29. 发明授权

US06885103B2 Semiconductor device including ternary phase diffusion barrier 有权
标题翻译：包括三相相位扩散屏障的半导体器件
公开(公告)号：US06885103B2
公开(公告)日：2005-04-26
申请号：US10620608
申请日：2003-07-17
申请人： Dong Kyun Sohn , Ji Soo Park , Jong Uk Bae
发明人： Dong Kyun Sohn , Ji Soo Park , Jong Uk Bae
IPC分类号： H01L21/28 , H01L21/285 , H01L21/768 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76846 , H01L21/28518 , H01L21/76843 , H01L21/76855 , H01L21/76856 , H01L21/76858
摘要： A method for manufacturing a semiconductor device can simply form a silicide film for reducing ohmic contact between a metal line and a substrate and a ternary phase thin film as an amorphous diffusion prevention film between a metal line and the silicide film. The method for manufacturing a semiconductor device includes the steps of sequentially forming a first refractory metal and a second refractory metal on a semiconductor substrate, forming a silicide film on an interface between the semiconductor substrate and the first refractory metal, and reacting the semiconductor substrate with the first and second refractory metals on the silicide film to form a ternary phase thin film.
摘要翻译：制造半导体器件的方法可以简单地形成用于在金属线和硅化物膜之间降低金属线与衬底之间的欧姆接触的硅化物膜和作为非晶扩散防止膜的三元相薄膜。制造半导体器件的方法包括以下步骤：在半导体衬底上依次形成第一难熔金属和第二难熔金属，在半导体衬底和第一难熔金属之间的界面上形成硅化物膜，并使半导体衬底与第一和第二难熔金属在硅化物膜上形成三元相薄膜。

30. 发明授权

US06649520B1 Method of forming film for reduced ohmic contact resistance and ternary phase layer amorphous diffusion barrier 有权
标题翻译：形成用于降低欧姆接触电阻的薄膜和三元相层无定形扩散屏障的方法
公开(公告)号：US06649520B1
公开(公告)日：2003-11-18
申请号：US09461767
申请日：1999-12-15
申请人： Dong Kyun Sohn , Ji Soo Park , Jong Uk Bae
发明人： Dong Kyun Sohn , Ji Soo Park , Jong Uk Bae
IPC分类号： H01L2144
CPC分类号： H01L21/76846 , H01L21/28518 , H01L21/76843 , H01L21/76855 , H01L21/76856 , H01L21/76858
摘要： A method for manufacturing a semiconductor device can simply form a silicide film for reducing ohmic contact between a metal line and a substrate and a ternary phase thin film as an amorphous diffusion prevention film between a metal line and the silicide film. The method for manufacturing a semiconductor device includes the steps of sequentially forming a first refractory metal and a second refractory metal on a semiconductor substrate, forming a silicide film on an interface between the semiconductor substrate and the first refractory metal, and reacting the semiconductor substrate with the first and second refractory metals on the silicide film to form a ternary phase thin film.
摘要翻译：制造半导体器件的方法可以简单地形成用于在金属线和硅化物膜之间降低金属线与衬底之间的欧姆接触的硅化物膜和作为非晶扩散防止膜的三元相薄膜。制造半导体器件的方法包括以下步骤：在半导体衬底上依次形成第一难熔金属和第二难熔金属，在半导体衬底和第一难熔金属之间的界面上形成硅化物膜，并使半导体衬底与第一和第二难熔金属在硅化物膜上形成三元相薄膜。

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