专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20130246824A1 Instruction For Enabling A Processor Wait State 审中-公开
标题翻译：启用处理器等待状态的指令
公开(公告)号：US20130246824A1
公开(公告)日：2013-09-19
申请号：US13891747
申请日：2013-05-10
申请人： Martin G. Dixon , Scott D. Rodgers , Taraneh Bahrami , Stephen H. Gunther , Prashant Sethi , Per Hammarlund
发明人： Martin G. Dixon , Scott D. Rodgers , Taraneh Bahrami , Stephen H. Gunther , Prashant Sethi , Per Hammarlund
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3206 , G06F1/3228 , G06F1/3293 , G06F9/30083 , G06F9/3009 , Y02D10/122 , Y02D50/20
摘要： In one embodiment, the present invention includes a processor having a core with decode logic to decode an instruction prescribing an identification of a location to be monitored and a timer value, and a timer coupled to the decode logic to perform a count with respect to the timer value. The processor may further include a power management unit coupled to the core to determine a type of a low power state based at least in part on the timer value and cause the processor to enter the low power state responsive to the determination. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有解码逻辑的核的处理器，用于解码指定要监视的位置的标识的指令和定时器值，以及耦合到解码逻辑的定时器，以执行相对于定时器值。处理器还可以包括耦合到核的功率管理单元，以至少部分地基于定时器值来确定低功率状态的类型，并且使处理器响应于该确定而进入低功率状态。描述和要求保护其他实施例。

22. 发明申请

US20120226926A1 INDEPENDENT POWER CONTROL OF PROCESSING CORES 审中-公开
标题翻译：加工过程中的独立功率控制
公开(公告)号：US20120226926A1
公开(公告)日：2012-09-06
申请号：US13471222
申请日：2012-05-14
申请人： Stephen H. Gunther , Edward A. Burton , Anant Deval , Stephan Jourdan , Robert Greiner , Michael Cornaby
发明人： Stephen H. Gunther , Edward A. Burton , Anant Deval , Stephan Jourdan , Robert Greiner , Michael Cornaby
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/324 , G06F1/3287 , G06F1/3296
摘要： Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.
摘要翻译：两个或多个处理核心的独立功率控制。更具体地，本发明的至少一个实施例涉及将至少一个处理核放置在功率状态而不与一个或多个其它处理核的功率状态协调的技术。

23. 发明申请

US20110154079A1 Instruction For Enabling A Procesor Wait State 有权
标题翻译：启用处理器等待状态的指令
公开(公告)号：US20110154079A1
公开(公告)日：2011-06-23
申请号：US12641534
申请日：2009-12-18
申请人： Martin G. Dixon , Scott D. Rodgers , Taraneh Bahrami , Stephen H. Gunther , Prashant Sethi , Per Hammarlund
发明人： Martin G. Dixon , Scott D. Rodgers , Taraneh Bahrami , Stephen H. Gunther , Prashant Sethi , Per Hammarlund
IPC分类号： G06F1/32 , G06F12/08 , G06F9/30
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3206 , G06F1/3228 , G06F1/3293 , G06F9/30083 , G06F9/3009 , Y02D10/122 , Y02D50/20
摘要： In one embodiment, the present invention includes a processor having a core with decode logic to decode an instruction prescribing an identification of a location to be monitored and a timer value, and a timer coupled to the decode logic to perform a count with respect to the timer value. The processor may further include a power management unit coupled to the core to determine a type of a low power state based at least in part on the timer value and cause the processor to enter the low power state responsive to the determination. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有解码逻辑的核的处理器，用于解码指定要监视的位置的标识的指令和定时器值，以及耦合到解码逻辑的定时器，以执行相对于定时器值。处理器还可以包括耦合到核的功率管理单元，以至少部分地基于定时器值来确定低功率状态的类型，并且使处理器响应于该确定而进入低功率状态。描述和要求保护其他实施例。

24. 发明申请

US20080136397A1 Operating integrated circuit logic blocks at independent voltages with single voltage supply 有权
标题翻译：使用单电源供电的独立电压下工作的集成电路逻辑块
公开(公告)号：US20080136397A1
公开(公告)日：2008-06-12
申请号：US11636425
申请日：2006-12-08
申请人： Stephen H. Gunther , Edward Burton , Anant Deval , Stephan Jourdan , Robert Greiner , Mike Cornaby
发明人： Stephen H. Gunther , Edward Burton , Anant Deval , Stephan Jourdan , Robert Greiner , Mike Cornaby
IPC分类号： G05F5/00
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Methods and apparatus to operate various logic blocks of an integrated circuit (IC) at independent voltages are described. In one embodiment, supply of power to one or more domains in an IC is adjusted based on an indication that power consumption by components of the corresponding domain is to be modified. Other embodiments are also described.
摘要翻译：描述以独立电压操作集成电路（IC）的各种逻辑块的方法和装置。在一个实施例中，基于对相应域的组件的功率消耗进行修改的指示来调整对IC中的一个或多个域的功率供给。还描述了其它实施例。

25. 发明授权

US06981163B2 Method and apparatus for power mode transition in a multi-thread processor 失效
标题翻译：多线程处理器中功率模式转换的方法和装置
公开(公告)号：US06981163B2
公开(公告)日：2005-12-27
申请号：US10887488
申请日：2004-07-07
申请人： Bret L. Toll , Alan B. Kyker , Stephen H. Gunther
发明人： Bret L. Toll , Alan B. Kyker , Stephen H. Gunther
IPC分类号： G06F1/32 , G06F1/26
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/329 , Y02D10/128 , Y02D10/24 , Y02D50/20
摘要： A method and apparatus for power mode transition in a multi-thread processor. A first indication is issued, including a first identifier associated with a first logical processor in a processor, that the first logical processor has entered a power mode. A second indication is issued, including a second identifier associated with a second logical processor in the processor, that the second logical processor has entered the power mode. The indications may be, for example, stop grant acknowledge special bus cycles indicating that the logical processors have entered a stop grant mode. The processor may be transitioned to a sleep mode when both the first and second indications have been issued.
摘要翻译：一种用于多线程处理器中功率模式转换的方法和装置。发布第一指示，包括与处理器中的第一逻辑处理器相关联的第一标识符，第一逻辑处理器已经进入功率模式。发出第二指示，包括与处理器中的第二逻辑处理器相关联的第二标识符，第二逻辑处理器已经进入电源模式。指示可以是例如停止授权确认特殊总线周期，指示逻辑处理器已经进入停止许可模式。当第一和第二指示都已被发出时，处理器可以转换到睡眠模式。

26. 发明授权

US5860106A Method and apparatus for dynamically adjusting power/performance characteristics of a memory subsystem 失效
标题翻译：用于动态调整存储器子系统的功率/性能特性的方法和装置
公开(公告)号：US5860106A
公开(公告)日：1999-01-12
申请号：US502094
申请日：1995-07-13
申请人： Stanley J. Domen , Dileep R. Idate , Stephen H. Gunther , George Thangadurai
发明人： Stanley J. Domen , Dileep R. Idate , Stephen H. Gunther , George Thangadurai
IPC分类号： G06F12/02 , G06F12/08 , G11C11/413 , G06F9/38 , G06F1/32
CPC分类号： G11C11/413 , G06F12/0215 , G06F12/0802 , G06F2212/1028 , Y02B60/1225
摘要： An apparatus and method for dynamically adjusting the power/performance characteristics of a memory subsystem. Since the memory subsystem access requirements are heavily dependent on the application being executed, static methods of enabling or disabling the individual memory system components (as are used in prior art) are less than optimal from a power consumption perspective. By dynamically tracking the behavior of the memory subsystem, the invention predicts the probability that the next event will have certain characteristics, such as whether it will result in a memory cycle that requires the attention of a cache memory, whether that memory cycle will result in a cache memory hit, and whether a DRAM page hit in main memory will occur if the requested data is not in one of the levels of cache memory. Based on these probabilities, the invention dynamically enables or disables components of the subsystem. By intelligently adjusting the state of these components, significant power savings are achieved without degradation in performance.
摘要翻译：一种用于动态调整存储器子系统的功率/性能特性的装置和方法。由于存储器子系统访问要求在很大程度上取决于正在执行的应用程序，所以启用或禁用各个存储器系统组件（如现有技术中所使用的）的静态方法从功耗角度来看不是最佳的。通过动态跟踪存储器子系统的行为，本发明预测下一个事件将具有某些特征的概率，例如它是否会导致需要高速缓冲存储器注意的存储器周期，该存储器周期是否会导致高速缓冲存储器命中，以及如果请求的数据不在高速缓冲存储器的一个级别中，是否将在主存储器中命中DRAM页面。基于这些概率，本发明动态地启用或禁用子系统的组件。通过智能地调整这些组件的状态，可以实现显着的功率节省，而不会降低性能。

27. 发明授权

US09563254B2 System, method and apparatus for energy efficiency and energy conservation by configuring power management parameters during run time 有权
标题翻译：通过在运行时配置电源管理参数，实现节能和节能的系统，方法和装置
公开(公告)号：US09563254B2
公开(公告)日：2017-02-07
申请号：US13335635
申请日：2011-12-22
申请人： Ryan D. Wells , Sanjeev Jahagirdar , Inder Sodhi , Jeremy Shrall , Stephen H. Gunther
发明人： Ryan D. Wells , Sanjeev Jahagirdar , Inder Sodhi , Jeremy Shrall , Stephen H. Gunther
IPC分类号： G06F1/00 , G06F1/32 , G06F1/26
CPC分类号： G06F1/324 , G06F1/26 , G06F1/3206 , Y02D10/126
摘要： According to one embodiment of the invention, an integrated circuit device at least one compute engine and a control unit. Coupled to the compute engine(s), the control unit is adapted to dynamically control an energy-efficient operating setting of at least one power management parameter for the integrated circuit device after execution of Basic Input/Output System (BIOS) has already completed.
摘要翻译：根据本发明的一个实施例，集成电路装置至少包括一个计算引擎和一个控制单元。耦合到计算引擎，控制单元适于在执行基本输入/输出系统（BIOS）已经完成之后动态地控制用于集成电路设备的至少一个功率管理参数的节能操作设置。

28. 发明申请

US20150346804A1 METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING DETECTING AND CONTROLLING CURRENT RAMPS IN PROCESSING CIRCUIT 有权
标题翻译：用于能源效率和能源保护的方法，装置和系统，包括检测和控制处理电路中的电流RAM
公开(公告)号：US20150346804A1
公开(公告)日：2015-12-03
申请号：US14823994
申请日：2015-08-11
申请人： Anupama Suryanarayanan , Matthew C. Merten , Ryan L. Carlson , Stephen H. Gunther
发明人： Anupama Suryanarayanan , Matthew C. Merten , Ryan L. Carlson , Stephen H. Gunther
IPC分类号： G06F1/32
CPC分类号： G06F1/3243 , Y02D10/152
摘要： Some implementations provide techniques and arrangements for adjusting a rate at which operations are performed by a processor based on a comparison of a first indication of power consumed by the processor as a result of performing a first set of operations and a second indication of power consumed by the processor as a result of performing a second set of operations. The rate at which operations are performed by the processor may be adjusted when the comparison indicates that a difference between the first indication of power consumed by the processor and the second indication of power consumed by the processor is greater than a threshold value.
摘要翻译：一些实施方案提供了用于调整由处理器执行操作的速率的技术和布置，其基于由执行第一组操作的结果和由处理器消耗的功率的第二指示来比较由处理器消耗的功率的第一指示作为执行第二组操作的结果的处理器。当比较指示处理器消耗的功率的第一指示与处理器消耗的功率的第二指示之间的差异大于阈值时，可以调整由处理器执行操作的速率。

29. 发明授权

US09052901B2 Method, apparatus, and system for energy efficiency and energy conservation including configurable maximum processor current 有权
标题翻译：能量效率和节能的方法，装置和系统，包括可配置的最大处理器电流
公开(公告)号：US09052901B2
公开(公告)日：2015-06-09
申请号：US13326105
申请日：2011-12-14
申请人： Ketan R. Shah , Eric Distefano , Stephen H. Gunther , Jeremy J. Shrall
发明人： Ketan R. Shah , Eric Distefano , Stephen H. Gunther , Jeremy J. Shrall
IPC分类号： G06F1/32 , G06F9/44 , G06F9/455
CPC分类号： G06F1/3243 , G06F1/3206 , G06F1/324 , G06F9/4401 , G06F9/4411 , G06F9/455 , Y02D10/126 , Y02D10/152 , Y02D50/20
摘要： An apparatus, method and system is described herein for providing multiple maximum current configuration options including corresponding turbo frequencies for a processing device. Available options for a processor are determined by initialization code. And based on platform electrical capabilities, an optimal one of the multiple current configuration options is selected. Moreover, during runtime another current configuration is dynamically selected based on current configuration considerations to provide high flexibility and best possible performance per part and computing platform.
摘要翻译：本文描述了一种用于提供多个最大电流配置选项的装置，方法和系统，包括用于处理设备的对应的turbo频率。处理器的可用选项由初始化代码确定。并且基于平台电气功能，选择多个当前配置选项中的最佳一个。此外，在运行期间，基于当前配置注意事项动态地选择当前配置，以提供每个部件和计算平台的高灵活性和最佳性能。

30. 发明授权

US09037885B2 Independent power control of processing cores 有权
公开(公告)号：US09037885B2
公开(公告)日：2015-05-19
申请号：US12899311
申请日：2010-10-06
申请人： Stephen H. Gunther , Edward A. Burton , Anant Deval , Stephan Jourdan , Robert Greiner , Michael Cornaby
发明人： Stephen H. Gunther , Edward A. Burton , Anant Deval , Stephan Jourdan , Robert Greiner , Michael Cornaby
IPC分类号： G06F1/32 , G06F1/26
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/324 , G06F1/3287 , G06F1/3296
摘要： Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式