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1. 发明授权

US06754828B1 Algorithm for non-volatile memory updates 有权
标题翻译：用于非易失性存储器更新的算法
公开(公告)号：US06754828B1
公开(公告)日：2004-06-22
申请号：US09352715
申请日：1999-07-13
申请人： Suresh Marisetty , Andrew J. Fish , Yan Li , Mani Ayyar , Amy O'Donnell , George Thangadurai , Sham M. Datta
发明人： Suresh Marisetty , Andrew J. Fish , Yan Li , Mani Ayyar , Amy O'Donnell , George Thangadurai , Sham M. Datta
IPC分类号： G06F942
CPC分类号： G06F8/65
摘要： A novel processor architecture and algorithms are provided which improve non-volatile memory updates and increases processor performance in successive generations of processors. A new processor architecture is supported by a software model consisting of two new firmware layers and the legacy 32 bit basic input output system (BIOS) firmware. The new firmware layers consist of a Processor Abstraction Layer (PAL) and a System Abstraction Layer (SAL). The PAL and SAL have procedure calls which allow updates of the firmware components in the non-volatile memory of a system, e.g. non-volatile ROM. The present invention includes invoking a system abstraction layer update procedure to implement a new input binary into the non-volatile memory. An algorithm for the non-volatile memory includes selecting a lead processor to perform an update and using the system abstraction layer update procedure. The system abstraction layer update procedure is used to call an appropriate authentication routine. The system abstraction layer update procedure is used to call a specific non-volatile memory implementation routine.
摘要翻译：提供了一种新颖的处理器架构和算法，其改进了非易失性存储器更新并且在连续几代处理器中提高了处理器性能。由两个新固件层和传统32位基本输入输出系统（BIOS）固件组成的软件模型支持新的处理器架构。新的固件层由处理器抽象层（PAL）和系统抽象层（SAL）组成。 PAL和SAL具有允许更新系统的非易失性存储器中的固件组件的过程调用，例如，非易失性ROM。本发明包括调用系统抽象层更新过程以将新的输入二进制文件实现到非易失性存储器中。用于非易失性存储器的算法包括选择引导处理器来执行更新并使用系统抽象层更新过程。系统抽象层更新过程用于调用适当的认证例程。系统抽象层更新过程用于调用特定的非易失性存储器实现例程。

2. 发明授权

US06587947B1 System and method for verification of off-chip processor code 有权
标题翻译：用于片外处理器代码验证的系统和方法
公开(公告)号：US06587947B1
公开(公告)日：2003-07-01
申请号：US09283062
申请日：1999-04-01
申请人： Amy O'Donnell , George Thangadurai , Anand Rajan
发明人： Amy O'Donnell , George Thangadurai , Anand Rajan
IPC分类号： G06F1130
CPC分类号： G06F21/57 , G06F21/64
摘要： An electronic system and corresponding method for verifying the integrity of code that is stored off-chip. The electronic system comprises a memory element to store Processor Abstraction Layer (PAL) code and a processor coupled to the memory element. The processor verifies the integrity of the PAL code prior to execution of the PAL code.
摘要翻译：一种用于验证芯片外存储的代码完整性的电子系统和相应的方法。电子系统包括存储处理器抽象层（PAL）代码的存储器元件和耦合到存储元件的处理器。处理器在执行PAL代码之前验证PAL码的完整性。

3. 发明授权

US6112274A Method and apparatus for processing more than one interrupts without reinitializing the interrupt handler program 失效
标题翻译：用于处理多个中断而不重新初始化中断处理程序的方法和装置
公开(公告)号：US6112274A
公开(公告)日：2000-08-29
申请号：US98993
申请日：1998-06-17
申请人： Richard Goe , Vijay Goru , George Thangadurai
发明人： Richard Goe , Vijay Goru , George Thangadurai
IPC分类号： G06F13/26 , G06F13/24
CPC分类号： G06F13/26
摘要： A system and method is provided for processing interrupt requests. The method is accomplished by detecting when an interrupt request is being stored in a storage location, examining the storage location storing the interrupt request, prioritizing the interrupt request when more than one interrupt request is stored in the storage location to determine an interrupt request processing order, clearing the interrupt request in the storage location that is to be processed, and processing the interrupt request. The system comprises a first storage location for storing an interrupt request, a second storage location for storing an interrupt handler program with encoded statements for examining the first storage location, prioritizing the interrupt request that is to be processed if more than one interrupt request is stored in said first storage location, clearing the interrupt request that is to be processed, and processing the interrupt request. The system further comprises a processor for executing the interrupt handler program.
摘要翻译：提供了一种用于处理中断请求的系统和方法。该方法通过检测中断请求是否被存储在存储位置中，检查存储中断请求的存储位置，当多于一个中断请求被存储在存储位置中时优先处理中断请求，以确定中断请求处理顺序，清除要处理的存储位置中的中断请求，并处理中断请求。该系统包括用于存储中断请求的第一存储位置，用于存储具有用于检查第一存储位置的编码语句的中断处理程序的第二存储位置，如果存储多于一个中断请求，则优先处理要处理的中断请求在所述第一存储位置，清除要处理的中断请求，并处理中断请求。该系统还包括用于执行中断处理程序的处理器。

4. 发明授权

US06675324B2 Rendezvous of processors with OS coordination 有权
标题翻译：处理器集合与操作系统协调
公开(公告)号：US06675324B2
公开(公告)日：2004-01-06
申请号：US09405972
申请日：1999-09-27
申请人： Suresh Marisetty , George Thangadurai , Mani Ayyar
发明人： Suresh Marisetty , George Thangadurai , Mani Ayyar
IPC分类号： G06F1100
CPC分类号： G06F11/2242
摘要： A system comprises a non volatile memory and a plurality of processors. The non volatile memory stores an error handling routine. Each processor of the plurality of processors accesses the error handling routine on detecting an error and, on certain errors, signals the remaining processors to enter a rendezvous state. In the rendezvous state, a single processor takes over and performs error handling.
摘要翻译：一种系统包括非易失性存储器和多个处理器。非易失性存储器存储错误处理例程。多个处理器的每个处理器在检测到错误时访问错误处理例程，并且在某些错误时，信号剩余的处理器进入会合状态。在会合状态下，单个处理器接管并执行错误处理。

5. 发明授权

US06571335B1 System and method for authentication of off-chip processor firmware code 有权
标题翻译：片外处理器固件代码认证的系统和方法
公开(公告)号：US06571335B1
公开(公告)日：2003-05-27
申请号：US09282948
申请日：1999-04-01
申请人： Amy O'Donnell , George Thangadurai , Anand Rajan
发明人： Amy O'Donnell , George Thangadurai , Anand Rajan
IPC分类号： G06F1130
CPC分类号： G06F21/57 , G06F21/64
摘要： An electronic system and corresponding method for authenticating firmware stored in a memory element external to a processor. In one embodiment, an electronic system comprises a processor and a memory element. The memory element is used to contain firmware and a digital signature of the firmware signed by a signatory. Coupled to the memory element, the processor authenticates the firmware during a predetermined condition, which occurs prior to execution of the firmware, through use of a pre-stored public key of the signatory and a pre-stored digital signature function.
摘要翻译：一种用于认证存储在处理器外部的存储器元件中的固件的电子系统和相应方法。在一个实施例中，电子系统包括处理器和存储元件。存储器元件用于包含由签名人签名的固件和固件的数字签名。耦合到存储器元件的处理器通过使用预先存储的签名者的公开密钥和预先存储的数字签名功能，在执行固件之前发生的预定条件下对固件进行认证。

6. 发明授权

US07171547B1 Method and apparatus to save processor architectural state for later process resumption 有权
标题翻译：节省处理器架构状态以便稍后恢复的方法和设备
公开(公告)号：US07171547B1
公开(公告)日：2007-01-30
申请号：US09473448
申请日：1999-12-28
申请人： George Thangadurai , Erik T. Lode
发明人： George Thangadurai , Erik T. Lode
IPC分类号： G06F9/40
CPC分类号： G06F9/4484
摘要： A method and an apparatus for restoring logic states using programming code are disclosed. In one embodiment, the process of a data processing system identifies a first logic value stored in a first register and branches to a first location within the programming code based upon the first logic value. The execution of the programming code occurs in a processor firmware layer. The first register can be used as a scratch register for the subsequent instruction.
摘要翻译：公开了一种使用编程代码恢复逻辑状态的方法和装置。在一个实施例中，数据处理系统的处理识别存储在第一寄存器中的第一逻辑值，并且基于第一逻辑值分支到编程代码内的第一位置。编程代码的执行发生在处理器固件层中。第一个寄存器可以用作后续指令的临时寄存器。

7. 发明授权

US07502959B2 Error correction apparatus, systems, and methods 有权
标题翻译：纠错装置，系统和方法
公开(公告)号：US07502959B2
公开(公告)日：2009-03-10
申请号：US10628726
申请日：2003-07-28
申请人： Suresh Marisetty , George Thangadurai , Mani Ayyar
发明人： Suresh Marisetty , George Thangadurai , Mani Ayyar
IPC分类号： G06F11/00
CPC分类号： G06F11/2242
摘要： A system comprises a non volatile memory and a plurality of processors. The non volatile memory stores an error handling routine. Each processor of the plurality of processors accesses the error handling routine on detecting an error and, on certain errors, signals the remaining processors to enter a rendezvous state. In the rendezvous state, a single processor takes over and performs error handling.
摘要翻译：一种系统包括非易失性存储器和多个处理器。非易失性存储器存储错误处理例程。多个处理器的每个处理器在检测到错误时访问错误处理例程，并且在某些错误时，信号剩余的处理器进入会合状态。在会合状态下，单个处理器接管并执行错误处理。

8. 发明授权

US06748526B1 CPU stepping and processor firmware matching mechanism 有权
标题翻译： CPU步进和处理器固件匹配机制
公开(公告)号：US06748526B1
公开(公告)日：2004-06-08
申请号：US09474347
申请日：1999-12-29
申请人： George Thangadurai
发明人： George Thangadurai
IPC分类号： G06F15177
CPC分类号： G06F8/65 , G06F8/654
摘要： A method and an apparatus for validating a processor firmware (“PF”) are disclosed. In one embodiment, at least one version of Processor Firmware (“PF”) is identified. After identification, the PF is compared with a version of PF that is required by a processor, to determine whether the PF is compatible with the processor. If the version of PF is incompatible with the version of PF required by the processor, the current execution is suspended and a new version of PF is obtained. When the new version of PF is received, the system is initialized.
摘要翻译：公开了一种用于验证处理器固件（“PF”）的方法和装置。在一个实施例中，识别至少一个版本的处理器固件（“PF”）。识别后，将PF与处理器要求的PF版本进行比较，以确定PF是否与处理器兼容。如果PF版本与处理器所需的PF版本不兼容，则暂停执行当前执行，并获得新版本的PF。当接收到新版本的PF时，系统被初始化。

9. 发明授权

US5860106A Method and apparatus for dynamically adjusting power/performance characteristics of a memory subsystem 失效
标题翻译：用于动态调整存储器子系统的功率/性能特性的方法和装置
公开(公告)号：US5860106A
公开(公告)日：1999-01-12
申请号：US502094
申请日：1995-07-13
申请人： Stanley J. Domen , Dileep R. Idate , Stephen H. Gunther , George Thangadurai
发明人： Stanley J. Domen , Dileep R. Idate , Stephen H. Gunther , George Thangadurai
IPC分类号： G06F12/02 , G06F12/08 , G11C11/413 , G06F9/38 , G06F1/32
CPC分类号： G11C11/413 , G06F12/0215 , G06F12/0802 , G06F2212/1028 , Y02B60/1225
摘要： An apparatus and method for dynamically adjusting the power/performance characteristics of a memory subsystem. Since the memory subsystem access requirements are heavily dependent on the application being executed, static methods of enabling or disabling the individual memory system components (as are used in prior art) are less than optimal from a power consumption perspective. By dynamically tracking the behavior of the memory subsystem, the invention predicts the probability that the next event will have certain characteristics, such as whether it will result in a memory cycle that requires the attention of a cache memory, whether that memory cycle will result in a cache memory hit, and whether a DRAM page hit in main memory will occur if the requested data is not in one of the levels of cache memory. Based on these probabilities, the invention dynamically enables or disables components of the subsystem. By intelligently adjusting the state of these components, significant power savings are achieved without degradation in performance.
摘要翻译：一种用于动态调整存储器子系统的功率/性能特性的装置和方法。由于存储器子系统访问要求在很大程度上取决于正在执行的应用程序，所以启用或禁用各个存储器系统组件（如现有技术中所使用的）的静态方法从功耗角度来看不是最佳的。通过动态跟踪存储器子系统的行为，本发明预测下一个事件将具有某些特征的概率，例如它是否会导致需要高速缓冲存储器注意的存储器周期，该存储器周期是否会导致高速缓冲存储器命中，以及如果请求的数据不在高速缓冲存储器的一个级别中，是否将在主存储器中命中DRAM页面。基于这些概率，本发明动态地启用或禁用子系统的组件。通过智能地调整这些组件的状态，可以实现显着的功率节省，而不会降低性能。

10. 发明授权

US5745770A Method and apparatus for servicing simultaneous I/O trap and debug traps in a microprocessor 失效
标题翻译：用于维护微处理器中同步I / O陷阱和调试陷阱的方法和装置
公开(公告)号：US5745770A
公开(公告)日：1998-04-28
申请号：US595187
申请日：1996-02-01
申请人： George Thangadurai , Chih-Hung Chung
发明人： George Thangadurai , Chih-Hung Chung
IPC分类号： G06F9/48 , G06F11/36 , G06F9/46
CPC分类号： G06F9/4812 , G06F11/3648 , Y02B60/144
摘要： A microprocessor includes the capability to service at least one debug exception and an I/O trap generated during execution of a single instruction. After executing each instruction, the microprocessor determines whether a debug exception and an I/O trap occurred. If at least one debug exception and an I/O trap exist, then the microprocessor determines an active status for the debug exception. The microprocessor stores the contents of internal registers, constituting a state of the microprocessor, to memory, and latches a breakpoint status for the debug exception in a public debug status register. The breakpoint status is preserved by copying the breakpoint status to a private debug status register. The microprocessor services the I/O trap by executing a SMM handler, an upon returning from the SMM handler, the state of the microprocessor is restored. If the I/O trap serviced requires instruction restart, then the state of the microprocessor is adjusted to re-execute the instruction. The microprocessor copies the breakpoint status, stored in the private debug status register, to the public debug status register when the I/O trap does not require instruction restart. The debug exception is subsequently serviced by executing an INT1 handler.
摘要翻译：微处理器包括服务于在单个指令执行期间产生的至少一个调试异常和I / O陷阱的能力。执行每条指令后，微处理器确定是否发生调试异常和I / O陷阱。如果存在至少一个调试异常和I / O陷阱，则微处理器确定调试异常的活动状态。微处理器将构成微处理器状态的内部寄存器的内容存储到存储器中，并在公共调试状态寄存器中锁存调试异常的断点状态。通过将断点状态复制到专用调试状态寄存器来保留断点状态。微处理器通过执行SMM处理程序来服务I / O陷阱，当从SMM处理程序返回时，微处理器的状态被恢复。如果I / O陷阱需要指令重新启动，则调整微处理器的状态以重新执行指令。当I / O陷阱不需要重新启动指令时，微处理器将存储在专用调试状态寄存器中的断点状态复制到公共调试状态寄存器。调试异常随后通过执行INT1处理程序进行服务。

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