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21. 发明申请

US20130046955A1 Local Computation Logic Embedded in a Register File to Accelerate Programs 审中-公开
标题翻译：嵌入在寄存器文件中的本地计算逻辑来加速程序
公开(公告)号：US20130046955A1
公开(公告)日：2013-02-21
申请号：US13211701
申请日：2011-08-17
申请人： Pradip Bose , Alper Buyuktosunoglu , Jeffrey Haskell Derby , Michele Martino Franceschini , Robert Kevin Montoye , Augusto J. Vega
发明人： Pradip Bose , Alper Buyuktosunoglu , Jeffrey Haskell Derby , Michele Martino Franceschini , Robert Kevin Montoye , Augusto J. Vega
IPC分类号： G06F15/76
摘要： A system and methods for improving performance of an central processing unit. The central processing unit system includes: a pipeline configured to receive an instruction; and a register file partitioned into a one or more subarrays where (i) the register file includes one or more computation elements and (ii) the one or more computation elements are directly connected to one or more subarrays.
摘要翻译：一种用于提高中央处理单元性能的系统和方法。中央处理单元系统包括：配置成接收指令的流水线; 以及分配到一个或多个子阵列中的寄存器文件，其中（i）寄存器文件包括一个或多个计算元件，并且（ii）一个或多个计算元件直接连接到一个或多个子阵列。

22. 发明申请

US20120245897A1 Virtualized Abstraction with Built-in Data Alignment and Simultaneous Event Monitoring in Performance Counter Based Application Characterization and Tuning 有权
标题翻译：基于性能计数器的应用程序表征和调优的内置数据对齐和同步事件监控的虚拟化抽象
公开(公告)号：US20120245897A1
公开(公告)日：2012-09-27
申请号：US13052616
申请日：2011-03-21
申请人： Pradip Bose , Alper Buyuktosunoglu , Canturk Isci , Jeff Kephart , Xiaoqiao Meng , Ruhi Sarikaya
发明人： Pradip Bose , Alper Buyuktosunoglu , Canturk Isci , Jeff Kephart , Xiaoqiao Meng , Ruhi Sarikaya
IPC分类号： G06F11/30 , G06F15/00
CPC分类号： G06F11/3089 , G06F11/3024 , G06F11/3466 , G06F2201/815 , G06F2201/86 , G06F2201/88
摘要： Techniques for monitoring a set of one or more event counters of application execution are provided. The techniques include constructing a virtual performance monitoring counter (VPMC) layer as a unified abstraction of a physical performance monitoring counter (PMC) architecture, and incorporating one or more programming interfaces (PIs) in connection with the virtual performance monitoring counter, wherein the one or more programming interfaces facilitate simultaneous access and data monitoring across a set of one or more event counters.
摘要翻译：提供了用于监视应用执行的一个或多个事件计数器的集合的技术。这些技术包括构建虚拟性能监视计数器（VPMC）层作为物理性能监视计数器（PMC）体系结构的统一抽象，并且结合一个或多个与虚拟性能监视计数器结合的编程接口（PI），其中一个或更多的编程接口便于跨一组或多个事件计数器的同时访问和数据监视。

23. 发明授权

US08219834B2 Predictive power gating with optional guard mechanism 有权
标题翻译：具有可选保护机构的预测电源门控
公开(公告)号：US08219834B2
公开(公告)日：2012-07-10
申请号：US12539978
申请日：2009-08-12
申请人： Jayanta Basak , Pradip Bose , Alper Buyuktosunoglu , Anita Lungu
发明人： Jayanta Basak , Pradip Bose , Alper Buyuktosunoglu , Anita Lungu
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32
CPC分类号： G06F1/3203
摘要： A mechanism is provided for predictively power gating a set of units within the data processing system. A second-level power gating controller monitors a set of events for each unit in a set of units within the data processing system. The second-level power gating controller identifies idle sequences of a predetermined set of cycles within the events from each unit where the unit is idle. The second-level power gating controller determines preceding sequences of a predetermined length that precede the idle sequences. The second-level power gating controller determines an accuracy of the preceding sequences. Responsive to the accuracy being above a threshold, the second-level power gating controller sends a permit command to a first-level power gating mechanism associated with the unit to permit power gating of the unit.
摘要翻译：提供了用于在数据处理系统内预测性地选通一组单元的机构。二级电源门控控制器监视数据处理系统内的一组单元中的每个单元的一组事件。第二级电力门控控制器从单元空闲的每个单元的事件内识别预定的一组周期的空闲序列。第二级电源门控控制器确定在空闲序列之前的预定长度的先前序列。二级电源门控控制器确定前面的序列的精度。响应于精度高于阈值，二级电源门控控制器向与该单元相关联的一级电源门控机构发送许可命令，以允许该单元的电源门控。

24. 发明授权

US07487012B2 Methods for thermal management of three-dimensional integrated circuits 失效
标题翻译：三维集成电路热管理方法
公开(公告)号：US07487012B2
公开(公告)日：2009-02-03
申请号：US11747279
申请日：2007-05-11
申请人： Pradip Bose , Alper Buyuktosunoglu , Eren Kursun
发明人： Pradip Bose , Alper Buyuktosunoglu , Eren Kursun
IPC分类号： G05D23/00
CPC分类号： G05D23/1932
摘要： A method of dynamic thermal management in a multi-dimensional integrated circuit or device is provided. The method includes monitoring on-chip temperatures, power dissipation, and performance of device layers. The method includes comparing on-chip temperatures to thermal thresholds, on-chip power dissipation to power thresholds and on-chip performance to performance thresholds. Also, the method includes analyzing interactions between temperatures, power, and performance of different device layers within the multi-dimensional integrated circuits. The method includes activating layer-specific thermal and power management within performance constraints on one or more device layers through actuators in the corresponding device layers, depending on the severity of heating.
摘要翻译：提供了一种多维集成电路或器件中的动态热管理方法。该方法包括监测片上温度，功耗和器件层的性能。该方法包括将片上温度与热阈值进行比较，将片上功耗降至功率阈值，并将片上性能与性能阈值进行比较。此外，该方法包括分析多维集成电路内不同器件层的温度，功率和性能之间的相互作用。该方法包括根据加热的严重程度，通过相应设备层中的致动器在一个或多个设备层上的性能约束内激活层特定的热和功率管理。

25. 发明授权

US07447923B2 Systems and methods for mutually exclusive activation of microprocessor resources to control maximum power 失效
标题翻译：用于互相激活微处理器资源以控制最大功率的系统和方法
公开(公告)号：US07447923B2
公开(公告)日：2008-11-04
申请号：US11207333
申请日：2005-08-19
申请人： Pradip Bose , Alper Buyuktosunoglu , Zhigang Hu , Hans Mikael Jacobson , Vijayalakshmi Srinivasan , Victor Zyuban
发明人： Pradip Bose , Alper Buyuktosunoglu , Zhigang Hu , Hans Mikael Jacobson , Vijayalakshmi Srinivasan , Victor Zyuban
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/3287 , G06F1/329 , G06F9/30145 , G06F9/382 , G06F9/3836 , G06F9/3842 , G06F9/3867 , Y02D10/171 , Y02D10/24
摘要： A device for controlling power parameters in a microprocessor includes a resource activation control unit for controlling the maximum power of the microprocessor and two or more resources. The resource activation control unit controls the activation of the resources such that the consumed and dissipated power of the microprocessor does not exceed a power bound which is configurable to a predetermined value below the maximum power.
摘要翻译：用于控制微处理器中的功率参数的装置包括用于控制微处理器的最大功率和两个或更多个资源的资源激活控制单元。资源激活控制单元控制资源的激活，使得微处理器的消耗和耗散功率不超过可配置为低于最大功率的预定值的功率限制。

26. 发明授权

US07392366B2 Adaptive fetch gating in multithreaded processors, fetch control and method of controlling fetches 有权
标题翻译：多线程处理器中的自适应提取门控，提取控制和控制提取的方法
公开(公告)号：US07392366B2
公开(公告)日：2008-06-24
申请号：US11228781
申请日：2005-09-16
申请人： Pradip Bose , Alper Buyuktosunoglu , Richard J. Eickemeyer , Lee E. Eisen , Philip G. Emma , John B. Griswell , Zhigang Hu , Hung Q. Le , Douglas R. Logan , Balaram Sinharoy
发明人： Pradip Bose , Alper Buyuktosunoglu , Richard J. Eickemeyer , Lee E. Eisen , Philip G. Emma , John B. Griswell , Zhigang Hu , Hung Q. Le , Douglas R. Logan , Balaram Sinharoy
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/3867
摘要： A multithreaded processor, fetch control for a multithreaded processor and a method of fetching in the multithreaded processor. Processor event and use (EU) signs are monitored for downstream pipeline conditions indicating pipeline execution thread states. Instruction cache fetches are skipped for any thread that is incapable of receiving fetched cache contents, e.g., because the thread is full or stalled. Also, consecutive fetches may be selected for the same thread, e.g., on a branch mis-predict. Thus, the processor avoids wasting power on unnecessary or place keeper fetches.
摘要翻译：多线程处理器，用于多线程处理器的获取控制以及在多线程处理器中获取的方法。监视处理器事件和使用（EU）符号，用于指示管道执行线程状态的下游管道条件。对于不能接收获取的高速缓存内容的任何线程，例如由于线程已满或停顿，跳过指令高速缓存提取。此外，可以针对相同的线程选择连续的提取，例如在分支误预测中。因此，处理器避免浪费电力不必要的或放置保持器提取。

27. 发明申请

US20070043960A1 Systems and methods for mutually exclusive activation of microprocessor resources to control maximum power 失效
标题翻译：用于互相激活微处理器资源以控制最大功率的系统和方法
公开(公告)号：US20070043960A1
公开(公告)日：2007-02-22
申请号：US11207333
申请日：2005-08-19
申请人： Pradip Bose , Alper Buyuktosunoglu , Zhigang Hu , Hans Jacobson , Vijayalakshmi Srinivasan , Victor Zyuban
发明人： Pradip Bose , Alper Buyuktosunoglu , Zhigang Hu , Hans Jacobson , Vijayalakshmi Srinivasan , Victor Zyuban
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3287 , G06F1/329 , G06F9/30145 , G06F9/382 , G06F9/3836 , G06F9/3842 , G06F9/3867 , Y02D10/171 , Y02D10/24
摘要： A device for controlling power parameters in a microprocessor includes a resource activation control unit for controlling the maximum power of the microprocessor and two or more resources. The resource activation control unit controls the activation of the resources such that the consumed and dissipated power of the microprocessor does not exceed a power bound which is configurable to a predetermined value below the maximum power.
摘要翻译：用于控制微处理器中的功率参数的装置包括用于控制微处理器的最大功率和两个或更多个资源的资源激活控制单元。资源激活控制单元控制资源的激活，使得微处理器的消耗和耗散功率不超过可配置为低于最大功率的预定值的功率限制。

28. 发明授权

US10534608B2 Local computation logic embedded in a register file to accelerate programs 有权
公开(公告)号：US10534608B2
公开(公告)日：2020-01-14
申请号：US13211701
申请日：2011-08-17
申请人： Pradip Bose , Alper Buyuktosunoglu , Jeffrey Haskell Derby , Michele Martino Franceschini , Robert Kevin Montoye , Augusto J. Vega
发明人： Pradip Bose , Alper Buyuktosunoglu , Jeffrey Haskell Derby , Michele Martino Franceschini , Robert Kevin Montoye , Augusto J. Vega
IPC分类号： G06F15/78 , G06F15/16 , G06F9/30 , G06F9/38
摘要： A central processing unit system includes: a pipeline configured to receive an instruction; and a register file partitioned into one or more subarrays where (i) the register file includes one or more computation elements and (ii) the one or more computation elements are directly connected to one or more subarrays.

29. 发明授权

US08914764B2 Adaptive workload based optimizations coupled with a heterogeneous current-aware baseline design to mitigate current delivery limitations in integrated circuits 有权
标题翻译：基于自适应工作负载的优化与异构电流感知基线设计相结合，以减轻集成电路中的当前传输限制
公开(公告)号：US08914764B2
公开(公告)日：2014-12-16
申请号：US13526252
申请日：2012-06-18
申请人： Pradip Bose , Alper Buyuktosunoglu , John A. Darringer , Moinuddin K. Qureshi , Jeonghee Shin
发明人： Pradip Bose , Alper Buyuktosunoglu , John A. Darringer , Moinuddin K. Qureshi , Jeonghee Shin
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5072 , G06F17/5036
摘要： A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.
摘要翻译：与“前置硅”设计方法和“后硅”当前优化编程方法相结合的动态系统，以改进和优化当前传输到芯片的传输，这受到连接的物理特性的限制（例如，受控崩溃芯片连接或 C4s）。该机制包括测量或估计芯片内特定粒度的功耗，使用一种方法将功率信息转换为C4当前信息，并在适用的情况下触发限流机制（包括基于令牌的限制），以限制每个C4超过预先的当前传输 - 建立的限制或期限。设计辅助工具用于根据当前的交付要求在整个芯片上分配C4。该系统与设计和编程方法相结合，改进并优化电流传递可扩展到多层3D芯片堆叠中的层间连接。

30. 发明授权

US08458501B2 Measuring data switching activity in a microprocessor 失效
标题翻译：测量微处理器中的数据交换活动
公开(公告)号：US08458501B2
公开(公告)日：2013-06-04
申请号：US12844372
申请日：2010-07-27
申请人： Pradip Bose , Alper Buyuktosunoglu , Christopher J. Gonzalez , Moinuddin K. Qureshi , Victor Zyuban
发明人： Pradip Bose , Alper Buyuktosunoglu , Christopher J. Gonzalez , Moinuddin K. Qureshi , Victor Zyuban
IPC分类号： G06F1/32 , G06F3/00
CPC分类号： G06F1/3206 , G06F1/324 , G06F1/3296 , Y02D10/126
摘要： A mechanism is provided for approximating data switching activity in a data processing system. A data switching activity identification mechanism in the data processing system receives an identification of a set of data storage devices and a set of bits in the set of data storage devices in the data processing system to be monitored for the data switching activity. The data switching activity identification mechanism sums a count of the identified bits that have changed state for the data storage device along with other counts of the identified bits that have changed state for other data storage devices in the set of data storage devices to form an approximation of data switching activity. A power manager in the data processing system then adjusts a set of operational parameters associated with the data processing system using the approximation of data switching activity.
摘要翻译：提供了一种用于近似数据处理系统中的数据交换活动的机制。数据处理系统中的数据交换活动识别机制在数据处理系统中接收数据存储设备的集合的标识和数据存储设备中的一组位，以对数据交换活动进行监控。数据交换活动识别机制对数据存储装置的已改变状态的已识别比特的计数与数据存储装置中的其他数据存储装置的已改变状态的识别比特的其他计数相加以形成近似值的数据交换活动。数据处理系统中的电源管理器然后使用数据交换活动的近似来调整与数据处理系统相关联的一组操作参数。

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