专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US06556481B1 3-step write operation nonvolatile semiconductor one-transistor, nor-type flash EEPROM memory cell 有权
标题翻译： 3步写操作非易失性半导体单晶体管，非型闪存EEPROM存储单元
公开(公告)号：US06556481B1
公开(公告)日：2003-04-29
申请号：US09852247
申请日：2001-05-09
申请人： Fu-Chang Hsu , Hsing-Ya Tsao , Peter W. Lee , Mervyn Wong
发明人： Fu-Chang Hsu , Hsing-Ya Tsao , Peter W. Lee , Mervyn Wong
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C2216/28
摘要： In the present invention a three step write of a nonvolatile single transistor cell is disclosed. The three steps comprise erasing, reverse programming and programming which can be applied to a plurality of cell types to produce a symmetrical design and allowing shrinkage of the cell beyond that which is possible with other cells designed to use a two step write procedure. The methodology can be applied to either N-channel or P-channel devices and can be used on various type memory cells such as “ETOX”, “NOR” type, “AND” type, and “OR” type. Erasing and programming steps increase the Vt of the cell transistor, whereas reverse programming decreases the Vt of the cell transistor. Over-erase problems are eliminated using the three step write procedure.
摘要翻译：在本发明中，公开了一种非易失性单晶体管单元的三步写入。三个步骤包括擦除，反向编程和编程，其可以应用于多个单元类型以产生对称设计，并且允许单元的收缩超过设计为使用两步写入过程的其他单元可能的缩小。该方法可应用于N沟道或P沟道器件，可用于各种类型的存储单元，例如“ETOX”，“NOR”型，“AND”型和“OR”型。擦除和编程步骤增加了单元晶体管的Vt，而反向编程减小了单元晶体管的Vt。使用三步写入过程可以消除过度擦除问题。

22. 发明授权

US06181607B2 Reversed split-gate cell array 有权
标题翻译：反向分裂栅极单元阵列
公开(公告)号：US06181607B2
公开(公告)日：2001-01-30
申请号：US09351740
申请日：1999-07-12
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao
IPC分类号： G11C1604
CPC分类号： G11C16/0425
摘要： In the present invention an array for a reverse split gate device is described for creating a flash memory that avoids both programming and erase disturb conditions. The device is designed so that the stacked gate is associated with the source and the enhancement gate is associated with the drain. This is the reverse of a conventional spit gate design and allows the drain to buffer the stacked gate from bit lines of a flash memory array. The source line now key to both program and erase operations is laid out in rows where two adjacent rows of cells share the same source line. The source line can be segmented to prevent the entire length of the pair of rows from being erased. The cell is programmed by flowing current backwards in the channel and injecting electrons into the floating gate from an impact ionization that occurs near the source. Erasure is accomplished by Fowler-Nordheim tunneling from the floating gate to the source caused by a potential between the source and the enhancement gate.
摘要翻译：在本发明中，描述了一种用于产生一个避免编程和擦除干扰条件的闪速存储器的用于反向分离栅极器件的阵列。设备被设计成使得堆叠的栅极与源相关联，并且增强栅极与漏极相关联。这与传统的喷口设计相反，并允许漏极从闪存阵列的位线缓冲堆叠的栅极。现在，编程和擦除操作的关键是将两行的单元格共享相同的源行。可以对源极线进行分段，以防止该对行的整个长度被擦除。通过在通道中向后流动电流并将电子从在源附近发生的冲击电离注入到浮动栅极中来编程单元。通过Fowler-Nordheim从源极和增强门之间的电位引起的浮动栅极到源极的擦除来完成擦除。

23. 发明授权

US5920503A Flash memory with novel bitline decoder and sourceline latch 失效
标题翻译：具有新型位线解码器和源极线锁存器的闪存
公开(公告)号：US5920503A
公开(公告)日：1999-07-06
申请号：US850489
申请日：1997-05-02
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao
IPC分类号： G11C11/56 , G11C16/08 , G11C16/14 , G11C16/16 , G11C16/34 , G11C16/00
CPC分类号： G11C16/3427 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/08 , G11C16/14 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/3418 , G11C16/3431 , G11C2211/5642 , G11C2216/20 , G11C8/00
摘要： A flash memory with a novel bitline and sourceline decoder includes a first bank of flash transistors forming a plurality of rows and a plurality of columns, and having wordlines, bitlines and a first sourceline. A second bank of flash transistors forms a plurality of rows and a plurality of columns, and has wordlines, bitlines and a second sourceline. A wordline decoder is coupled to the wordlines and configured to receive a wordline address signal and to decode the wordline address signal to select a wordline. A bitline and sourceline decoder is coupled to the bitlines and sourcelines and configured to receive a bitline address signal and to decode the bitline address signal to select predetermined bitlines and sourcelines. The bitline and sourceline decoder includes a latch coupled to the bitlines, the first sourceline and the second sourceline and configured to latch selected bitlines and sourcelines to selectively provide erase voltages on the selected bitlines and sourcelines. As a result of the novel memory architecture, a flexible number of bytes can be selected for erasure. The selected number of bytes can range from one byte to 64K bytes or more. Advantages of the invention include reduced erase/write cycle time and an improved expected lifetime of the flash memory due to reduced stress on the flash transistors within the flash memory.
摘要翻译：具有新颖位线和源线解码器的闪速存储器包括形成多行和多列的第一闪存晶体组，并具有字线，位线和第一源极线。闪存晶体管的第二组形成多个行和多个列，并且具有字线，位线和第二源极线。字线解码器耦合到字线并且被配置为接收字线地址信号并解码字线地址信号以选择字线。位线和源线解码器耦合到位线和源极线，并被配置为接收位线地址信号并解码位线地址信号以选择预定的位线和源线。位线和源线解码器包括耦合到位线的锁存器，第一源极线路和第二源极线路，并且被配置为锁存所选择的位线和源极线以选择性地在所选择的位线和源极线上提供擦除电压。作为新颖的存储器架构的结果，可以选择灵活的字节数来进行擦除。所选字节数可以从一个字节到64K字节或更多。由于闪速存储器内的闪存晶体管上的应力减小，本发明的优点包括减少的擦除/写入周期时间和闪存的预期寿命的改善。

24. 发明授权

US5917757A Flash memory with high speed erasing structure using thin oxide semiconductor devices 失效
标题翻译：使用薄氧化物半导体器件的高速擦除结构的闪存
公开(公告)号：US5917757A
公开(公告)日：1999-06-29
申请号：US882558
申请日：1997-06-25
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao
IPC分类号： G05F3/20 , G11C5/14 , G11C8/10 , G11C11/56 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/30 , G11C16/34 , H01L27/115 , H02M3/07 , H03K3/0231 , G11C7/00
CPC分类号： G11C16/3427 , G05F3/20 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/30 , G11C16/3404 , G11C16/3409 , G11C16/3418 , G11C16/3431 , G11C16/3445 , G11C5/145 , G11C8/10 , H01L27/115 , H02M3/073 , H03K3/0231 , G11C2211/5621 , G11C2211/5642 , G11C2211/5645 , G11C2216/18 , G11C8/00 , G11C8/14
摘要： A flash memory with a high speed erasing structure includes a bank of flash transistors having a plurality of wordlines, a plurality of bitlines and a sourceline. A wordline decoder is coupled to the wordlines and configured to selectively apply voltages to the wordlines to perform procedures on the flash transistors, where the procedures include a read procedure, an erase procedure and a program procedure. During the erase procedure, the wordline decoder is configured to apply a first increasingly negative voltage in a first voltage range to at least one selected wordline until a first threshold voltage is met, then to apply a second increasingly negative voltage in a second voltage range to the selected wordline and to simultaneously apply a third negative voltage in a third voltage range to at least one deselected wordline. Another embodiment of the invention increases the selected sourceline voltage to achieve a high voltage differential between the gate and source of flash transistors selected to be erased. Advantages of the invention include a fast erasing procedure due to the increased voltage differential applied between the gate and source of flash transistors selected to be erased. Moreover, since the deselected wordlines are also ramped to a negative voltage, stress is reduced on the deselected wordline drivers, thereby increasing the longevity of the flash memory.
摘要翻译：具有高速擦除结构的闪速存储器包括具有多个字线的组闪存晶体管，多个位线和源极线。字线解码器耦合到字线并且被配置为选择性地向字线施加电压以对闪存晶体管执行过程，其中过程包括读取过程，擦除过程和程序过程。在擦除过程期间，字线解码器被配置为将第一电压范围中的第一越来越大的负电压施加到至少一个选定字线，直到满足第一阈值电压，然后在第二电压范围内施加第二越来越大的负电压，并且将第三电压范围中的第三负电压同时施加到至少一个取消选择的字线。本发明的另一实施例增加了所选择的源极线电压，以实现选择被擦除的闪光晶体管的栅极和源极之间的高电压差。本发明的优点包括快速擦除程序，这是由于在被选择被擦除的闪光晶体管的栅极和源极之间施加的电压差增大。此外，由于取消选择的字线也被斜变为负电压，所以在取消选择的字线驱动器上的应力减小，从而增加了闪存的使用寿命。

25. 发明授权

US5859571A Frequency trimmable oscillator and frequency multiplier 失效
标题翻译：频率可调振荡器和倍频器
公开(公告)号：US5859571A
公开(公告)日：1999-01-12
申请号：US814913
申请日：1997-03-11
申请人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
发明人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
IPC分类号： G11C11/56 , G11C16/14 , G11C16/16 , H03K3/0231 , H03B19/14 , H03K3/354
CPC分类号： H03K3/0231 , G11C11/5628 , G11C11/5635 , G11C16/14 , G11C16/16 , G11C2211/5645
摘要： A pure MOS-implementable oscillator requires no trimming to make the oscillation frequency Vdd independent, but permits trimming to compensate for process and fabrication variations. A current generator creates a core reference current Iosc0, mirrored programmable trim currents, and dynamic reference voltages that do not require a constant Vdd source. A programmable delay unit provides value-programmable capacitors that receive mirrored currents A.times.(M/N).times.Iosc0, where A is a MOS channel W/L ratio constant, and M and N are integers. The currents create ramp-like voltage signals across the capacitors, the slewrate being A.times.(M/N).times.Iosc0/capacitance. A comparator unit compares the ramp-like signals, which ramp-down from Vdd, against a (Vdd-Vt) reference voltage (Vt being a MOS threshold voltage). The comparator unit outputs complementary signals that toggle a set-reset flipflop, whose output is the oscillator output signal. This signal is fedback to the programmable delay unit to toggle on and off the current flow that determines oscillation period. Frequency change due to discrepancies between anticipated and realized load resistors and capacitors may be coarse and/or fine trimmed, for example by incrementally varying M and/or by turning-on a current-providing MOS device having an appropriate W/L value for A. The oscillator includes two programmable delay paths and can accept an input oscillator signal and output a signal whose frequency is a non-integer or integer multiple, simply by varying capacitor ratios.
摘要翻译：纯MOS可实现的振荡器不需要修整以使振荡频率Vdd独立，但允许修整以补偿工艺和制造变化。电流发生器产生核心参考电流Iosc0，镜像可编程微调电流和不需要恒定Vdd源的动态参考电压。可编程延迟单元提供接收镜像电流Ax（M / N）xIosc0的值可编程电容器，其中A是MOS通道W / L比常数，M和N是整数。电流在电容器两端产生斜坡状电压信号，摆率为Ax（M / N）xIosc0 /电容。比较器单元将从Vdd斜降的斜坡信号与（Vdd-Vt）参考电压（Vt为MOS阈值电压）进行比较。比较器单元输出互补信号，其触发设置复位触发器，其输出是振荡器输出信号。该信号被反馈到可编程延迟单元以打开和关闭确定振荡周期的电流。由于预期和实现的负载电阻器和电容器之间的差异导致的频率变化可以是粗略和/或微调，例如通过逐渐改变M和/或通过接通具有适当W / L值的电流提供MOS器件该振荡器包括两个可编程延迟路径，并且可以简单地通过改变电容器比率来接受输入振荡器信号并输出频率为非整数或整数倍的信号。

26. 发明授权

US5856945A Method for preventing sub-threshold leakage in flash memory cells to achieve accurate reading, verifying, and fast over-erased Vt correction 失效
标题翻译：用于防止闪存单元中的亚阈值泄漏以实现精确读取，验证和快速过擦除Vt校正的方法
公开(公告)号：US5856945A
公开(公告)日：1999-01-05
申请号：US906198
申请日：1997-08-05
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao
IPC分类号： G11C11/56 , G11C16/04 , G11C16/34 , H01L27/115 , G11C16/06
CPC分类号： G11C16/3409 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0416 , G11C16/34 , G11C16/3404 , G11C16/3413 , G11C16/3418 , H01L27/115 , G11C2216/20
摘要： The present invention provides a method for preventing sub-threshold leakage in flash EPROM cells during Vt repair, read and verify operations. The present invention prevents sub-threshold leakage by either biasing the floating gate voltage of non-selected cells to a level that is less than the sources voltage. This biasing is achieved by controlling the voltages applied to such non-selected cells bitline and wordline voltages, or by floating the non-selected sourcelines to electrically disconnect the sourcelines of the non-selected cells. This method allows fast and accurate Vt repair of cells while avoiding Vt degradation of non-erased and repaired cells due to subthreshold current leakage, as well as reduced sub-threshold leakage during read and verify operations.
摘要翻译：本发明提供一种在Vt修复，读取和验证操作期间防止闪存EPROM单元中的次阈值泄漏的方法。本发明通过将未选择的单元的浮置栅极电压偏置到小于源极电压的水平来防止亚阈值泄漏。通过控制施加到这种未选择的单元位线和字线电压的电压，或者通过浮动未选择的电源线来电连接未选择的单元的源极线来实现该偏置。该方法允许快速且准确的Vt修复细胞，同时避免由于亚阈值电流泄漏而导致的未擦除和修复的细胞的Vt劣化，以及在读取和验证操作期间降低的亚阈值泄漏。

27. 发明授权

US5600586A Flat-cell ROM and decoder 失效
标题翻译：平板ROM和解码器
公开(公告)号：US5600586A
公开(公告)日：1997-02-04
申请号：US279682
申请日：1994-07-25
申请人： Peter W. Lee
发明人： Peter W. Lee
IPC分类号： H01L27/112 , G11C17/12 , H01L21/8246 , G11C17/00
CPC分类号： G11C17/126
摘要： A flat-cell ROM array includes a bank of field effect transistors, each having a source, drain and gate, formed by ion implantation between columns of buried N+ and under rows of polysilicon, wherein adjacent columns of buried N+ are the source and drain of at least one transistor and a corresponding row of polysilicon is the gate of the transistor. Each of these transistors is programmed to have one of a plurality of threshold voltages depending on a desired storage value. Attached to the bank of transistors is an upper selector network associated with the bank connected to a first class of alternating sets of the columns, and a lower selector network associated with the bank connected to a second class of alternating sets of the columns. A method provides steps for performing the present invention.
摘要翻译：平面单元ROM阵列包括一组场效应晶体管，每一个具有源极，漏极和栅极，通过离子注入在掩埋N +的列之间和下行多晶硅之间形成，其中相邻的掩埋N +列是源极和漏极至少一个晶体管和对应的多晶硅行是晶体管的栅极。根据期望的存储值，将这些晶体管中的每一个编程为具有多个阈值电压中的一个。连接到晶体管组的是与连接到第一类交替列列的存储体相关联的上选择器网络，以及与连接到第二类交替列列的存储体相关联的下选择器网络。一种方法提供了执行本发明的步骤。

28. 发明授权

US4601592A Tapered roller bearing capable of sustained operation without lubricant replenishment 失效
标题翻译：圆锥滚子轴承能够持续运行，无需润滑剂补充
公开(公告)号：US4601592A
公开(公告)日：1986-07-22
申请号：US578025
申请日：1984-02-08
申请人： Chester F. Jatczak , Peter W. Lee , Peter S. Orvos
发明人： Chester F. Jatczak , Peter W. Lee , Peter S. Orvos
IPC分类号： F16C19/36 , F16C19/52 , F16C33/60 , F16C33/66 , F16C33/58 , F16C33/36
CPC分类号： F16C33/605 , F16C19/364 , F16C33/4605 , F16C33/543 , F16C33/6648 , Y10S384/902
摘要： A tapered roller bearing has a porous rib ring against which the large ends of its wrought steel tapered rollers bear so that the ring prevents the rollers from being expelled. The rib ring is formed from porous powdered steel that has been compacted to a density of about 70% to 85% of theoretical and then sintered and machined. Thereafter, the machined rib ring is etched to expose the pores at the surface against which the large ends of the rollers bear. Finally, the rib ring is impregnated with oil. Should the bearing lose its normal supply of lubrication, the critical region of contact between the abutment face on the rib ring and the large ends of the rollers will nevertheless be adequately lubricated for a reasonable time by lubricant which escapes from the pores of the rib ring. The cage of the bearing may be piloted by the rib ring and by a ring-like cup insert that is formed in the same manner as the rib ring.
摘要翻译：圆锥滚子轴承具有多孔肋环，其锻造圆锥滚子的大端承受着多个肋环，使得环防止辊被排出。肋环由多孔粉末状钢制成，其已被压实成理论值的约70％至85％的密度，然后烧结和加工。此后，对机加工的肋环进行蚀刻以暴露出辊的大端承载的表面的孔。最后，肋环用油浸渍。如果轴承失去正常的润滑润滑，则肋环上的邻接面与辊的大端之间的临界接触区域在合理的时间内将通过从肋环孔隙逸出的润滑剂充分润滑。轴承的保持架可以由肋环和与肋环相同的方式形成的环状杯形插入件引导。

29. 发明授权

US08775719B2 NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with parallel interface 失效
标题翻译：基于NAND的混合NVM设计，在单模并行接口中集成NAND和NOR
公开(公告)号：US08775719B2
公开(公告)日：2014-07-08
申请号：US12807996
申请日：2010-09-17
申请人： Peter W. Lee , Fu-Chang Hsu , Kesheng Wang
发明人： Peter W. Lee , Fu-Chang Hsu , Kesheng Wang
IPC分类号： G06F12/00
CPC分类号： G11C16/10 , G11C7/1006 , G11C7/1012 , G11C7/1051 , G11C7/1075 , G11C2216/22
摘要： A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A parallel interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the parallel interface at the rising edge and the falling edge of the synchronizing clock. The parallel interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. Reading one nonvolatile memory array may be interrupted for reading another. One reading operation has two sub-addresses with one transferred prior to a command.
摘要翻译：非易失性存储器件包括多个独立的非易失性存储器阵列，用于并行读写非易失性存储器阵列。并行接口在主设备和非易失性存储器阵列之间传送命令，地址，设备状态和数据，用于同时读写非易失性存储器阵列和子阵列。数据在同步时钟的上升沿和下降沿在并行接口上传输。并行接口从主设备发送命令代码和地址代码，并在主设备和非易失性存储设备之间传送数据代码，其中数据代码具有由命令代码确定的长度和由地址代码读取一个非易失性存储器阵列可能会中断读取另一个。一次读取操作具有两个子地址，一个命令之前传送一个。

30. 发明申请

US20110072200A1 Novel NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with parallel interface 失效
标题翻译：新型基于NAND的混合NVM设计，将NAND和NOR集成在1模并行接口中
公开(公告)号：US20110072200A1
公开(公告)日：2011-03-24
申请号：US12807996
申请日：2010-09-17
申请人： Peter W. Lee , Fu-Chang Hsu , Kesheng Wang
发明人： Peter W. Lee , Fu-Chang Hsu , Kesheng Wang
IPC分类号： G06F12/02 , G11C16/06
CPC分类号： G11C16/10 , G11C7/1006 , G11C7/1012 , G11C7/1051 , G11C7/1075 , G11C2216/22
摘要： A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A parallel interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the parallel interface at the rising edge and the falling edge of the synchronizing clock. The parallel interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. Reading one nonvolatile memory array may be interrupted for reading another. One reading operation has two sub-addresses with one transferred prior to a command.
摘要翻译：非易失性存储器件包括多个独立的非易失性存储器阵列，用于并行读写非易失性存储器阵列。并行接口在主设备和非易失性存储器阵列之间传送命令，地址，设备状态和数据，用于同时读写非易失性存储器阵列和子阵列。数据在同步时钟的上升沿和下降沿在并行接口上传输。并行接口从主设备发送命令代码和地址代码，并在主设备和非易失性存储设备之间传送数据代码，其中数据代码具有由命令代码确定的长度和由地址代码读取一个非易失性存储器阵列可能会中断读取另一个。一次读取操作具有两个子地址，一个命令之前传送一个。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式