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21. 发明授权

US07849454B2 Automatic firmware corruption recovery and update 有权
标题翻译：自动固件损坏恢复和更新
公开(公告)号：US07849454B2
公开(公告)日：2010-12-07
申请号：US11331509
申请日：2006-01-13
申请人： Timothy Lambert , Stephen Cochran , Pedro Lopez
发明人： Timothy Lambert , Stephen Cochran , Pedro Lopez
IPC分类号： G06F9/44 , G06F9/45
CPC分类号： G06F11/0793 , G06F8/654 , G06F11/0709 , G06F11/1417
摘要： Firmware for a baseboard management controller (BMC) of a blade server module in an information handling system may have automatic firmware corruption recovery and updating through a TFTP transfer from a central storage location having the most recent BMC firmware image. Upon blade power-on or reset the BMC firmware image is checked for corruption and if corrupted a new BMC firmware image is loaded into the BMC memory. If the BMC firmware image is not corrupted then it is checked to determine if it is the latest version. If it is the latest version the BMC starts normal program execution. If not the latest version then the BMC firmware is updated through the TFTP transfer from the central storage location having the most recent BMC firmware image.
摘要翻译：用于信息处理系统中的刀片服务器模块的基板管理控制器（BMC）的固件可以具有通过从具有最新BMC固件映像的中央存储位置的TFTP传输的自动固件损坏恢复和更新。在刀片上电或复位时，BMC固件映像被检查是否损坏，如果损坏，则将新的BMC固件映像加载到BMC存储器中。如果BMC固件映像没有被破坏，则检查它是否是最新版本。如果是最新版本，BMC启动正常的程序执行。如果不是最新版本，则通过从具有最新BMC固件映像的中央存储位置通过TFTP传输来更新BMC固件。

22. 发明申请

US20100262812A1 REGISTER CHECKPOINTING MECHANISM FOR MULTITHREADING 有权
标题翻译：注册检查机制进行多元化
公开(公告)号：US20100262812A1
公开(公告)日：2010-10-14
申请号：US12420762
申请日：2009-04-08
申请人： Pedro Lopez , Carlos Madriles , Alejandro Martinez , Raul Martinez , Josep M. Codina , Enric Gibert Codina , Fernando Latorre , Antonio Gonzalez
发明人： Pedro Lopez , Carlos Madriles , Alejandro Martinez , Raul Martinez , Josep M. Codina , Enric Gibert Codina , Fernando Latorre , Antonio Gonzalez
IPC分类号： G06F9/30
CPC分类号： G06F9/3863 , G06F9/30043 , G06F9/3842 , G06F9/3851 , G06F11/1402
摘要： Methods and apparatus are disclosed for using a register checkpointing mechanism to resolve multithreading mis-speculations. Valid architectural state is recovered and execution is rolled back. Some embodiments include memory to store checkpoint data. Multiple thread units concurrently execute threads. They execute a checkpoint mask instruction to initialize memory to store active checkpoint data including register contents and a checkpoint mask indicating the validity of stored register contents. As register contents change, threads execute checkpoint write instructions to store register contents and update the checkpoint mask. Threads also execute a recovery function instruction to store a pointer to a checkpoint recovery function, and in response to mis-speculation among the threads, branch to the checkpoint recovery function. Threads then execute one or more checkpoint read instructions to copy data from a valid checkpoint storage area into the registers necessary to recover a valid architectural state, from which execution may resume.
摘要翻译：公开了使用寄存器检查点机制来解决多线程错误猜测的方法和装置。恢复有效的架构状态并回滚执行。一些实施例包括用于存储检查点数据的存储器。多个线程单元同时执行线程。它们执行检查点掩码指令来初始化存储器以存储包括寄存器内容的活动检查点数据和指示存储的寄存器内容的有效性的检查点掩码。随着寄存器内容的改变，线程执行检查点写入指令来存储寄存器内容并更新检查点掩码。线程还执行恢复功能指令来存储指向检查点恢复功能的指针，并且响应于线程之间的误推测，分支到检查点恢复功能。线程然后执行一个或多个检查点读取指令，以将数据从有效的检查点存储区域复制到恢复有效架构状态所需的寄存器，从中可以恢复执行。

23. 发明申请

US20070226377A1 Detecting parameters of a system UART and matching those parameters in a serial-over-LAN (SOL) UART 审中-公开
标题翻译：检测系统UART的参数，并将这些参数与LAN串行（SOL）UART匹配
公开(公告)号：US20070226377A1
公开(公告)日：2007-09-27
申请号：US11350458
申请日：2006-02-09
申请人： Elie Jreij , Wai-ming Chan , Anand Joshi , Pedro Lopez
发明人： Elie Jreij , Wai-ming Chan , Anand Joshi , Pedro Lopez
IPC分类号： G06F3/00
CPC分类号： G06F13/385
摘要： An information handling system has the capability of matching UART baud rates and other serial data parameters between a system UART and baseboard management controller (BMC) UART used for serial-over-LAN (SOL) access to the information handling system via an Ethernet connection, either locally or remotely by a user, administrator, maintenance technician, etc. The BMC may snoop set-up data sent to the control register(s) of the system UART, look up a corresponding baud rate from a baud rate table of the BMC and set the BMC UART to match the system UART baud rate and other serial data parameters so that SOL access to the information handling system is available no matter what baud rate and/or serial data parameters an application may have programmed the system UART configuration registers. The BMC may snoop system UART data over a simple data bus such a low pin count (LPC) bus.
摘要翻译：信息处理系统具有通过以太网连接在系统UART和用于串行LAN（SOL）访问信息处理系统的系统UART和基板管理控制器（BMC）UART之间匹配UART波特率和其他串行数据参数的功能，本地或远程用户，管理员，维护技术人员等。BMC可以窥探发送到系统UART的控制寄存器的设置数据，从BMC的波特率表中查找相应的波特率并设置BMC UART以匹配系统UART波特率和其他串行数据参数，以便SOL访问信息处理系统可用，无论应用程序可以编程系统UART配置寄存器的波特率和/或串行数据参数。 BMC可以通过简单的数据总线监听系统UART数据，如低引脚数（LPC）总线。

24. 发明授权

US09158705B2 Stride-based translation lookaside buffer (TLB) prefetching with adaptive offset 有权
标题翻译：基于Stride的翻译后备缓冲器（TLB）预取与自适应偏移
公开(公告)号：US09158705B2
公开(公告)日：2015-10-13
申请号：US13799582
申请日：2013-03-13
申请人： Jaroslaw Topp , Pedro Lopez , Fernando Latorre , Demos Pavlou , Thang Vu
发明人： Jaroslaw Topp , Pedro Lopez , Fernando Latorre , Demos Pavlou , Thang Vu
IPC分类号： G06F12/00 , G06F12/10 , G06F12/08
CPC分类号： G06F12/1027 , G06F12/0862 , G06F2212/602 , G06F2212/6026 , G06F2212/654
摘要： A processing device implementing stride-based translation lookaside buffer (TLB) prefetching with adaptive offset is disclosed. A processing device of the disclosure includes a data prefetcher to generate a data prefetch address based on a linear address, a stride, or a prefetch distance, the data prefetch address associated with a data prefetch request, and a TLB prefetch address computation component to generate a TLB prefetch address based on the linear address, the stride, the prefetch distance, or an adaptive offset. The processing device also includes a cross page detection component to determine that the data prefetch address or the TLB prefetch address cross a page boundary associated with the linear address, and cause a TLB prefetch request to be written to a TLB request queue, the TLB prefetch request for translation of an address of a linear page number (LPN) based on the data prefetch address or the TLB prefetch address.
摘要翻译：公开了一种利用自适应偏移实现基于步幅翻译后备缓冲器（TLB）预取的处理装置。本公开的处理设备包括数据预取器，用于基于线性地址，步幅或预取距离生成数据预取地址，与数据预取请求相关联的数据预取地址以及TLB预取地址计算组件以产生基于线性地址，步幅，预取距离或自适应偏移的TLB预取地址。该处理设备还包括一个跨页检测组件，用于确定数据预取地址或TLB预取地址与与线性地址相关联的页边界交叉，并且使TLB预取请求被写入TLB请求队列，TLB预取基于数据预取地址或TLB预取地址来请求翻译线性页码（LPN）的地址。

25. 发明申请

US20140181388A1 Method And Apparatus To Implement Lazy Flush In A Virtually Tagged Cache Memory 有权
标题翻译：在几乎标记的高速缓冲存储器中实现懒惰冲洗的方法和装置
公开(公告)号：US20140181388A1
公开(公告)日：2014-06-26
申请号：US13724848
申请日：2012-12-21
申请人： Varun K. Mohandru , Fernando Latorre , NIRANJAN L. COORAY , Pedro Lopez , NAVEEN NEELAKANTAM , LI-GAO ZEI , RAMI MAY , JAROSLAW TOPP , THOMAS GAERTNER
发明人： Varun K. Mohandru , Fernando Latorre , NIRANJAN L. COORAY , Pedro Lopez , NAVEEN NEELAKANTAM , LI-GAO ZEI , RAMI MAY , JAROSLAW TOPP , THOMAS GAERTNER
IPC分类号： G11C7/10 , G06F12/08
CPC分类号： G11C7/1072 , G06F12/0804 , G06F12/0891 , G06F12/1036
摘要： A processor includes a processor core including an execution unit to execute instructions, and a cache memory. The cache memory includes a controller to update each of a plurality of stale indicators in response to a lazy flush instruction. Each stale indicator is associated with respective data, and each updated stale indicator is to indicate that the respective data is stale. The cache memory also includes a plurality of cache lines. Each cache line is to store corresponding data and a foreground tag that includes a respective virtual address associated with the corresponding data, and that includes the associated stale indicator. Other embodiments are described as claimed.
摘要翻译：处理器包括处理器核心，其包括执行指令的执行单元和高速缓冲存储器。高速缓冲存储器包括控制器，以响应于惰性冲洗指令来更新多个陈旧指示器中的每一个。每个陈旧的指示符与相应的数据相关联，每个更新的陈旧指示符指示相应的数据是否过时。高速缓冲存储器还包括多条高速缓存行。每个高速缓存行将存储对应的数据和前景标签，其包括与对应的数据相关联的相应的虚拟地址，并且其包括相关联的陈旧指示符。其他实施例被描述为所要求保护的。

26. 发明申请

US20140156976A1 METHOD, APPARATUS AND SYSTEM FOR SELECTIVE EXECUTION OF A COMMIT INSTRUCTION 审中-公开
标题翻译：方法，选择性执行委托指令的方法和系统
公开(公告)号：US20140156976A1
公开(公告)日：2014-06-05
申请号：US13995441
申请日：2011-12-22
申请人： Enric Gibert Codina , Josep M. Codina , Fernando Latorre , Pedro Marcuello , Pedro Lopez , Crispin Gomez Requena , Antonio Gonzalez , Mirem Hyuseinova , Christos E. Kotselidis , Marc Lupon , Carlos Madriles Gimeno , Grigorios Magklis , Alejandro Martinez Vicente , Raul Martinez , Daniel Ortega , Demos Pavlou , Kyriakos A. Stavrou , Georgios Tournavitis , Polychronis Xekalakis
发明人： Enric Gibert Codina , Josep M. Codina , Fernando Latorre , Pedro Marcuello , Pedro Lopez , Crispin Gomez Requena , Antonio Gonzalez , Mirem Hyuseinova , Christos E. Kotselidis , Marc Lupon , Carlos Madriles Gimeno , Grigorios Magklis , Alejandro Martinez Vicente , Raul Martinez , Daniel Ortega , Demos Pavlou , Kyriakos A. Stavrou , Georgios Tournavitis , Polychronis Xekalakis
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30087 , G06F9/30185 , G06F9/3842 , G06F9/3857 , G06F9/3863
摘要： Techniques and mechanisms for a processor to determine whether a commit action is to be performed. In an embodiment, a processor performs operations to determine whether a commit instruction is for contingent performance of a commit action. In another embodiment, one or more conditions of processor state are evaluated in response to determining that the commit instruction is for contingent performance of the commit action, where the evaluation is performed to determine whether the commit action indicated by the commit instruction is to be performed.
摘要翻译：处理器确定是否执行提交动作的技术和机制。在一个实施例中，处理器执行操作以确定提交指令是否用于或然执行提交动作。在另一个实施例中，响应于确定提交指令用于提交动作的或然执行来评估处理器状态的一个或多个条件，其中执行评估以确定是否要执行由提交指令指示的提交动作。

27. 发明申请

US20100115247A1 REPLACEMENT POLICY FOR HOT CODE DETECTION 有权
标题翻译：替代热代码检测政策
公开(公告)号：US20100115247A1
公开(公告)日：2010-05-06
申请号：US12263418
申请日：2008-10-31
申请人： Pedro Lopez , F. Jesus Sanchez , Josep M. Codina , Enric Gibert , Fernando Latorre , Grigorios Magklis , Pedro Marcuello , Antonio Gonzalez
发明人： Pedro Lopez , F. Jesus Sanchez , Josep M. Codina , Enric Gibert , Fernando Latorre , Grigorios Magklis , Pedro Marcuello , Antonio Gonzalez
IPC分类号： G06F9/30 , G06F9/06
CPC分类号： G06F11/3419 , G06F11/3466 , G06F2201/81 , G06F2201/88 , G06F2201/885
摘要： Methods and apparatus relating to a replacement policy for hot code detection are described. In some embodiments, it may be determined which entry amongst a plurality of entries stored in storage unit is to be replaced next. The entries may correspond to hot code and may store age and execution frequency information corresponding to the hot code. Other embodiments are also described and claimed.
摘要翻译：描述与热代码检测的替换策略有关的方法和装置。在一些实施例中，可以确定存储在存储单元中的多个条目中的哪个条目将被替换。这些条目可以对应于热代码，并且可以存储对应于热代码的年龄和执行频率信息。还描述和要求保护其他实施例。

28. 发明申请

US20080005222A1 System and Method for Server Information Handling System Management Through Local I/O Devices 审中-公开
标题翻译：通过本地I / O设备处理系统管理的服务器信息的系统和方法
公开(公告)号：US20080005222A1
公开(公告)日：2008-01-03
申请号：US11422628
申请日：2006-06-07
申请人： Timothy M. Lambert , Pedro Lopez
发明人： Timothy M. Lambert , Pedro Lopez
IPC分类号： G06F15/16
CPC分类号： G06F13/387 , G06F3/0227 , G06F3/023
摘要： A server information handling system integrated management controller selectively communicates management information between a baseboard management controller and either a network remote console session or local I/O devices, such as a display, a keyboard, a mouse or a KVM appliance. Display information is communicated from the baseboard management controller to a display by writing from the baseboard management controller through a unified memory controller to a display frame buffer for presentation at the display. Keyboard, mouse and KVM information is communicated through a USB host to the baseboard management controller or, in an operational state, is communicated from the USB host to a USB client for use by the server information handling system. In an operational state, a break sequence selectively interfaces the I/O devices with the server information handling system or the baseboard management controller.
摘要翻译：服务器信息处理系统集成管理控制器选择性地在基板管理控制器与网络远程控制台会话或本地I / O设备（诸如显示器，键盘，鼠标或KVM设备）之间传送管理信息。通过从基板管理控制器通过统一的存储器控制器写入显示器信息，从基板管理控制器向显示器传送显示帧缓冲器以在显示器上呈现。键盘，鼠标和KVM信息通过USB主机传送到基板管理控制器，或者在操作状态下从USB主机传送到USB客户端以供服务器信息处理系统使用。在操作状态下，断点序列选择性地将I / O设备与服务器信息处理系统或基板管理控制器接口。

29. 发明申请

US20070016827A1 Systems and methods for providing remotely accessible in-system emulation and/or debugging 有权
标题翻译：用于提供远程可访问的系统仿真和/或调试的系统和方法
公开(公告)号：US20070016827A1
公开(公告)日：2007-01-18
申请号：US11183380
申请日：2005-07-18
申请人： Pedro Lopez , Timothy Lambert
发明人： Pedro Lopez , Timothy Lambert
IPC分类号： G06F11/00
CPC分类号： G06F11/2294 , G06F11/261
摘要： An information handling system providing remotely accessible in-system debugging functionality is provided. The information handling system may include a first logic device and a remote access card distinct from the first logic device. The remote access card may include a network interface port, a processor, and a second logic device. The network interface port may be coupled to the second logic device and configured to receive a communications link for communications with a remote device. The second logic device may include debugging logic configured to be executed by the processor. The processor may be configured to receive debugging instructions from the remote device via the network interface port and, based at least on the received debugging instructions, execute the debugging logic to communicate with the first logic device via a communication link between the first logic device and the second logic device to facilitate remote debugging of the information handling system.
摘要翻译：提供了提供远程可访问的系统内调试功能的信息处理系统。信息处理系统可以包括与第一逻辑设备不同的第一逻辑设备和远程访问卡。远程访问卡可以包括网络接口端口，处理器和第二逻辑设备。网络接口端口可以耦合到第二逻辑设备并且被配置为接收用于与远程设备通信的通信链路。第二逻辑设备可以包括被配置为由处理器执行的调试逻辑。处理器可以被配置为经由网络接口端口从远程设备接收调试指令，并且至少基于所接收的调试指令，执行调试逻辑以经由第一逻辑设备和第一逻辑设备之间的通信链路与第一逻辑设备通信第二个逻辑设备便于信息处理系统的远程调试。

30. 发明申请

US20060265656A1 System and method for managing information handling system service communication 审中-公开
标题翻译：用于管理信息处理系统服务通信的系统和方法
公开(公告)号：US20060265656A1
公开(公告)日：2006-11-23
申请号：US11134966
申请日：2005-05-23
申请人： Timothy Lambert , Pedro Lopez
发明人： Timothy Lambert , Pedro Lopez
IPC分类号： G06F17/00
CPC分类号： G06Q10/00
摘要： A technical support button accepts user activation to request a technical support session for an information handling system. For instance, activation of technical support sends an electronic message, such as an e-mail or instant message, to a technical support site that includes technical support information for establishing a technical support session, such as identification and diagnostics information. The technical support session is established through the information handling system to aid a technical support agent in investigating the system directly while communicating with the user of the system. For instance, VoIP communication is established through a management subsystem that operates on auxiliary power so that a technical support session is supported even if the information handling system is powered down or inoperative.
摘要翻译：技术支持按钮接受用户激活以请求信息处理系统的技术支持会话。例如，技术支持的激活将电子消息（例如电子邮件或即时消息）发送到技术支持站点，该技术支持站点包括用于建立技术支持会话的技术支持信息，例如识别和诊断信息。通过信息处理系统建立技术支持会议，以帮助技术支持代理人直接调查系统，同时与系统的用户进行通信。例如，通过在辅助电源上操作的管理子系统建立VoIP通信，使得即使信息处理系统断电或不起作用也支持技术支持会话。

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