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21. 发明申请

US20070055845A1 Self-reparable semiconductor and method thereof 有权
公开(公告)号：US20070055845A1
公开(公告)日：2007-03-08
申请号：US11594312
申请日：2006-11-08
申请人： Sehat Sutardja , Pantas Sutardja
发明人： Sehat Sutardja , Pantas Sutardja
IPC分类号： G06F11/00
CPC分类号： H01L22/22 , G06F11/2028 , G06F11/2038 , G06F11/2051 , G11C29/848 , H01L2924/0002 , H01L2924/00
摘要： A self-reparable semiconductor comprises first and second physical layer devices each including first and second subfunctional units that cooperate to provide first and second ports associated with a multi-bit Gigabit physical layer device. A first spare physical layer device includes first and second subfunctional units. The first sub-functional units are functionally interchangeable. The second sub-functional units are functionally interchangeable. Switching devices communicate with the first and second subfunctional units of the first, second and first spare physical layer devices and replace at least one of the first and second sub-functional units of at least one of the first and second physical layer devices with at least one of the first and second sub-functional units of the first spare physical layer device when the at least one of the first and second sub-functional units is non-operable.

22. 再颁专利

USRE37335E1 Ripple carry logic and method 有权
标题翻译：纹波携带逻辑和方法
公开(公告)号：USRE37335E1
公开(公告)日：2001-08-21
申请号：US09585343
申请日：2000-06-02
申请人： Sehat Sutardja , Pantas Sutardja
发明人： Sehat Sutardja , Pantas Sutardja
IPC分类号： G11C1900
CPC分类号： G11C21/005 , G11C19/00
摘要： Apparatus and method to logically process signals representative of multiple bits of multiple-bit numbers include successively delaying applications of the bit-representative signals to logical processing stages from associated input registers by a delay interval between input registers that is substantially equal to the processing delay interval per bit-level processing stage. In this way, successively more significant bits of each of plural numbers being logically processed are validly available for processing at each bit-level logic stage after a delay that is substantially equal to the processing delay interval of a preceding bit-level logic stage. Similarly, output registers for latching the logic output of each bit-level logic stage are clocked at successively delayed intervals substantially equal to the processing delay interval, and carry output from preceding logic stages are supplied to carry inputs of successive logic stages without additional delays following the processing delay interval of each preceding logic stage.
摘要翻译：用于逻辑地处理表示多位数位的多个比特的信号的装置和方法包括将来自相关联的输入寄存器的位代表信号到逻辑处理级的应用连续地延迟输入寄存器之间的延迟间隔，其基本上等于处理延迟间隔每个位级处理阶段。以这种方式，在逻辑处理的多个数字中的每一个的连续更多有效位有效地可用于在基本上等于先前位级逻辑级的处理延迟间隔的延迟之后的每个位级逻辑级处理。类似地，用于锁存每个位级逻辑级的逻辑输出的输出寄存器以基本上等于处理延迟间隔的连续延迟的时间间隔进行计时，并且提供来自先前逻辑级的进位输出以承载连续逻辑级的输入，而不需要额外的延迟每个前一逻辑级的处理延迟间隔。

23. 发明授权

US5576647A Charge pump for phase lock loop 失效
标题翻译：电荷泵用于锁相环
公开(公告)号：US5576647A
公开(公告)日：1996-11-19
申请号：US493799
申请日：1995-06-22
申请人： Pantas Sutardja , Sehat Sutardja
发明人： Pantas Sutardja , Sehat Sutardja
IPC分类号： H03K3/0231 , H03L7/089 , H03L7/099 , H03K5/13 , H03L7/093
CPC分类号： H03K3/0231 , H03L7/0895 , H03L7/0995
摘要： A monolithic CMOS phase-lock loop (PLL) circuit provides a high frequency of operation suitable for RF applications. The PLL produces an output clock with high spectral purity and very low jitter. The output clock has a low static phase error relative to a reference input, making the PLL also useful for clock synchronizing applications, such as clock recovery elements in transmission/recording channels. The PLL provides in-phase and quadrature signals from a VCO which has two differential transconductor stages having negative output conductance. The PLL also includes a charge pump using transistors driven by high speed switching drivers.
摘要翻译：单片CMOS锁相环（PLL）电路提供适合RF应用的高频操作。 PLL产生具有高光谱纯度和非常低抖动的输出时钟。输出时钟相对于参考输入具有较低的静态相位误差，使得PLL对于时钟同步应用（如发送/录制通道中的时钟恢复元件）也很有用。 PLL提供来自VCO的同相和正交信号，该VCO具有负输出电导的两个差分跨导级。 PLL还包括使用由高速开关驱动器驱动的晶体管的电荷泵。

24. 发明申请

US20130057163A1 REGULATOR FOR LED LIGHTING COLOR MIXING 有权
标题翻译： LED照明颜色混合调节器
公开(公告)号：US20130057163A1
公开(公告)日：2013-03-07
申请号：US13589937
申请日：2012-08-20
申请人： Sehat Sutardja , Pantas Sutardja , Wanfeng Zhang
发明人： Sehat Sutardja , Pantas Sutardja , Wanfeng Zhang
IPC分类号： H05B37/00
CPC分类号： H05B33/0815 , H05B33/0857 , Y02B20/347
摘要： A system includes a first light emitting diode configured to produce light of a first color and a second light emitting diode configured to produce light of a second color. A constant current circuit is configured to provide a first current, wherein (i) the first current is approximately constant, (ii) a first portion of the first current flows through the second light emitting diode, and (iii) a remaining portion of the first current flows through the first light emitting diode. A current regulating circuit is configured to control the first portion of the first current flowing through the second light emitting diode. The current regulating circuit is connected in series with the second light emitting diode, the constant current circuit, and a reference potential. The first light emitting diode is connected in series directly between the constant current circuit and the reference potential.
摘要翻译：一种系统包括被配置为产生第一颜色的光的第一发光二极管和被配置为产生第二颜色的光的第二发光二极管。恒流电路被配置为提供第一电流，其中（i）第一电流近似恒定，（ii）第一电流的第一部分流过第二发光二极管，以及（iii）剩余部分第一电流流过第一发光二极管。电流调节电路被配置为控制流过第二发光二极管的第一电流的第一部分。电流调节电路与第二发光二极管，恒流电路和参考电位串联。第一个发光二极管直接连接在恒流电路和参考电位之间。

25. 发明授权

US07657784B2 Self-reparable semiconductor and method thereof 有权
标题翻译：自修复半导体及其方法
公开(公告)号：US07657784B2
公开(公告)日：2010-02-02
申请号：US11594537
申请日：2006-11-08
申请人： Sehat Sutardja , Pantas Sutardja
发明人： Sehat Sutardja , Pantas Sutardja
IPC分类号： G06F11/00
CPC分类号： H01L22/22 , G06F11/2028 , G06F11/2038 , G06F11/2051 , G11C29/848 , H01L2924/0002 , H01L2924/00
摘要： A self-reparable semiconductor comprises M functional units each including N sub-functional units. Corresponding ones of the N sub-functional units in each of the M functional units perform the same function. At least two of the N sub-functional units in one of the M functional units perform different functions. A first spare functional unit includes X sub-functional units, wherein X is greater than or equal to one and less than or equal to N and wherein the X sub-functional units of. the first spare functional unit are functionally interchangeable with corresponding sub-functional units of the M functional units and wherein the X sub-functional units are provided for the at least two of the N sub-functional units. A plurality of switching devices replace at least one of the N sub-functional units with at least one of the X sub-functional units when the at least one of the N sub-functional units is non-operable.
摘要翻译：自修复半导体包括各自包括N个子功能单元的M个功能单元。每个M个功能单元中的N个子功能单元中的相应的功能单元执行相同的功能。 M个功能单元之一中的N个子功能单元中的至少两个执行不同的功能。第一备用功能单元包括X个子功能单元，其中X大于或等于1且小于或等于N，并且其中X个子功能单元。第一备用功能单元与功能单元的相应子功能单元功能上可互换，并且其中为N个子功能单元中的至少两个提供了X个子功能单元。当N个子功能单元中的至少一个不可操作时，多个交换设备用至少一个X子功能单元替换N个子功能单元中的至少一个。

26. 发明申请

US20080215914A1 Self-reparable semiconductor and method thereof 有权
标题翻译：自修复半导体及其方法
公开(公告)号：US20080215914A1
公开(公告)日：2008-09-04
申请号：US12074557
申请日：2008-03-04
申请人： Sehat Sutardja , Pantas Sutardja , William Lo
发明人： Sehat Sutardja , Pantas Sutardja , William Lo
IPC分类号： G06F11/20
CPC分类号： G01R31/317 , G01R31/31718 , G01R31/3172 , G11C29/848 , H01L22/22 , H01L2924/0002 , H01L2924/00
摘要： A self-reparable semiconductor includes multiple functional units that perform the same function and that include sub-functional units. The semiconductor includes one or more full or partial spare functional units that are integrated into the semiconductor. If a defect in a sub-functional unit is detected, then that sub-functional unit is switched out and replaced with a sub-functional unit in the full or partial spare functional unit. The reconfiguration is realized with switching devices that are associated with the sub-functional units. Defective functional or sub-functional units can be detected after assembly, during power up, periodically during operation, and/or manually.
摘要翻译：自修复半导体包括执行相同功能并且包括子功能单元的多个功能单元。半导体包括集成到半导体中的一个或多个全部或部分备用功能单元。如果检测到子功能单元中的缺陷，那么该子功能单元被切换并且被全部或部分备用功能单元中的子功能单元替换。通过与子功能单元相关联的开关设备来实现重新配置。可以在组装，上电，定期运行和/或手动期间检测功能或子功能单元的不良。

27. 发明申请

US20070055906A1 Self-reparable semiconductor and method thereof 有权
标题翻译：自修复半导体及其方法
公开(公告)号：US20070055906A1
公开(公告)日：2007-03-08
申请号：US11594390
申请日：2006-11-08
申请人： Sehat Sutardja , Pantas Sutardja
发明人： Sehat Sutardja , Pantas Sutardja
IPC分类号： G06F11/00
CPC分类号： H01L22/22 , G06F11/2028 , G06F11/2038 , G06F11/2051 , G11C29/848 , H01L2924/0002 , H01L2924/00
摘要： A self-reparable semiconductor comprises first, second and spare functional units including first and second sub-functional units that cooperate to perform first and second functions. The first and second sub-functional units of the first, second and first spare functional units are functionally interchangeable, respectively. At least one of the first and second sub-functional units of the first functional unit at least one of receives and outputs an analog signal and includes an analog circuit. Switching devices communicate with the first and second sub-functional units of the first, second and first spare functional units and replace at least one of the first and second sub-functional units of at least one of the first and second functional units with at least one of the first and second sub-functional units of the first spare functional unit when the at least one of the first and second sub-functional units is non-operable.
摘要翻译：自修复半导体包括第一，第二和备用功能单元，其包括协调以执行第一和第二功能的第一和第二子功能单元。第一，第二和第一备用功能单元的第一和第二子功能单元分别在功能上可互换。第一功能单元的第一和第二子功能单元中的至少一个至少一个接收并输出模拟信号并且包括模拟电路。交换设备与第一，第二和第一备用功能单元的第一和第二子功能单元通信，并且至少替换第一和第二功能单元中的至少一个功能单元的第一和第二子功能单元中的至少一个当第一和第二子功能单元中的至少一个不可操作时，第一备用功能单元的第一和第二子功能单元之一。

28. 发明授权

US5686867A Regulated supply for voltage controlled oscillator 失效
标题翻译：压控振荡器的稳压电源
公开(公告)号：US5686867A
公开(公告)日：1997-11-11
申请号：US657087
申请日：1996-06-03
申请人： Pantas Sutardja , Sehat Sutardja
发明人： Pantas Sutardja , Sehat Sutardja
IPC分类号： H03K3/0231 , H03L7/089 , H03L7/099 , H03L5/00
CPC分类号： H03K3/0231 , H03L7/0895 , H03L7/0995
摘要： A monolithic CMOS phase-lock loop (PLL) circuit provides a high frequency of operation suitable for RF applications. The PLL produces an output clock with high spectral purity and very low jitter. The output clock has a low static phase error relative to a reference input, making the PLL useful for clock synchronizing applications, such as clock recovery elements in transmission/recording channels. The PLL provides in-phase and quadrature signals from a voltage controlled oscillator (VCO) which has two differential transconductors. The second differential transconductor has a positive input coupled to a positive output of the first differential transconductor, a negative input coupled to a negative output of the first differential transconductor, a positive output coupled to a negative input of the first differential transconductor, and a negative output coupled to a positive input of the first differential transconductor. Each differential transconductor has a negative output impedance. Each differential transconductor includes a current controlled transconductor circuit (CCXG) and a voltage-current converter coupled to a first supply node for providing a current to the CCXG responsive to a voltage applied to a voltage control input of the differential transconductor.
摘要翻译：单片CMOS锁相环（PLL）电路提供适合RF应用的高频操作。 PLL产生具有高光谱纯度和非常低抖动的输出时钟。输出时钟相对于参考输入具有较低的静态相位误差，使PLL对时钟同步应用有用，例如传输/录制通道中的时钟恢复元件。 PLL提供具有两个差分跨导器的压控振荡器（VCO）的同相和正交信号。第二差分跨导体具有耦合到第一差分跨导体的正输出的正输入，耦合到第一差分跨导的负输出的负输入，耦合到第一差分跨导的负输入的正输出，以及负输入输出耦合到第一差分跨导体的正输入。每个差分跨导体都具有负输出阻抗。每个差分跨导体包括电流控制跨导体电路（CCXG）和耦合到第一电源节点的电压 - 电流转换器，用于响应于施加到差分跨导体的电压控制输入的电压向CCXG提供电流。

29. 发明授权

US5635879A Voltage controlled oscillator formed of two differential transconductors 失效
标题翻译：由两个差动跨导器组成的压控振荡器
公开(公告)号：US5635879A
公开(公告)日：1997-06-03
申请号：US660006
申请日：1996-06-03
申请人： Pantas Sutardja , Sehat Sutardja
发明人： Pantas Sutardja , Sehat Sutardja
IPC分类号： H03K3/0231 , H03L7/089 , H03L7/099 , H03B5/00
CPC分类号： H03K3/0231 , H03L7/0895 , H03L7/0995
摘要： A monolithic CMOS phase-lock loop (PLL) circuit provides a high frequency of operation suitable for RF applications. The PLL produces an output clock with high spectral purity and very low jitter. The output clock has a low static phase error relative to a reference input, making the PLL also useful for clock synchronizing applications, such as clock recovery elements in transmission/recycling channels. The PLL provides in-phase and quadrature signals from a VCO which has two differential transconductor stages having negative output conductance.
摘要翻译：单片CMOS锁相环（PLL）电路提供适合RF应用的高频操作。 PLL产生具有高光谱纯度和非常低抖动的输出时钟。输出时钟相对于参考输入具有较低的静态相位误差，使得PLL也可用于时钟同步应用，如传输/再循环通道中的时钟恢复元件。 PLL提供来自VCO的同相和正交信号，该VCO具有负输出电导的两个差分跨导级。

30. 发明公开

US20240256222A1 HIGH SPEED RIPPLE ADDER 审中-公开
公开(公告)号：US20240256222A1
公开(公告)日：2024-08-01
申请号：US18423214
申请日：2024-01-25
申请人： Sehat Sutardja
发明人： Sehat Sutardja
IPC分类号： G06F7/506 , H03K19/00
CPC分类号： G06F7/506 , H03K19/00
摘要： Apparatus and method to logically process signals representative of multiple-bit numbers include successively delaying applications of the bit-representative signals to logical processing stages from associated input registers by a delay interval between input registers that is substantially equal to the processing delay interval per bit-level of the logical processing stage. In this way, successively more significant bits of each of plural numbers being logically processed are validly available for processing at each bit-level logic stage after a delay. At least one of the bit-representative signals is inverted prior to the input registers or prior to processing by the logical processing stage. The delay is reduced by omitting an inverting function in a carry circuit associated with at least one logical processing stage. Similarly, output registers for latching the logic output of each bit-level logic stage are clocked at successively delayed intervals substantially equal to the processing delay interval.

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