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21. 发明申请

US20050042882A1 Method of etching metallic thin film on thin film resistor 有权
标题翻译：在薄膜电阻上蚀刻金属薄膜的方法
公开(公告)号：US20050042882A1
公开(公告)日：2005-02-24
申请号：US10944665
申请日：2004-09-17
申请人： Ichiro Ito , Satoshi Shiraki
发明人： Ichiro Ito , Satoshi Shiraki
IPC分类号： H01L21/02 , H01L21/3213 , H01L21/302 , H01L21/461
CPC分类号： H01L28/24 , H01L21/32139
摘要： An Al film is formed on a barrier metal covering a thin film resistor to have a first opening. A photo-resist is formed on the Al film and in the opening, and is patterned to have a second opening having an opening area smaller than that of the first opening and open in the first opening to expose the barrier metal therefrom. Then, the barrier metal is etched through the second opening. Because the barrier metal is etched from an inner portion more than the opening end of the first opening, under-cut of the barrier metal is prevented.
摘要翻译：在覆盖薄膜电阻器的阻挡金属上形成具有第一开口的Al膜。在Al膜和开口中形成光致抗蚀剂，并且被图案化以具有开口面积小于第一开口的开口面积并在第一开口中开口的第二开口，以暴露出阻挡金属。然后，通过第二开口蚀刻阻挡金属。由于阻挡金属从第一开口的开口端的内部蚀刻，因此防止了阻挡金属的切割。

22. 发明授权

US06274452B1 Semiconductor device having multilayer interconnection structure and method for manufacturing the same 失效
标题翻译：具有多层互连结构的半导体装置及其制造方法
公开(公告)号：US06274452B1
公开(公告)日：2001-08-14
申请号：US08965030
申请日：1997-11-05
申请人： Shoji Miura , Satoshi Shiraki , Hajime Soga
发明人： Shoji Miura , Satoshi Shiraki , Hajime Soga
IPC分类号： H01L2120
CPC分类号： H01L28/20 , H01L21/84 , H01L27/13 , H01L2924/0002 , H01L2924/00
摘要： After an insulating layer made of BPSG is formed on a diffusion layer, a contact hole is formed to expose the diffusion layer. Then, a first aluminum layer is formed in the contact hole. Then, first and second TEOS layers are formed. Thereafter, a thin film resistor is formed on the second TEOS layer by photo-lithography and etching treatments. In this process, the other parts are covered with the second TEOS layer to prevent being damaged. As a result, occurrence of a leak current at the diffusion layer and the like can be prevented. Further, a third TEOS layer is formed on the thin film resistor, and then a second aluminum layer is formed to be electrically connected to the thin film resistor through a contact hole by an ECR dry etching treatment. In this etching treatment, the thin film resistor is not damaged due to the third TEOS layer.
摘要翻译：在扩散层上形成由BPSG制成的绝缘层之后，形成接触孔以露出扩散层。然后，在接触孔中形成第一铝层。然后，形成第一和第二TEOS层。此后，通过光刻和蚀刻处理在第二TEOS层上形成薄膜电阻器。在此过程中，其他部分被第二个TEOS层覆盖，以防止损坏。结果，可以防止在扩散层等处发生泄漏电流。此外，在薄膜电阻器上形成第三TEOS层，然后通过ECR干蚀刻处理通过接触孔形成第二铝层与薄膜电阻器电连接。在这种蚀刻处理中，由于第三TEOS层，薄膜电阻器不会被损坏。

23. 发明授权

US08102047B2 Load driving device 有权
标题翻译：负载驱动装置
公开(公告)号：US08102047B2
公开(公告)日：2012-01-24
申请号：US12801187
申请日：2010-05-27
申请人： Satoshi Shiraki , Akira Yamada , Hiroyuki Ban
发明人： Satoshi Shiraki , Akira Yamada , Hiroyuki Ban
IPC分类号： H01L23/34 , H01L23/10
CPC分类号： H05K7/1432 , H01L24/73 , H01L2224/32145 , H01L2224/32245 , H01L2224/33181 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/73215 , H01L2224/73265 , H01L2924/01046 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H02M7/003 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A load driving device includes: an output power device for driving a load; a driving IC for controlling the output power device, wherein the driving IC is electrically coupled with the output power device through a wire or a connection member; and a first electrode substrate. The output power device and the driving IC are mounted on the first electrode substrate. In this case, the output power device is controlled with high speed, and a mounting area of the output power device and the driving IC is reduced.
摘要翻译：负载驱动装置包括：用于驱动负载的输出功率装置; 用于控制输出功率器件的驱动IC，其中驱动IC通过导线或连接构件与输出功率器件电耦合; 和第一电极基板。输出功率器件和驱动IC安装在第一电极基板上。在这种情况下，输出功率器件被高速控制，并且输出功率器件和驱动IC的安装面积减小。

24. 发明授权

US07799667B2 Method for manufacturing semiconductor device with planer gate electrode and trench gate electrode 有权
标题翻译：制造具有平面栅电极和沟槽栅电极的半导体器件的方法
公开(公告)号：US07799667B2
公开(公告)日：2010-09-21
申请号：US12219008
申请日：2008-07-15
申请人： Satoshi Shiraki , Yoshiaki Nakayama , Shoji Mizuno , Takashi Nakano , Akira Yamada
发明人： Satoshi Shiraki , Yoshiaki Nakayama , Shoji Mizuno , Takashi Nakano , Akira Yamada
IPC分类号： H01L21/336
CPC分类号： H01L29/7824 , H01L21/26586 , H01L21/76286 , H01L21/763 , H01L21/823418 , H01L21/823456 , H01L21/823462 , H01L21/823481 , H01L29/0696 , H01L29/1041 , H01L29/105 , H01L29/1095 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/66681 , H01L29/66795 , H01L29/7825 , H01L29/7831 , H01L29/7835
摘要： A semiconductor device includes: a semiconductor substrate with a principal plane; a base region disposed on the principal plane; a source region disposed on the principal plane in the base region to be shallower than the base region; a drain region disposed on the principal plane, and spaced to the base region; a trench disposed on the principal plane; a trench gate electrode disposed in the trench through a trench gate insulation film; a planer gate electrode disposed on the principal plane of the semiconductor substrate through a planer gate insulation film; and an impurity diffusion region having high concentration of impurities and disposed in a portion of the base region to be a channel region facing the planer gate electrode.
摘要翻译：半导体器件包括：具有主平面的半导体衬底; 设置在主平面上的基部区域; 源区域，其设置在所述基底区域中的所述主平面上，以比所述基底区域浅; 漏极区域，设置在所述主平面上，并且与所述基极区域间隔开; 设在主平面上的沟槽; 通过沟槽栅极绝缘膜设置在沟槽中的沟槽栅电极; 通过平面栅极绝缘膜设置在半导体衬底的主平面上的平面栅电极; 以及杂质扩散区域，其具有高浓度的杂质，并且设置在基极区域的一部分中，作为面向平面栅电极的沟道区域。

25. 发明授权

US07755187B2 Load driving device 有权
公开(公告)号：US07755187B2
公开(公告)日：2010-07-13
申请号：US11806467
申请日：2007-05-31
申请人： Satoshi Shiraki , Akira Yamada , Hiroyuki Ban
发明人： Satoshi Shiraki , Akira Yamada , Hiroyuki Ban
IPC分类号： H01L23/34 , H01L23/495
CPC分类号： H05K7/1432 , H01L24/73 , H01L2224/32145 , H01L2224/32245 , H01L2224/33181 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/73215 , H01L2224/73265 , H01L2924/01046 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H02M7/003 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A load driving device includes: an output power device for driving a load; a driving IC for controlling the output power device, wherein the driving IC is electrically coupled with the output power device through a wire or a connection member; and a first electrode substrate. The output power device and the driving IC are mounted on the first electrode substrate. In this case, the output power device is controlled with high speed, and a mounting area of the output power device and the driving IC is reduced.

26. 发明申请

US20080231340A1 Level shift circuit 有权
标题翻译：电平移位电路
公开(公告)号：US20080231340A1
公开(公告)日：2008-09-25
申请号：US12076521
申请日：2008-03-19
申请人： Satoshi Shiraki , Hiroyuki Ban , Junichi Nagata
发明人： Satoshi Shiraki , Hiroyuki Ban , Junichi Nagata
IPC分类号： H03L5/00
CPC分类号： H03K19/018571 , H01L27/0251 , H03K5/003 , H03K19/00361
摘要： A level shift circuit includes a first capacitor circuit including capacitors connected in series between a ground and a predetermined potential, a first trigger circuit coupled to the predetermined potential side of the first capacitor circuit, an input terminal coupled to the ground side of the first capacitor circuit, a second capacitor circuit including capacitors connected in series between the ground and the predetermined potential, a second trigger circuit coupled to the predetermined potential side of the second capacitor circuit, an inverter coupled between the input terminal and the ground potential side of the second capacitor circuit, and a SR latch circuit having a first input coupled to an output of the first trigger circuit and a second input coupled to an output of the second trigger circuit.
摘要翻译：电平移位电路包括：第一电容器电路，包括串联连接在接地和预定电位之间的电容器;耦合到第一电容器电路的预定电位侧的第一触发电路;耦合到第一电容器的接地侧的输入端子电路，包括串联连接在接地和预定电位之间的电容器的第二电容器电路，耦合到第二电容器电路的预定电位侧的第二触发电路，耦合在第二电容器的输入端子和地电位侧之间的反相器电容器电路和SR锁存电路，其具有耦合到第一触发电路的输出的第一输入和耦合到第二触发电路的输出的第二输入。

27. 发明授权

US06809034B2 Method of etching metallic thin film on thin film resistor 失效
公开(公告)号：US06809034B2
公开(公告)日：2004-10-26
申请号：US10131683
申请日：2002-04-24
申请人： Ichiro Ito , Satoshi Shiraki , Tomio Yamamoto , Makoto Ohkawa , Atsumi Takahashi , Yasuaki Tsuzuki , Akito Fukui , Toshio Sakakibara , Takayuki Sugisaka
发明人： Ichiro Ito , Satoshi Shiraki , Tomio Yamamoto , Makoto Ohkawa , Atsumi Takahashi , Yasuaki Tsuzuki , Akito Fukui , Toshio Sakakibara , Takayuki Sugisaka
IPC分类号： H01L21302
CPC分类号： H01L28/24 , H01L21/32139
摘要： An Al film is formed on a barrier metal covering a thin film resistor to have a first opening. A photo-resist is formed on the Al film and in the opening, and is patterned to have a second opening having an opening area smaller than that of the first opening and open in the first opening to expose the barrier metal therefrom. Then, the barrier metal is etched through the second opening. Because the barrier metal is etched from an inner portion more than the opening end of the first opening, under-cut of the barrier metal is prevented.

28. 发明授权

US07639060B2 Level shift circuit 有权
标题翻译：电平移位电路
公开(公告)号：US07639060B2
公开(公告)日：2009-12-29
申请号：US12076521
申请日：2008-03-19
申请人： Satoshi Shiraki , Hiroyuki Ban , Junichi Nagata
发明人： Satoshi Shiraki , Hiroyuki Ban , Junichi Nagata
IPC分类号： H03L5/00
CPC分类号： H03K19/018571 , H01L27/0251 , H03K5/003 , H03K19/00361
摘要： A level shift circuit includes a first capacitor circuit including capacitors connected in series between a ground and a predetermined potential, a first trigger circuit coupled to the predetermined potential side of the first capacitor circuit, an input terminal coupled to the ground side of the first capacitor circuit, a second capacitor circuit including capacitors connected in series between the ground and the predetermined potential, a second trigger circuit coupled to the predetermined potential side of the second capacitor circuit, an inverter coupled between the input terminal and the ground potential side of the second capacitor circuit, and a SR latch circuit having a first input coupled to an output of the first trigger circuit and a second input coupled to an output of the second trigger circuit.
摘要翻译：电平移位电路包括：第一电容器电路，包括串联连接在接地和预定电位之间的电容器;耦合到第一电容器电路的预定电位侧的第一触发电路;耦合到第一电容器的接地侧的输入端子电路，包括串联连接在接地和预定电位之间的电容器的第二电容器电路，耦合到第二电容器电路的预定电位侧的第二触发电路，耦合在第二电容器的输入端子和地电位侧之间的反相器电容器电路和SR锁存电路，其具有耦合到第一触发电路的输出的第一输入和耦合到第二触发电路的输出的第二输入。

29. 发明申请

US20080007920A1 Loading driving device 有权
标题翻译：装载驱动装置
公开(公告)号：US20080007920A1
公开(公告)日：2008-01-10
申请号：US11806467
申请日：2007-05-31
申请人： Satoshi Shiraki , Akira Yamada , Hiroyuki Ban
发明人： Satoshi Shiraki , Akira Yamada , Hiroyuki Ban
IPC分类号： H02M7/537 , H05K7/20
CPC分类号： H05K7/1432 , H01L24/73 , H01L2224/32145 , H01L2224/32245 , H01L2224/33181 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/73215 , H01L2224/73265 , H01L2924/01046 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H02M7/003 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A load driving device includes: an output power device for driving a load; a driving IC for controlling the output power device, wherein the driving IC is electrically coupled with the output power device through a wire or a connection member; and a first electrode substrate. The output power device and the driving IC are mounted on the first electrode substrate. In this case, the output power device is controlled with high speed, and a mounting area of the output power device and the driving IC is reduced.
摘要翻译：负载驱动装置包括：用于驱动负载的输出功率装置; 用于控制输出功率器件的驱动IC，其中驱动IC通过导线或连接构件与输出功率器件电耦合; 和第一电极基板。输出功率器件和驱动IC安装在第一电极基板上。在这种情况下，输出功率器件被高速控制，并且输出功率器件和驱动IC的安装面积减小。

30. 发明授权

US07109558B2 Power MOS transistor having capability for setting substrate potential independently of source potential 有权
公开(公告)号：US07109558B2
公开(公告)日：2006-09-19
申请号：US10160098
申请日：2002-06-04
申请人： Takashi Nakano , Satoshi Shiraki , Yutaka Fukuda , Nobumasa Ueda , Shoji Miura
发明人： Takashi Nakano , Satoshi Shiraki , Yutaka Fukuda , Nobumasa Ueda , Shoji Miura
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7811 , H01L23/4824 , H01L29/0696 , H01L29/0847 , H01L29/1087 , H01L29/1095 , H01L29/7802 , H01L29/7816 , H01L29/7835 , Y10S257/901
摘要： A power MOS transistor formed of an array of source cells and drain cells on an IC chip substrate has a plurality of substrate contact cells, each formed external to the source cells, having respective substrate potential-setting electrodes to which an externally supplied substrate bias voltage can be applied, enabling the substrate potential to be set independently of the source potential of the transistor. It thereby becomes possible to modify the threshold voltage of the transistor or maintain a constant potential difference between the substrate potential and that of a gate input signal. Since the requirement for a substrate contact region within each source cell is eliminated, and the number of substrate contact cells can be fewer than that of the source cells, the chip area occupied by the transistor can be reduced by comparison with a prior art configuration providing such a substrate potential control capability.

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