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21. 发明申请

US20160350088A1 FUSING A SEQUENCE OF OPERATIONS THROUGH SUBDIVIDING 审中-公开
标题翻译：通过分解来完成操作的顺序
公开(公告)号：US20160350088A1
公开(公告)日：2016-12-01
申请号：US14723141
申请日：2015-05-27
申请人： Nvidia Corporation
发明人： Mahesh Ravishankar , Paulius Micikevicius , Vinod Grover
IPC分类号： G06F9/45
CPC分类号： G06F8/4434 , G06F8/41 , G06F8/45
摘要： A compiler and a method of compiling code that reduces memory bandwidth when processing code on a computer are provided herein. In one embodiment, the method includes: (1) automatically identifying a sequence of operations for fusing, wherein the sequence of operations correspond to instructions from a source code, (2) determining subdivisions of a final output of the sequence of operations, (3) determining input data and intermediate operations needed to obtain a final subdivision output for each of the subdivisions and (4) automatically generating code to fuse the sequence of operations employing the subdivisions, wherein the automatically identifying and the automatically generating are performed by a processor.
摘要翻译：本文提供了一种编译器和编译在计算机上处理代码时减少内存带宽的代码的方法。在一个实施例中，该方法包括：（1）自动识别用于融合的操作序列，其中所述操作序列对应于源代码的指令，（2）确定所述操作序列的最终输出的细分，（3 ）确定为每个子部分获得最终细分输出所需的输入数据和中间操作，以及（4）自动生成代码以融合采用该细分的操作序列，其中自动识别和自动生成由处理器执行。

22. 发明授权

US09038080B2 Method and system for heterogeneous filtering framework for shared memory data access hazard reports 有权
标题翻译：用于共享内存数据访问危害报告的异构过滤框架的方法和系统
公开(公告)号：US09038080B2
公开(公告)日：2015-05-19
申请号：US13728968
申请日：2012-12-27
申请人： NVIDIA Corporation
发明人： Vyas Venkataraman , Manjunath Kudlur , Vinod Grover
IPC分类号： G06F9/46 , G06F3/06 , G06F9/48 , G06F11/07
CPC分类号： G06F3/0653 , G06F9/4881 , G06F9/4887 , G06F11/0715 , G06F11/0751
摘要： A system and method for detecting, filtering, prioritizing and reporting shared memory hazards are disclosed. The method includes, for a unit of hardware operating on a block of threads, mapping a plurality of shared memory locations assigned to the unit to a tracking table. The tracking table comprises initialization information for each shared memory location. The method also includes, for an instruction of a program within a barrier region, identifying a potential conflict by identifying a second access to a location in shared memory within a block of threads executed by the hardware unit. First information associated with a first access and second information associated with the second access to the location is determined. Filter criteria is applied to the first and second information to determine whether the instruction causes a reportable hazard. The instruction is reported when it causes the reportable hazard.
摘要翻译：公开了一种用于检测，过滤，优先排序和报告共享内存危害的系统和方法。该方法包括对于在线程块上操作的硬件单元，将分配给该单元的多个共享存储器位置映射到跟踪表。跟踪表包括每个共享存储器位置的初始化信息。该方法还包括对于屏障区域内的程序的指令，通过识别由硬件单元执行的线程块内的共享存储器中的位置的第二访问来识别潜在的冲突。确定与第一访问相关联的第一信息和与对该位置的第二访问相关联的第二信息。过滤标准被应用于第一和第二信息以确定该指令是否导致可报告的危险。当导致可报告的危险时，报告该指令。

23. 发明申请

US20140164727A1 SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR OPTIMIZING THE MANAGEMENT OF THREAD STACK MEMORY 有权
标题翻译：系统，方法和计算机程序产品，用于优化螺纹堆叠存储器的管理
公开(公告)号：US20140164727A1
公开(公告)日：2014-06-12
申请号：US13712897
申请日：2012-12-12
申请人： NVIDIA CORPORATION
发明人： Adriana Maria Susnea , Vinod Grover , Sean Youngsung Lee
IPC分类号： G06F12/02
CPC分类号： G06F12/023 , G06F8/434 , G06F8/443
摘要： A system, method, and computer program product for optimizing thread stack memory allocation is disclosed. The method includes the steps of receiving source code for a program, translating the source code into an intermediate representation, analyzing the intermediate representation to identify at least two objects that could use a first allocated memory space in a thread stack memory, and modifying the intermediate representation by replacing references to a first object of the at least two objects with a reference to a second object of the at least two objects.
摘要翻译：公开了一种用于优化线程栈内存分配的系统，方法和计算机程序产品。该方法包括以下步骤：接收程序的源代码，将源代码转换为中间表示，分析中间表示以识别可在线程堆栈存储器中使用第一分配的存储器空间的至少两个对象，以及修改中间代码通过对所述至少两个对象的第二对象的引用来替换对所述至少两个对象的第一对象的引用的表示。

24. 发明申请

US20130304996A1 METHOD AND SYSTEM FOR RUN TIME DETECTION OF SHARED MEMORY DATA ACCESS HAZARDS 审中-公开
标题翻译：用于运行时间检测共享存储器数据访问危险的方法和系统
公开(公告)号：US20130304996A1
公开(公告)日：2013-11-14
申请号：US13728990
申请日：2012-12-27
申请人： NVIDIA CORPORATION
发明人： Vyas Venkataraman , Jaydeep Marathe , Manjunath Kudlur , Vinod Grover , Geoffrey Gerfin , Alban Douillet , Mayank Kaushik
IPC分类号： G06F3/06
CPC分类号： G06F3/067 , G06F11/0715 , G06F11/073 , G06F11/0751
摘要： A system and method for detecting shared memory hazards are disclosed. The method includes, for a unit of hardware operating on a block of threads, mapping a plurality of shared memory locations assigned to the unit to a tracking table. The tracking table comprises an initialization bit as well as access type information, collectively called the state tracking bits for each shared memory location. The method also includes, for an instruction of a program within a barrier region, identifying a second access to a location in shared memory within a block of threads executed by the hardware unit. The second access is identified based on a status of the state tracking bits. The method also includes determining a hazard based on a first type of access and a second type of access to the shared memory location. Information related to the first access is provided in the table.
摘要翻译：公开了一种用于检测共享内存危害的系统和方法。该方法包括对于在线程块上操作的硬件单元，将分配给该单元的多个共享存储器位置映射到跟踪表。跟踪表包括初始化位以及访问类型信息，统称为用于每个共享存储器位置的状态跟踪位。该方法还包括对于屏障区域内的程序的指令，识别由硬件单元执行的线程块内的共享存储器中的位置的第二访问。基于状态跟踪位的状态来识别第二访问。该方法还包括基于第一类型的访问确定危险，以及对共享存储器位置进行第二类型的访问。与第一次访问相关的信息在表中提供。

25. 发明授权

US11630653B2 Execution of computation graphs 有权
公开(公告)号：US11630653B2
公开(公告)日：2023-04-18
申请号：US15872663
申请日：2018-01-16
申请人： NVIDIA CORPORATION
发明人： Mahesh Ravishankar , Vinod Grover , Evghenii Gaburov , Alberto Magni , Sean Lee
IPC分类号： G06F8/41 , G06F9/455 , G06N20/00
摘要： A computation graph is accessed. In the computation graph, operations to be performed are represented as interior nodes, inputs to the operations are represented as leaf nodes, and a result of the operations is represented as a root. Selected sets of the operations are combined to form respective kernels of operations. Code is generated execute the kernels of operations. The code is executed to determine the result.

26. 发明申请

US20230051050A1 NEURAL NETWORK LOOP DETECTION 有权
公开(公告)号：US20230051050A1
公开(公告)日：2023-02-16
申请号：US17393246
申请日：2021-08-03
申请人： NVIDIA Corporation
发明人： Vinod Grover , Sean Youngsung Lee
IPC分类号： G06N3/08
摘要： Apparatuses, systems, and techniques to detect loops in neural network graphs. In at least one embodiment, one or more loops are detected within one or more graphs corresponding to one or more neural networks.

27. 发明授权

US11579852B2 Device profiling in GPU accelerators by using host-device coordination 有权
公开(公告)号：US11579852B2
公开(公告)日：2023-02-14
申请号：US16939313
申请日：2020-07-27
申请人： NVIDIA Corporation
发明人： Hariharan Sandanagobalane , Sean Lee , Vinod Grover
IPC分类号： G06F8/41 , G06F11/36 , G06F16/903 , G06F16/901 , G06F9/445
摘要： System and method of compiling a program having a mixture of host code and device code to enable Profile Guided Optimization (PGO) for device code execution. An exemplary integrated compiler can compile source code programmed to be executed by a host processor (e.g., CPU) and a co-processor (e.g., a GPU) concurrently. The compilation can generate an instrumented executable code which includes: profile instrumentation counters for the device functions; and instructions for the host processor to allocate and initialize device memory for the counters and to retrieve collected profile information from the device memory to generate instrumentation output. The output is fed back to the compiler for compiling the source code a second time to generate optimized executable code for the device functions defined in the source code.

28. 发明申请

US20230025245A1 NEURAL NETWORK EVALUATION 有权
公开(公告)号：US20230025245A1
公开(公告)日：2023-01-26
申请号：US17374664
申请日：2021-07-13
申请人： NVIDIA Corporation
发明人： Vinod Grover , Mahesh Ravishankar , Bin Fan , Alexander James Collins , Se Jong Oh , Evghenii Gaburov
IPC分类号： G06N3/08
摘要： Apparatuses, systems, and techniques to modify performance of a neural network. In at least one embodiment, performance of one or more neural networks is modified based, at least in part, on a user-provided description of at least portions of the one or more neural networks.

29. 发明授权

US10853044B2 Device profiling in GPU accelerators by using host-device coordination 有权
公开(公告)号：US10853044B2
公开(公告)日：2020-12-01
申请号：US16154560
申请日：2018-10-08
申请人： Nvidia Corporation
发明人： Hariharan Sandanagobalane , Sean Lee , Vinod Grover
IPC分类号： G06F8/41 , G06F11/36 , G06F16/903 , G06F16/901 , G06F9/445
摘要： System and method of compiling a program having a mixture of host code and device code to enable Profile Guided Optimization (PGO) for device code execution. An exemplary integrated compiler can compile source code programmed to be executed by a host processor (e.g., CPU) and a co-processor (e.g., a GPU) concurrently. The compilation can generate an instrumented executable code which includes: profile instrumentation counters for the device functions; and instructions for the host processor to allocate and initialize device memory for the counters and to retrieve collected profile information from the device memory to generate instrumentation output. The output is fed back to the compiler for compiling the source code a second time to generate optimized executable code for the device functions defined in the source code.

30. 发明申请

US20190146766A1 DEVICE PROFILING IN GPU ACCELERATORS BY USING HOST-DEVICE 审中-公开
公开(公告)号：US20190146766A1
公开(公告)日：2019-05-16
申请号：US16154560
申请日：2018-10-08
申请人： Nvidia Corporation
发明人： Hariharan Sandanagobalane , Sean Lee , Vinod Grover
IPC分类号： G06F8/41 , G06F16/901 , G06F16/903
摘要： System and method of compiling a program having a mixture of host code and device code to enable Profile Guided Optimization (PGO) for device code execution. An exemplary integrated compiler can compile source code programmed to be executed by a host processor (e.g., CPU) and a co-processor (e.g., a GPU) concurrently. The compilation can generate an instrumented executable code which includes: profile instrumentation counters for the device functions; and instructions for the host processor to allocate and initialize device memory for the counters and to retrieve collected profile information from the device memory to generate instrumentation output. The output is fed back to the compiler for compiling the source code a second time to generate optimized executable code for the device functions defined in the source code.

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