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1. 发明申请

US20160350088A1 FUSING A SEQUENCE OF OPERATIONS THROUGH SUBDIVIDING 审中-公开
标题翻译：通过分解来完成操作的顺序
公开(公告)号：US20160350088A1
公开(公告)日：2016-12-01
申请号：US14723141
申请日：2015-05-27
申请人： Nvidia Corporation
发明人： Mahesh Ravishankar , Paulius Micikevicius , Vinod Grover
IPC分类号： G06F9/45
CPC分类号： G06F8/4434 , G06F8/41 , G06F8/45
摘要： A compiler and a method of compiling code that reduces memory bandwidth when processing code on a computer are provided herein. In one embodiment, the method includes: (1) automatically identifying a sequence of operations for fusing, wherein the sequence of operations correspond to instructions from a source code, (2) determining subdivisions of a final output of the sequence of operations, (3) determining input data and intermediate operations needed to obtain a final subdivision output for each of the subdivisions and (4) automatically generating code to fuse the sequence of operations employing the subdivisions, wherein the automatically identifying and the automatically generating are performed by a processor.
摘要翻译：本文提供了一种编译器和编译在计算机上处理代码时减少内存带宽的代码的方法。在一个实施例中，该方法包括：（1）自动识别用于融合的操作序列，其中所述操作序列对应于源代码的指令，（2）确定所述操作序列的最终输出的细分，（3 ）确定为每个子部分获得最终细分输出所需的输入数据和中间操作，以及（4）自动生成代码以融合采用该细分的操作序列，其中自动识别和自动生成由处理器执行。

2. 发明授权

US09563933B2 Methods for reducing memory space in sequential operations using directed acyclic graphs 有权
标题翻译：使用有向非循环图在顺序操作中减少内存空间的方法
公开(公告)号：US09563933B2
公开(公告)日：2017-02-07
申请号：US14165789
申请日：2014-01-28
申请人： Nvidia Corporation
发明人： Vinod Grover , Mahesh Ravishankar
IPC分类号： G06T1/60 , G06F9/44 , G06F9/45
CPC分类号： G06T1/60 , G06F8/34 , G06F8/4434
摘要： Various disclosed embodiments are directed to methods and systems for reducing memory space in sequential computer-implemented operations. The method includes generating a directed acyclic graph (DAG) having a plurality of vertices and directed edges, wherein each edge connects a predecessor vertex to a successor vertex. Each vertex represents one of the computer-implemented operations and each directed edge represents output data generated by the operations. The method includes merging one of the predecessor vertex with one of the successor vertex by combining the operations of the predecessor vertex and the successor vertex if the predecessor and successor vertices are connected by a directed edge and there is only one directed edge originating from the predecessor vertex. The merger of the predecessor and the successor vertices reduces the number of directed edges in the DAG, resulting in a reduction of intermediate buffer memory required to store the output data.
摘要翻译：各种公开的实施例涉及用于在顺序的计算机实现的操作中减少存储空间的方法和系统。该方法包括生成具有多个顶点和定向边缘的有向非循环图（DAG），其中每个边缘将前导顶点连接到后继顶点。每个顶点表示计算机实现的操作之一，每个有向边代表由操作产生的输出数据。该方法包括通过将前导顶点和后继顶点的操作通过组合前导顶点和后继顶点的操作通过有向边连接并且仅有一个源自前导的有向边的方式将前导顶点之一与后继顶点之一合并顶点。前导和后继顶点的合并减少了DAG中的有向边的数量，导致存储输出数据所需的中间缓冲存储器的减少。

3. 发明公开

US20230251861A1 ACCELERATING LINEAR ALGEBRA KERNELS FOR ANY PROCESSOR ARCHITECTURE 审中-公开
公开(公告)号：US20230251861A1
公开(公告)日：2023-08-10
申请号：US18136233
申请日：2023-04-18
申请人： NVIDIA Corporation
发明人： Venmugil Elango , Norman Rubin , Mahesh Ravishankar , Vinod Grover
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F9/30065 , G06T1/20
摘要： Systems and methods for obtaining a set of instructions for executing a computer program and generating executable code for the computer program based, at least in part, on scheduling operations associated with the executable code according to a polyhedral representation of a directed acyclic graph. The set of instructions may be represented as a domain-specific language. The executable code may be executable code for a specific processor architecture.

4. 发明申请

US20150212933A1 METHODS FOR REDUCING MEMORY SPACE IN SEQUENTIAL OPERATIONS USING DIRECTED ACYCLIC GRAPHS 有权
标题翻译：使用方向图的顺序操作减少记忆空间的方法
公开(公告)号：US20150212933A1
公开(公告)日：2015-07-30
申请号：US14165789
申请日：2014-01-28
申请人： Nvidia Corporation
发明人： Vinod Grover , Mahesh Ravishankar
IPC分类号： G06F12/02 , G06T1/60
CPC分类号： G06T1/60 , G06F8/34 , G06F8/4434
摘要： Various disclosed embodiments are directed to methods and systems for reducing memory space in sequential computer-implemented operations. The method includes generating a directed acyclic graph (DAG) having a plurality of vertices and directed edges, wherein each edge connects a predecessor vertex to a successor vertex. Each vertex represents one of the computer-implemented operations and each directed edge represents output data generated by the operations. The method includes merging one of the predecessor vertex with one of the successor vertex by combining the operations of the predecessor vertex and the successor vertex if the predecessor and successor vertices are connected by a directed edge and there is only one directed edge originating from the predecessor vertex. The merger of the predecessor and the successor vertices reduces the number of directed edges in the DAG, resulting in a reduction of intermediate buffer memory required to store the output data.
摘要翻译：各种公开的实施例涉及用于在顺序的计算机实现的操作中减少存储空间的方法和系统。该方法包括生成具有多个顶点和定向边缘的有向非循环图（DAG），其中每个边缘将前导顶点连接到后继顶点。每个顶点表示计算机实现的操作之一，每个有向边代表由操作产生的输出数据。该方法包括通过组合前导顶点和后继顶点的操作，将前导顶点之一与后继顶点之一合并，如果前导和后继顶点通过有向边连接，并且只有一个源自前导的有向边顶点。前导和后继顶点的合并减少了DAG中的有向边的数量，导致存储输出数据所需的中间缓冲存储器的减少。

5. 发明授权

US11630653B2 Execution of computation graphs 有权
公开(公告)号：US11630653B2
公开(公告)日：2023-04-18
申请号：US15872663
申请日：2018-01-16
申请人： NVIDIA CORPORATION
发明人： Mahesh Ravishankar , Vinod Grover , Evghenii Gaburov , Alberto Magni , Sean Lee
IPC分类号： G06F8/41 , G06F9/455 , G06N20/00
摘要： A computation graph is accessed. In the computation graph, operations to be performed are represented as interior nodes, inputs to the operations are represented as leaf nodes, and a result of the operations is represented as a root. Selected sets of the operations are combined to form respective kernels of operations. Code is generated execute the kernels of operations. The code is executed to determine the result.

6. 发明申请

US20230025245A1 NEURAL NETWORK EVALUATION 有权
公开(公告)号：US20230025245A1
公开(公告)日：2023-01-26
申请号：US17374664
申请日：2021-07-13
申请人： NVIDIA Corporation
发明人： Vinod Grover , Mahesh Ravishankar , Bin Fan , Alexander James Collins , Se Jong Oh , Evghenii Gaburov
IPC分类号： G06N3/08
摘要： Apparatuses, systems, and techniques to modify performance of a neural network. In at least one embodiment, performance of one or more neural networks is modified based, at least in part, on a user-provided description of at least portions of the one or more neural networks.

7. 发明申请

US20190278593A1 ACCELERATING LINEAR ALGEBRA KERNELS FOR ANY PROCESSOR ARCHITECTURE 审中-公开
公开(公告)号：US20190278593A1
公开(公告)日：2019-09-12
申请号：US16277661
申请日：2019-02-15
申请人： NVIDIA Corporation
发明人： Venmugil Elango , Norman Rubin , Mahesh Ravishankar , Vinod K. Grover
IPC分类号： G06F9/30
摘要： Systems and methods for obtaining a set of instructions for executing a computer program and generating executable code for the computer program based, at least in part, on scheduling operations associated with the executable code according to a polyhedral representation of a directed acyclic graph. The set of instructions may be represented as a domain-specific language. The executable code may be executable code for a specific processor architecture.

8. 发明授权

US10152310B2 Fusing a sequence of operations through subdividing 有权
公开(公告)号：US10152310B2
公开(公告)日：2018-12-11
申请号：US14723141
申请日：2015-05-27
申请人： Nvidia Corporation
发明人： Mahesh Ravishankar , Paulius Micikevicius , Vinod Grover
IPC分类号： G06F9/45 , G06F8/41
摘要： A compiler and a method of compiling code that reduces memory bandwidth when processing code on a computer are provided herein. In one embodiment, the method includes: (1) automatically identifying a sequence of operations for fusing, wherein the sequence of operations correspond to instructions from a source code, (2) determining subdivisions of a final output of the sequence of operations, (3) determining input data and intermediate operations needed to obtain a final subdivision output for each of the subdivisions and (4) automatically generating code to fuse the sequence of operations employing the subdivisions, wherein the automatically identifying and the automatically generating are performed by a processor.

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