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21. 发明授权

US5909059A Semiconductor device having contact plug and method for manufacturing the same 失效
标题翻译：具有接触塞的半导体装置及其制造方法
公开(公告)号：US5909059A
公开(公告)日：1999-06-01
申请号：US984214
申请日：1997-12-03
申请人： Hiromitsu Hada , Toru Tatsumi , Naoki Kasai , Hidemitsu Mori
发明人： Hiromitsu Hada , Toru Tatsumi , Naoki Kasai , Hidemitsu Mori
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/336 , H01L21/768 , H01L21/8234 , H01L21/8242 , H01L23/485 , H01L23/52 , H01L27/088 , H01L27/108 , H01L29/08 , H01L29/45 , H01L29/78 , H01L29/04 , H01L23/48 , H01L29/40
CPC分类号： H01L27/10888 , H01L21/28512 , H01L21/28525 , H01L21/28562 , H01L21/76879 , H01L23/485 , H01L29/0847 , H01L29/456 , H01L29/66477 , H01L29/66613 , H01L27/10814 , H01L27/10852 , H01L27/10873 , H01L2924/0002
摘要： On a main surface of a silicon substrate of one conductivity type, a diffusion layer of the opposite conductivity type is formed, and the main surface of the silicon substrate is covered by an insulator film. The insulator film is formed with a contact hole which extends to reach the diffusion layer of the opposite conductivity type. A contact plug is provided in the contact hole. The contact plug fills the contact hole and comprises a first silicon layer of the opposite conductivity type directly connected to the diffusion layer of the opposite conductivity type, a silicon-germanium alloy layer of the opposite conductivity type directly contact to the first silicon layer, and a second silicon layer of the opposite conductivity type directly contact to the silicon-germanium alloy layer. Wiring is provided on the surface of the insulator film in direct contact to the contact plug. As a result, increase in leakage at the junction of the diffusion layer is prevented by the low-resistance contact plug including the silicon-germanium alloy.
摘要翻译：在一种导电类型的硅衬底的主表面上，形成相反导电型的扩散层，并且硅衬底的主表面被绝缘体膜覆盖。绝缘膜形成有延伸到达相反导电类型的扩散层的接触孔。在接触孔中设置接触塞。接触塞填充接触孔，并且包括直接连接到相反导电类型的扩散层的相反导电类型的第一硅层，相反导电类型的硅 - 锗合金层直接接触第一硅层，以及相反导电类型的第二硅层直接接触硅 - 锗合金层。绝缘膜的表面设置有与接触插头直接接触的接线。结果，通过包括硅 - 锗合金的低电阻接触塞来防止扩散层的接合处的泄漏增加。

22. 发明授权

US08946668B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08946668B2
公开(公告)日：2015-02-03
申请号：US13574405
申请日：2011-01-21
申请人： Yukishige Saito , Kimihiko Ito , Hiromitsu Hada
发明人： Yukishige Saito , Kimihiko Ito , Hiromitsu Hada
IPC分类号： H01L29/02 , H01L47/00 , H01L23/522 , H01L45/00
CPC分类号： H01L23/5228 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/1675 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a semiconductor device including a resistive change element between a first wiring and a second wiring, which are arranged in a vertical direction so as to be adjacent to each other, with an interlayer insulation film being interposed on a semiconductor substrate. The resistive change element includes a lower electrode, a resistive change element film made of a metal oxide and an upper electrode. Since the upper electrode on the resistive change element film is formed as part of a plug for the second wiring, a structure in which a side surface of the upper electrode is not in direct contact with the side surface of the metal oxide or the lower electrode is provided so that it is possible to realize excellent device characteristics, even when a byproduct is adhered to the side wall of the metal oxide or the lower electrode in the etching thereof.
摘要翻译：公开了一种半导体器件，其包括在第一布线和第二布线之间的电阻变化元件，它们在垂直方向上彼此相邻地布置，层间绝缘膜插入在半导体衬底上。电阻变化元件包括下电极，由金属氧化物和上电极制成的电阻变化元件膜。由于电阻变化元件膜上的上电极被形成为用于第二布线的插头的一部分，所以上电极的侧表面不与金属氧化物或下电极的侧表面直接接触的结构即使在其蚀刻中副产物附着在金属氧化物或下电极的侧壁上时，也可以实现优异的器件特性。

23. 发明申请

US20120286231A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120286231A1
公开(公告)日：2012-11-15
申请号：US13574405
申请日：2011-01-21
申请人： Yukishige Saito , Kimihiko Ito , Hiromitsu Hada
发明人： Yukishige Saito , Kimihiko Ito , Hiromitsu Hada
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： H01L23/5228 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/1675 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a semiconductor device including a resistive change element between a first wiring and a second wiring, which are arranged in a vertical direction so as to be adjacent to each other, with an interlayer insulation film being interposed on a semiconductor substrate. The resistive change element includes a lower electrode, a resistive change element film made of a metal oxide and an upper electrode. Since the upper electrode on the resistive change element film is formed as part of a plug for the second wiring, a structure in which a side surface of the upper electrode is not in direct contact with the side surface of the metal oxide or the lower electrode is provided so that it is possible to realize excellent device characteristics, even when a byproduct is adhered to the side wall of the metal oxide or the lower electrode in the etching thereof.
摘要翻译：公开了一种半导体器件，其包括在第一布线和第二布线之间的电阻变化元件，它们在垂直方向上彼此相邻地布置，层间绝缘膜插入在半导体衬底上。电阻变化元件包括下电极，由金属氧化物和上电极制成的电阻变化元件膜。由于电阻变化元件膜上的上电极被形成为用于第二布线的插头的一部分，所以上电极的侧表面不与金属氧化物或下电极的侧表面直接接触的结构即使在其蚀刻中副产物附着在金属氧化物或下电极的侧壁上时，也可以实现优异的器件特性。

24. 发明授权

US5946570A Process for fabricating semiconductor device having semiconductor layers epitaxially grown from active areas without short-circuit on field insulating layer 失效
标题翻译：制造半导体器件的方法，该半导体器件具有从场绝缘层上没有短路的有源区域外延生长的半导体层
公开(公告)号：US5946570A
公开(公告)日：1999-08-31
申请号：US974996
申请日：1997-11-20
申请人： Naoki Kasai , Hiromitsu Hada , Hidemitsu Mori , Toru Tatsumi
发明人： Naoki Kasai , Hiromitsu Hada , Hidemitsu Mori , Toru Tatsumi
IPC分类号： H01L21/28 , H01L21/285 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L23/522 , H01L27/04 , H01L27/108
CPC分类号： H01L27/10852 , H01L2924/0002
摘要： A memory cell of a semiconductor dynamic random access memory device requires a bit line contact hole open to a drain region of a cell transistor for connecting a bit line to the drain region and a node contact hole open to a source region for connecting a storage electrode of a stacked capacitor to the source region, and the bit line contact hole and the node contact hole are plugged with silicon layers; the silicon layers are epitaxially grown from the source and drain regions over an oxide-encapsulated gate electrode of the cell transistor so as to increase the contact areas; and the silicon layers are firstly anisotropically grown until reaching the upper surface of the oxide-encapsulated gate electrode, and, thereafter, isotropically grown so as to increase the contact areas.
摘要翻译：半导体动态随机存取存储器件的存储单元需要对单元晶体管的漏极区域开放的位线接触孔，用于将位线连接到漏极区域，并且向源区域开放的节点接触孔用于连接存储电极的堆叠电容器到源极区域，并且位线接触孔和节点接触孔被硅层堵塞; 硅层从单元晶体管的氧化物封装的栅电极上的源极和漏极区域外延生长，以增加接触面积; 首先各向异性生长硅层，直到达到氧化物封装的栅电极的上表面，然后各向同性地生长以增加接触面积。

25. 发明授权

US5895948A Semiconductor device and fabrication process thereof 失效
标题翻译：半导体器件及其制造工艺
公开(公告)号：US5895948A
公开(公告)日：1999-04-20
申请号：US936919
申请日：1997-09-25
申请人： Hidemitsu Mori , Toru Tatsumi , Hiromitsu Hada , Naoki Kasai
发明人： Hidemitsu Mori , Toru Tatsumi , Hiromitsu Hada , Naoki Kasai
IPC分类号： H01L23/522 , H01L21/20 , H01L21/205 , H01L21/28 , H01L21/768 , H01L21/8234 , H01L21/8242 , H01L27/088 , H01L27/108 , H01L29/78 , H01L27/02 , H01L27/08
CPC分类号： H01L27/10852 , H01L21/02381 , H01L21/02433 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L27/10888 , H01L27/10811 , H01L27/10873
摘要： A silicon layer serving as a contact plug directly connected to a diffusion layer of a MOS transistor is provided. On a surface of an N.sup.- type diffusion layer in self-alignment with a silicon nitride layer spacer and a field oxide layer, an N.sup.+ type monocrystalline silicon layer formed by anisotropic selective epitaxial growth method is directly connected. The surface of the N.sup.+ type monocrystalline silicon layer is directly connected to an N.sup.+ type monocrystalline silicon layer formed by isotropic selective epitaxial growth.
摘要翻译：提供用作直接连接到MOS晶体管的扩散层的接触插塞的硅层。在与氮化硅层间隔物和场氧化物层自对准的N型扩散层的表面上，通过各向异性选择性外延生长法形成的N +型单晶硅层直接连接。 N +型单晶硅层的表面直接连接到通过各向同性选择性外延生长形成的N +型单晶硅层。

26. 发明授权

US5640097A Test pattern for separately determining plug resistance and interfactial resistance 失效
标题翻译：分别确定插头电阻和间隙电阻的测试模式
公开(公告)号：US5640097A
公开(公告)日：1997-06-17
申请号：US724350
申请日：1996-10-01
申请人： Hiromitsu Hada
发明人： Hiromitsu Hada
IPC分类号： H01L21/66 , G01R31/26 , G01R31/28 , H01L21/822 , H01L23/544 , H01L27/04 , G01R27/08
CPC分类号： H01L22/34 , G01R31/2648 , G01R31/2884 , H01L2924/0002
摘要： A test pattern for contact resistance, includes a contact hole section, and first to fourth electrode pad patterns connected to the contact hole section. The contact hole section includes first and second semiconductor region patterns apart from each other, first and second metal patterns provided above the first and second semiconductor region patterns via an insulating film apart from each other such that each of the first and second metal patterns overlaps the first and second semiconductor region patterns, first and second contact holes each having a plug structure, filled with a conductive material, and respectively provided to connect between the first semiconductor region pattern and the first and second metal patterns, the first and second contact holes having first and second depths, respectively, third and fourth contact holes each having the plug structure, filled with the conductive material, and respectively provided to connect between the second semiconductor region pattern and the first and second metal patterns, the third and fourth contact holes having the second and first depths, respectively, and fifth and sixth contact holes provided to connect between the first and second semiconductor regions patterns and the first and second electrode pad patterns, respectively, wherein the third and fourth electrode pad patterns are connected to the first and second metal patterns, respectively.
摘要翻译：接触电阻的测试图案包括接触孔部分和连接到接触孔部分的第一至第四电极焊盘图形。接触孔部分包括彼此分开的第一和第二半导体区域图案，第一和第二金属图案经由彼此分离的绝缘膜设置在第一和第二半导体区域图案之上，使得第一和第二金属图案中的每一个与第二和第二半导体区域图案重叠第一和第二半导体区域图案，每个具有插塞结构的第一和第二接触孔，填充有导电材料，并且分别设置成连接在第一半导体区域图案和第一和第二金属图案之间，第一和第二接触孔具有第一和第二深度分别具有插塞结构的第三和第四接触孔，填充有导电材料，并且分别设置成连接在第二半导体区域图案与第一和第二金属图案之间，第三和第四接触孔具有第二和第一深度分别为第五和第六种 ct孔分别连接在第一和第二半导体区域图案与第一和第二电极焊盘图案之间，其中第三和第四电极焊盘图案分别连接到第一和第二金属图案。

27. 发明授权

US06030894A Method for manufacturing a semiconductor device having contact plug made of Si/SiGe/Si 失效
标题翻译：制造具有由Si / SiGe / Si制成的接触塞的半导体器件的方法
公开(公告)号：US06030894A
公开(公告)日：2000-02-29
申请号：US119541
申请日：1998-07-20
申请人： Hiromitsu Hada , Toru Tatsumi , Naoki Kasai , Hidemitsu Mori
发明人： Hiromitsu Hada , Toru Tatsumi , Naoki Kasai , Hidemitsu Mori
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/336 , H01L21/768 , H01L21/8234 , H01L21/8242 , H01L23/485 , H01L23/52 , H01L27/088 , H01L27/108 , H01L29/08 , H01L29/45 , H01L29/78 , H01L21/4763 , H01L21/44 , H01L21/31
CPC分类号： H01L27/10888 , H01L21/28512 , H01L21/28525 , H01L21/28562 , H01L21/76879 , H01L23/485 , H01L29/0847 , H01L29/456 , H01L29/66477 , H01L29/66613 , H01L27/10814 , H01L27/10852 , H01L27/10873 , H01L2924/0002
摘要： On a main surface of a silicon substrate of one conductivity type, a diffusion layer of the opposite conductivity type is formed, and the main surface of the silicon substrate is covered by an insulator film. The insulator film is formed with a contact hole which extends to reach the diffusion layer of the opposite conductivity type. A contact plug is provided in the contact hole. The contact plug fills the contact hole and comprises a first silicon layer of the opposite conductivity type directly connected to the diffusion layer of the opposite conductivity type, a silicon-germanium alloy layer of the opposite conductivity type directly contact to the first silicon layer, and a second silicon layer of the opposite conductivity type directly contact to the silicon-germanium alloy layer. Wiring is provided on the surface of the insulator film in direct contact to the contact plug. As a result, increase in leakage at the junction of the diffusion layer is prevented by the low-resistance contact plug including the silicon-germanium alloy.
摘要翻译：在一种导电类型的硅衬底的主表面上，形成相反导电型的扩散层，并且硅衬底的主表面被绝缘体膜覆盖。绝缘膜形成有延伸到达相反导电类型的扩散层的接触孔。在接触孔中设置接触塞。接触塞填充接触孔，并且包括直接连接到相反导电类型的扩散层的相反导电类型的第一硅层，相反导电类型的硅 - 锗合金层直接接触第一硅层，以及相反导电类型的第二硅层直接接触硅 - 锗合金层。绝缘膜的表面设置有与接触插头直接接触的接线。结果，通过包括硅 - 锗合金的低电阻接触塞来防止扩散层的接合处的泄漏增加。

28. 发明授权

US5663651A Method of separately determining plug resistor and interfacial resistor and test pattern for the same 失效
标题翻译：分别确定插头电阻和界面电阻的方法以及测试图案
公开(公告)号：US5663651A
公开(公告)日：1997-09-02
申请号：US541160
申请日：1995-10-11
申请人： Hiromitsu Hada
发明人： Hiromitsu Hada
IPC分类号： H01L21/66 , G01R31/26 , G01R31/28 , H01L21/822 , H01L23/544 , H01L27/04 , G01R27/08
CPC分类号： H01L22/34 , G01R31/2648 , G01R31/2884 , H01L2924/0002
摘要： The present invention provides a test pattern and method for separately measuring a plug resistance and interfacial resistance of a contact resistance with high precision including the steps of: (a) providing on a semiconductor chip a test pattern as described above; (b) applying a predetermined voltage between the electrode pad patterns of one of a pair of first and second electrode pad patterns and a pair of third and fourth electrode pad patterns and measuring a current flowing between the electrode pad patterns of the one pair in an open state between the electrode pad patterns of the other pair; (c) repeating this measuring method between the electrode pad patterns of each pair; and (d) determining a first plug resistance of the first or fourth contact hole and a second plug resistance of the second or third contact hole from the voltage and the first to third currents.
摘要翻译：本发明提供了一种用于分别测量接触电阻的插头电阻和界面电阻的测试图案和方法，包括以下步骤：（a）在半导体芯片上提供如上所述的测试图案; （b）在一对第一和第二电极焊盘图形中的一个的电极焊盘图案和一对第三和第四电极焊盘图案之间施加预定电压，并测量在一对电极焊盘图案之间流动的电流另一对的电极焊盘图案之间的打开状态; （c）在每对电极焊盘图案之间重复该测量方法; 以及（d）从电压和第一至第三电流确定第一或第四接触孔的第一插头电阻和第二或第三接触孔的第二插头电阻。

29. 发明授权

US5861653A Semiconductor device having gaseous isolating layer formed in inter-level insulating layer and process of fabrication thereof 失效
标题翻译：具有在层间绝缘层中形成的气体隔离层的半导体器件及其制造工艺
公开(公告)号：US5861653A
公开(公告)日：1999-01-19
申请号：US644339
申请日：1996-05-10
申请人： Hiromitsu Hada
发明人： Hiromitsu Hada
IPC分类号： H01L21/316 , H01L21/764 , H01L21/768 , H01L23/522 , H01L29/78 , H01L27/08 , H01L29/51
CPC分类号： H01L21/764 , H01L23/5222 , H01L2924/0002
摘要： An inter-level insulating structure is formed by a lower silicon oxide layer, an upper silicon oxide layer and an air layer filling a gap between the lower silicon oxide layer and the upper silicon oxide layer, and the air layer decreases the effective dielectric constant so that a parasitic capacitance across the inter-level insulating structure is drastically decreased.
摘要翻译：层间绝缘结构由下部氧化硅层，上部氧化硅层和填充下部氧化硅层和上部氧化硅层之间的间隙的空气层形成，空气层降低有效介电常数，因此跨层间绝缘结构的寄生电容急剧下降。

30. 发明授权

US5753555A Method for forming semiconductor device 失效
标题翻译：半导体器件形成方法
公开(公告)号：US5753555A
公开(公告)日：1998-05-19
申请号：US736193
申请日：1996-10-24
申请人： Hiromitsu Hada
发明人： Hiromitsu Hada
IPC分类号： H01L21/285 , H01L21/336 , H01L29/08 , H01L29/417 , H01L29/78
CPC分类号： H01L29/66666 , H01L21/28525 , H01L29/0847 , H01L29/41775 , H01L29/41783 , H01L29/66575 , H01L29/66628 , H01L29/7827 , Y10S117/902
摘要： A method is provided for forming an epitaxial silicon layer on a diffused region of a silicon substrate having an anisotropic ratio of more than 3:1 between the growth rate in the direction perpendicular to the substrate surface and the growth rate in the direction parallel to the substrate surface. The epitaxial silicon layer serves as a contact plug which does not contact an adjacent contact plug formed by the same process in order to obtain a reliable semiconductor memory device with a high throughput, which is free from short circuit failure.
摘要翻译：提供了一种用于在硅衬底的扩散区上形成外延硅层的方法，所述外延硅层在垂直于衬底表面的方向上的生长速率与平行于衬底表面的方向上的生长速率之间具有大于3:1的各向异性比的扩散区域基材表面。外延硅层用作不与相同工艺形成的相邻接触插头接触的接触插塞，以便获得具有高通量的可靠的半导体存储器件，该半导体存储器件没有短路故障。

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