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21. 发明授权

US5698876A Memory standard cell macro for semiconductor device 失效
标题翻译：用于半导体器件的内存标准单元宏
公开(公告)号：US5698876A
公开(公告)日：1997-12-16
申请号：US576477
申请日：1995-12-21
申请人： Tomoaki Yabe , Shinji Miyano , Katsuhiko Sato , Kenji Numata
发明人： Tomoaki Yabe , Shinji Miyano , Katsuhiko Sato , Kenji Numata
IPC分类号： G11C11/401 , G11C11/00 , G11C11/4074 , G11C29/14 , H01L21/82 , H01L27/02 , H01L27/10 , H01L27/118 , H01L27/108
CPC分类号： G11C29/14 , G11C11/005 , G11C11/4074 , H01L27/0207 , Y10S257/909
摘要： A semiconductor device of a memory-macro type can be designed within a short time to have a desired storage capacity, which does not occupy a large area, so as to reduce the chip cost. The semiconductor device includes a memory macro having sub-memory macros, each sub-memory macro having a DRAM memory-cell array, and a row decoder and a column decoder for selecting any desired memory-cell from the memory cell of the array. The memory macro also includes a control-section macro having a DC potential generating circuit for generating various DC potentials required to drive the sub-memory macros. At least one of the sub-memory macros is combined with the control-section macro to form the memory macro as a one-chip memory capable of storing an integral multiple of N bits.
摘要翻译：可以在短时间内设计存储器 - 宏型半导体器件以具有不占用大面积的期望的存储容量，从而降低芯片成本。半导体器件包括具有子存储器宏的存储器宏，每个子存储器宏具有DRAM存储单元阵列，以及用于从阵列的存储器单元中选择任何所需存储单元的行解码器和列解码器。存储器宏还包括具有DC电位产生电路的控制部分宏，用于产生驱动子存储器宏所需的各种DC电位。子存储器宏中的至少一个与控制部分宏组合以形成作为能够存储N位的整数倍的单片存储器的存储器宏。

22. 发明授权

US5559748A Semiconductor integrated circuit allowing change of product specification and chip screening method therewith 失效
标题翻译：半导体集成电路允许改变产品规格和芯片筛选方法
公开(公告)号：US5559748A
公开(公告)日：1996-09-24
申请号：US438656
申请日：1995-05-09
申请人： Kenji Numata , Masaki Ogihara
发明人： Kenji Numata , Masaki Ogihara
IPC分类号： G11C11/406 , G11C5/00 , G11C7/10 , G11C11/401 , G11C11/407 , G11C11/408 , G11C29/00 , G11C29/44 , G11C29/50 , G11C29/56 , H01L27/10 , G11C7/00
CPC分类号： G11C11/4085 , G11C11/406 , G11C29/028 , G11C29/44 , G11C29/50 , G11C29/50016 , G11C5/00 , G11C5/06 , G11C7/1018 , G11C11/401
摘要： A semiconductor integrated circuit capable of changing a product specification comprises a first circuit section having a first function, a second circuit section having a second function, and active signal generator means for producing an active signal for activating either the first circuit section or the second circuit section. To change the product specification, the integrated circuit further comprises means for receiving a decision signal, switching signal generator means, connected to said receiving means, for producing a switching signal for changing the product specification according to the decision signal, and switching means for receiving the active signal and the switching signal and for supplying the active signal to either the first circuit section or the second circuit section according to the switching signal.
摘要翻译：能够改变产品规格的半导体集成电路包括具有第一功能的第一电路部分，具有第二功能的第二电路部分和用于产生用于激活第一电路部分或第二电路的有源信号的有源信号发生器装置部分。为了改变产品规格，集成电路还包括用于接收决定信号的装置，连接到所述接收装置的切换信号发生装置，用于根据判定信号产生用于改变产品规格的切换信号，以及接收装置有源信号和切换信号，并根据切换信号将有效信号提供给第一电路部分或第二电路部分。

23. 发明授权

US5555523A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5555523A
公开(公告)日：1996-09-10
申请号：US556148
申请日：1995-11-09
申请人： Ryo Haga , Tomoaki Yabe , Shinji Miyano , Kenji Numata
发明人： Ryo Haga , Tomoaki Yabe , Shinji Miyano , Kenji Numata
IPC分类号： G11C11/409 , G11C11/401 , G11C11/4091 , G11C11/4094 , H01L21/8242 , H01L27/108 , G11C7/00
CPC分类号： G11C11/4091 , G11C11/4094
摘要： A semiconductor memory device comprises a plurality of memory cells including at least a first memory cell and a second memory cell, a first bit line connected to the first memory cell, a second bit line connected to the second memory cell and paired with the first bit line, an equalizer connected between the first and second bit lines, an amplifier connected between the first and second bit lines, a first driving signal line connected to the amplifier and drives the amplifier, a second driving signal line connected to the amplifier and paired with the first driving signal line, a driver for driving the amplifier and connected to the first and second driving signal lines and containing a precharger for presetting the potentials of the first and second driving signal lines to a predetermined precharge potential and a driving signal supply circuit for supplying a driving signal to the first and second driving signal lines, and a control circuit for controlling the equalizer and the driver, wherein the control circuit controls the equalizer and the precharger independently so that the precharger continues supplying the precharge potential to the first and second driving signal lines until essentially immediately before the driving signal supply circuit supplies the driving signal to the first and second driving signal lines.
摘要翻译：半导体存储器件包括至少包括第一存储器单元和第二存储单元的多个存储器单元，连接到第一存储器单元的第一位线，连接到第二存储单元的第二位线，并与第一位配对连接在第一和第二位线之间的均衡器，连接在第一和第二位线之间的放大器，连接到放大器并驱动放大器的第一驱动信号线，连接到放大器的第二驱动信号线，第一驱动信号线，用于驱动放大器并连接到第一和第二驱动信号线并且包含用于将第一和第二驱动信号线的电位预设为预定预充电电位的预充电器的驱动器和用于向第一和第二驱动信号线提供驱动信号，以及用于控制均衡器和驱动器的控制电路 r，其中控制电路独立地控制均衡器和预充电器，使得预充电器继续向第一和第二驱动信号线提供预充电电位，直到驱动信号提供电路将驱动信号提供给第一和第二驱动信号为止线条。

24. 发明公开

US20230238764A1 Piezo-tuned nonplanar ring oscillator with GHz range and 100 kHz bandwidth 审中-公开
公开(公告)号：US20230238764A1
公开(公告)日：2023-07-27
申请号：US18099362
申请日：2023-01-20
申请人： Thomas James Kane , Kenji Numata , John Lawrence Nightingale
发明人： Thomas James Kane , Kenji Numata , John Lawrence Nightingale
IPC分类号： H01S3/083 , H01S3/06 , H01S3/10
CPC分类号： H01S3/083 , H01S3/0627 , H01S3/1003
摘要： A monolithic nonplanar ring oscillator (NPRO) laser with a large piezo-electric tuning range and high frequency slew rate, denoted as a μNPRO, is described. A tuning range of 3.5 GHz with 192 volts applied, corresponding to a tuning coefficient of 18.2 MHz/volt was experimentally demonstrated. This performance was achieved by making the solid-state gain element small, with a small distance between a piezo-electric element bonded to the solid-state gain element and a first lase plane in the solid-state gain element. The entire nonplanar ring lasing path within the solid-state gain element may lie within the half of the solid-state gain element closest to the bonded piezo-electric element. This large frequency modulation span and wide frequency modulation bandwidth, combined with unsurpassed coherence and high power, make this an attractive laser for frequency-modulated continuous-wave (FMCW) LIDAR.

25. 发明申请

US20100135342A1 System and Method for Tuning Adjusting the Central Frequency of a Laser While Maintaining Frequency Stabilization to an External Reference 有权
标题翻译：调整激光器中心频率的系统和方法，同时保持频率稳定到外部参考
公开(公告)号：US20100135342A1
公开(公告)日：2010-06-03
申请号：US12496954
申请日：2009-07-02
申请人： Jeffrey Livas , James I. Thorpe , Kenji Numata
发明人： Jeffrey Livas , James I. Thorpe , Kenji Numata
IPC分类号： H01S3/13 , H01S3/10
CPC分类号： H01S3/1398
摘要： A method and system for stabilizing a laser to a frequency reference with an adjustable offset. The method locks a sideband signal generated by passing an incoming laser beam through the phase modulator to a frequency reference, and adjusts a carrier frequency relative to the locked sideband signal by changing a phase modulation frequency input to the phase modulator. The sideband signal can be a single sideband (SSB), dual sideband (DSB), or an electronic sideband (ESB) signal. Two separate electro-optic modulators can produce the DSB signal. The two electro-optic modulators can be a broadband modulator and a resonant modulator. With a DSB signal, the method can introduce two sinusoidal phase modulations at the phase modulator. With ESB signals, the method can further drive the optical phase modulator with an electrical signal with nominal frequency Ω1 that is phase modulated at a frequency Ω2.
摘要翻译：一种用于将激光器稳定到具有可调偏移的频率参考的方法和系统。该方法锁定通过将入射激光束通过相位调制器而产生的边带信号为频率参考，并且通过改变输入到相位调制器的相位调制频率来调整相对于锁定边带信号的载波频率。边带信号可以是单边带（SSB），双边带（DSB）或电子边带（ESB）信号。两个单独的电光调制器可以产生DSB信号。两个电光调制器可以是宽带调制器和谐振调制器。利用DSB信号，该方法可以在相位调制器上引入两个正弦相位调制。使用ESB信号，该方法可以用具有标称频率的电信号进一步驱动光相位调制器，并且以频率ωgr相位调制OHgr; 2。

26. 发明授权

US07331249B2 Non-destructive inspection apparatus and non-destructive inspection system 有权
标题翻译：无损检测仪器和无损检测系统
公开(公告)号：US07331249B2
公开(公告)日：2008-02-19
申请号：US11294920
申请日：2005-12-06
申请人： Kenji Numata
发明人： Kenji Numata
IPC分类号： G01M19/00
CPC分类号： G01N29/265 , G01N29/043 , G01N2291/0231 , G01N2291/105 , G01N2291/2694
摘要： A nondestructive inspection device nondestructively inspects an internal state of an inspection target, and transmits information indicating a progress status of the inspection to the outside of an inspection site. A nondestructive inspection system which uses this nondestructive inspection device includes a network connected to the nondestructive inspection device, and one or a plurality of computers connected via the network to the nondestructive inspection device.
摘要翻译：非破坏性检查装置无损检查检查对象的内部状态，并将检查进度状态的信息发送到检查部位外部。使用该非破坏性检查装置的非破坏性检查系统包括连接到非破坏性检查装置的网络和经由网络连接到非破坏性检查装置的一个或多个计算机。

27. 发明申请

US20060265094A1 Non-destructive inspection apparatus and non-destructive inspection system 有权
标题翻译：无损检测仪器和无损检测系统
公开(公告)号：US20060265094A1
公开(公告)日：2006-11-23
申请号：US11294920
申请日：2005-12-06
申请人： Kenji Numata
发明人： Kenji Numata
IPC分类号： G06F19/00
CPC分类号： G01N29/265 , G01N29/043 , G01N2291/0231 , G01N2291/105 , G01N2291/2694
摘要： A nondestructive inspection device nondestructively inspects an internal state of an inspection target, and transmits information indicating a progress status of the inspection to the outside of an inspection site. A nondestructive inspection system which uses this nondestructive inspection device includes a network connected to the nondestructive inspection device, and one or a plurality of computers connected via the network to the nondestructive inspection device.
摘要翻译：非破坏性检查装置无损检查检查对象的内部状态，并将检查进度状态的信息发送到检查部位外部。使用该非破坏性检查装置的非破坏性检查系统包括连接到非破坏性检查装置的网络和经由网络连接到非破坏性检查装置的一个或多个计算机。

28. 再颁专利

USRE37184E1 Semiconductor memory and screening test method thereof 失效
标题翻译：半导体存储器及其筛选试验方法
公开(公告)号：USRE37184E1
公开(公告)日：2001-05-22
申请号：US09108266
申请日：1998-07-01
申请人： Natsuki Kushiyama , Tohru Furuyama , Kenji Numata
发明人： Natsuki Kushiyama , Tohru Furuyama , Kenji Numata
IPC分类号： G11C700
CPC分类号： G11C29/025 , G11C11/401 , G11C29/02 , G11C29/028 , G11C29/24 , G11C29/50 , G11C2029/5004 , G11C2029/5006
摘要： A semiconductor memory comprises a dynamic type memory cell array arranged to form a matrix and provided with word lines commonly connected to memory cells of respective columns and bit lines commonly connected to memory cells of respective rows, a dummy cell section having a first set of dummy word lines connected to respective complimentary bit line pairs of said memory cell array by way of respective first capacitances and a second set of dummy word lines connected to respective complementary bit line pairs of said memory cell array by way of respective second capacitances, a dummy word line potential control circuit capable of optionally controlling the mode of driving selected dummy word lines when said word lines of said memory cell array are activated and sense amplifiers connected to the respective complementary bit line pairs of said memory cell array for reading data from selected memory cells of the memory cell array onto the related bit line.
摘要翻译：半导体存储器包括动态型存储单元阵列，其布置成形成矩阵并且设置有通常连接到相应列的存储器单元的字线和共同连接到各行的存储单元的位线的虚拟单元部分，虚拟单元部分具有第一组虚拟通过相应的第一电容连接到所述存储单元阵列的相应互补位线对的字线和通过相应的第二电容连接到所述存储单元阵列的相应互补位线对的第二组虚拟字线，线电势控制电路，当所述存储单元阵列的所述字线被激活时，能够可选地控制驱动所选择的虚拟字线的模式，以及连接到所述存储单元阵列的相应互补位线对的读出放大器，用于从所选存储单元读取数据的存储单元阵列到相关位线上。

29. 发明授权

US5881006A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5881006A
公开(公告)日：1999-03-09
申请号：US936550
申请日：1997-09-24
申请人： Tomoaki Yabe , Shinji Miyano , Kenji Numata
发明人： Tomoaki Yabe , Shinji Miyano , Kenji Numata
IPC分类号： G11C11/401 , G11C7/06 , G11C7/10 , G11C8/12 , G11C11/409 , G11C11/4091 , H01L21/8242 , H01L27/108 , G11C7/00
CPC分类号： G11C8/12 , G11C11/4091 , G11C7/065 , G11C7/103 , G11C7/1051
摘要： A semiconductor memory device includes a memory cell array having a plurality of memory cells arranged in rows and columns, a plurality of pairs of bit lines to each of which the plurality of memory cells arranged in the column direction are connected, a plurality of latch type amplifiers each of which is provided between the bit lines of a corresponding one of the bit line pairs to amplify a potential difference between the bit lines, a plurality of activation circuits for respectively activating the plurality of latch type amplifiers, a data bus acting as passages of input data, a plurality of latch type storage circuits each of which is provided on a corresponding one of the columns and connected to the data bus, for temporarily storing the input data, a plurality of transfer gates for transferring the input data from the latch type storage circuits to the latch type amplifiers, and a transfer control circuit for controlling the transfer gates to simultaneously transfer the input data from the latch type storage circuits to the latch type amplifiers for each of the rows, wherein the memory cell array is divided into a plurality of sub-arrays including a preset number of columns and the activation circuits are provided for the respective sub-arrays.
摘要翻译：一种半导体存储器件，包括具有以行和列排列的多个存储单元的存储单元阵列，与列方向排列的多个存储单元连接的多对位线，多个锁存型放大器中的每一个被提供在相应的一个位线对的位线之间以放大位线之间的电位差，多个激活电路用于分别激活多个闩锁型放大器，数据总线作为通道输入数据的多个锁存型存储电路，其各自设置在相应的列上并连接到数据总线，用于临时存储输入数据;多个传输门，用于从锁存器传送输入数据类型存储电路到锁存型放大器，以及传输控制电路，用于控制传输门以同时传送输入da 其中存储单元阵列被分成包括预定数量的列的多个子阵列，并且为每个子阵列提供激活电路。

30. 发明授权

US5706229A Semiconductor memory device 失效
公开(公告)号：US5706229A
公开(公告)日：1998-01-06
申请号：US553035
申请日：1995-11-03
申请人： Tomoaki Yabe , Shinji Miyano , Kenji Numata
发明人： Tomoaki Yabe , Shinji Miyano , Kenji Numata
IPC分类号： G11C11/401 , G11C7/06 , G11C7/10 , G11C8/12 , G11C11/409 , G11C11/4091 , H01L21/8242 , H01L27/108 , G11C7/00
CPC分类号： G11C8/12 , G11C11/4091 , G11C7/065 , G11C7/103 , G11C7/1051
摘要： A semiconductor memory device includes a memory cell array having a plurality of memory cells arranged in rows and columns, a plurality of pairs of bit lines to each of which the plurality of memory cells arranged in the column direction are connected, a plurality of latch type amplifiers each of which is provided between the bit lines of a corresponding one of the bit line pairs to amplify a potential difference between the bit lines, a plurality of activation circuits for respectively activating the plurality of latch type amplifiers, a data bus acting as passages of input data, a plurality of latch type storage circuits each of which is provided on a corresponding one of the columns and connected to the data bus, for temporarily storing the input data, a plurality of transfer gates for transferring the input data from the latch type storage circuits to the latch type amplifiers, and a transfer control circuit for controlling the transfer gates to simultaneously transfer the input data from the latch type storage circuits to the latch type amplifiers for each of the rows, wherein the memory cell array is divided into a plurality of sub-arrays including a preset number of columns and the activation circuits are provided for the respective sub-arrays.

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