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21. 发明授权

US06442075B2 Erasing method for nonvolatile semiconductor memory device capable of improving a threshold voltage distribution 有权
公开(公告)号：US06442075B2
公开(公告)日：2002-08-27
申请号：US09897999
申请日：2001-07-05
申请人： Yasuaki Hirano
发明人： Yasuaki Hirano
IPC分类号： G11C1604
CPC分类号： G11C16/3468
摘要： In a first step, “application of an erasing pulse” and “verification” are conducted so that all the memory cells in an erasing-target block are set to 3V or less. Consequently, generation of a memory cell with a negative threshold voltage is prevented, and accurate verification is conducted to ensure that all the memory cells in a block are brought in an erased state. In a second step, “application of an erasing pulse” is executed to set a threshold voltage of the most erase-slow memory cell to 1.5V or less. In this process, instead of conducting verification, the pulse is applied N times as large as the number of pulse application in the first step. In a third step, “application of a program pulse” and “verification” are conducted to execute a channel writing.

22. 发明授权

US06433582B1 Voltage level shifter circuit 失效
公开(公告)号：US06433582B1
公开(公告)日：2002-08-13
申请号：US09025995
申请日：1998-02-19
申请人： Yasuaki Hirano
发明人： Yasuaki Hirano
IPC分类号： H03K19094
摘要： A voltage level shifter circuit includes a first transistor having a source, a drain, and first and second gates; a second transistor having a source, a drain, and first and second gates; and a switching section for receiving an input signal and changing respective voltages to be applied to first and second nodes, wherein one of the source and the drain of each of the first and second transistors is connected to a third node, the first gate of each of the first and second transistors is connected to the third node, the other of the source and the drain of the first transistor and the second gate of the second transistor are connected to the first node, and the other of the source and the drain of the second transistor and the second gate of the first transistor are connected to the second node, the voltage level shifter circuit further including a resistance equivalent element having first and second ends, a high voltage being applied to the first end, and the second end being are connected to the third node.

23. 发明授权

US06198659B1 Defective address data storage circuit for nonvolatile semiconductor memory device having redundant function and method of writing defective address data 有权
标题翻译：具有冗余功能的非易失性半导体存储器件的不良地址数据存储电路和写入不良地址数据的方法
公开(公告)号：US06198659B1
公开(公告)日：2001-03-06
申请号：US09592964
申请日：2000-06-13
申请人： Yasuaki Hirano
发明人： Yasuaki Hirano
IPC分类号： G11C1600
CPC分类号： G11C29/789 , G11C8/06 , G11C16/08 , G11C16/3418 , G11C16/3427 , G11C29/82
摘要： In a defective address data storage circuit for a nonvolatile semiconductor memory, electrically erasable programmable memory cells are arranged in rows and columns. A plurality of word lines are connected to the memory cells in each row, while a plurality of bit lines are connected to the memory cells in each column. There are further provided a column decoder for selecting a bit line and a word line decoder circuit selecting a different word line in a different write operation of defective address data. Because a different word line is selected every writing of defective address data, a write voltage is only once applied to memory cells connected to an identical word line.
摘要翻译：在用于非易失性半导体存储器的缺陷地址数据存储电路中，电可擦除可编程存储单元以行和列布置。多行字线连接到每行的存储单元，而多列位线连接到各列中的存储单元。还提供了一种列解码器，用于在不同地址数据的不同写入操作中选择位线和字线解码器电路来选择不同的字线。由于在每次写入缺陷地址数据时都选择了不同的字线，写入电压仅被一次施加到连接到相同字线的存储器单元。

24. 发明授权

US06195287B1 Data programming method for a nonvolatile semiconductor storage 有权
标题翻译：非易失性半导体存储器的数据编程方法
公开(公告)号：US06195287B1
公开(公告)日：2001-02-27
申请号：US09497053
申请日：2000-02-02
申请人： Yasuaki Hirano
发明人： Yasuaki Hirano
IPC分类号： A11C1604
CPC分类号： G11C16/3459 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/0491 , G11C16/10 , G11C16/3454 , G11C2211/5621
摘要： A data programming method for a nonvolatile semiconductor storage device includes: a number of memory cells each having a control gate, drain and source with an electrically data-programmable, erasable floating gate, arranged matrix-wise in rows and columns forming a memory cell array; a multiple number of word lines, each being connected to the control gates of the memory cells in one row; and a multiple number of bit lines, each being connected to the drains of the memory cells in one column and also connected to the sources of the memory cells in the adjacent column so that each is shared by the two adjacent columns, forming a virtual ground type array, wherein three or more classes of data can be electrically written into each memory cell by differentiating the threshold level of the charge amount accumulated on the floating gate. The method includes: the first writing step for setting the charge amount on the floating gate of each memory cell to be programmed with target data at a first threshold level other than the threshold level of target data; and the second writing step for re-setting the charge amount on the floating gate of the memory cell at the threshold level of target data, after the first writing step.
摘要翻译：一种用于非易失性半导体存储装置的数据编程方法包括：多个存储单元，每个存储单元具有控制栅极，漏极和源极以及电数据可编程的可擦除浮动栅极，按行和列形成一个存储单元阵列 ; 多个字线，各自连接到一行中的存储器单元的控制栅极; 和多个位线，每个位线连接到一列中的存储器单元的漏极，并且还连接到相邻列中的存储器单元的源，使得每个位线由两个相邻列共享，形成虚拟地类型阵列，其中通过对在浮动栅极上累积的电荷量的阈值电平进行微分，可以将三个或更多类数据电写入每个存储单元。该方法包括：第一写入步骤，用于在除了目标数据的阈值水平之外的第一阈值电平上设置要对目标数据进行编程的每个存储器单元的浮动栅极上的电荷量; 以及第二写入步骤，用于在第一写入步骤之后，以目标数据的阈值水平重新设置存储器单元的浮动栅极上的电荷量。

25. 发明授权

US6160735A Negative voltage level shifter circuit and nonviolatile semiconductor storage device including the circuit 失效
标题翻译：负电压电平移位电路和非易失性半导体存储器件包括电路
公开(公告)号：US6160735A
公开(公告)日：2000-12-12
申请号：US455810
申请日：1999-12-07
申请人： Yasuaki Hirano
发明人： Yasuaki Hirano
IPC分类号： G11C16/06 , G11C5/14 , G11C16/12 , G11C16/16 , H03K17/10 , H03K19/0185 , G11C16/04
CPC分类号： G11C16/16 , G11C5/145 , G11C16/12
摘要： Between a first negative voltage level shifter which is made up of transistors having a normal breakdown voltage and which shifts an input signal of a level Vcc or Vss to a level Vcc or Vnmin, and a second negative voltage level shifter which is made up of transistors having a normal breakdown voltage and which shifts an input signal of a level Vnmin or Vss to a level Vss or Vneg, is provided an inverter 8 for converting the level Vcc or Vnmin derived from the first negative voltage level shifter to the level Vnmin or Vss and then feeds the resulting voltage level to the second negative voltage level shifter. Vnmin, which is an intermediate level between Vss and Vneg, is set so that the maximum voltage difference of voltages applied to the transistors of the first negative voltage level shifter becomes equal to or smaller than the breakdown voltage. Thus, an output of Vneg (Vss-breakdown voltage of transistors of second negative voltage level shifter) lower in level than the conventional Vneg (Vcc-Vss-breakdown voltage) is obtained. As a result, the absolute value of the outputted negative voltage can be increased without increasing the breakdown voltage of the transistors.
摘要翻译：在由具有正常击穿电压的晶体管构成的第一负电压电平移位器和将电平Vcc或Vss的输入信号移位到电平Vcc或Vnmin之间的第一负电压电平移位器和由晶体管具有正常击穿电压并将电平Vnmin或Vss的输入信号移位到电平Vss或Vneg的反相器8，用于将从第一负电压电平移位器导出的电平Vcc或Vnmin转换为电平Vnmin或Vss 然后将所得到的电压电平馈送到第二负电压电平移位器。 Vnmin是Vss和Vneg之间的中间电平，使得施加到第一负电压电平移位器的晶体管的电压的最大电压差变得等于或小于击穿电压。因此，获得了比常规Vneg（Vcc-Vss击穿电压）更低的Vneg（第二负电压电平移位器的晶体管的Vss击穿电压）的输出。结果，可以在不增加晶体管的击穿电压的情况下增加输出的负电压的绝对值。

26. 发明授权

US6111785A Nonvolatile semiconductor memory device capable of decreasing layout area for writing defective address 有权
标题翻译：非易失性半导体存储器件能够减少写入缺陷地址的布局区域
公开(公告)号：US6111785A
公开(公告)日：2000-08-29
申请号：US379009
申请日：1999-08-23
申请人： Yasuaki Hirano
发明人： Yasuaki Hirano
IPC分类号： G11C16/06 , G11C8/06 , G11C16/08 , G11C29/04
CPC分类号： G11C8/06 , G11C16/08
摘要： A latch circuit functions as a write latch circuit when writing a defective address into a nonvolatile semiconductor memory cell array. The latch circuit also functions as a defective address latch circuit when the power voltage rises. Therefore, the layout area of the defective address setting circuit can be reduced as compared with the defective address setting circuit of the conventional flash memory of the FN--FN type provided with a write latch circuit and a defective address latch circuit.
摘要翻译：当将缺陷地址写入非易失性半导体存储单元阵列时，锁存电路用作写锁存电路。当电源电压上升时，锁存电路也起缺陷地址锁存电路的作用。因此，与设置有写入锁存电路和缺陷地址锁存电路的FN-FN类型的常规闪存的缺陷地址设置电路相比，可以减少缺陷地址设置电路的布局面积。

27. 发明授权

US5910918A Data writing circuit for a nonvolatile semiconductor memory 失效
标题翻译：用于非易失性半导体存储器的数据写入电路
公开(公告)号：US5910918A
公开(公告)日：1999-06-08
申请号：US924417
申请日：1997-08-27
申请人： Yasuaki Hirano
发明人： Yasuaki Hirano
IPC分类号： G11C16/04 , G11C16/06 , G11C16/10 , G11C16/12
CPC分类号： G11C16/10 , G11C16/12
摘要： A data writing circuit includes: a transfer gate (TG) selecting a bit line (BL0) of a virtually grounded cell array; a latch circuit (L) connected to the bit line (BL0) via the transfer gate (TG) for latching the data to be written, given to the bit line; a switching circuit (PM) which is connected between the bit line (BL0) and a program power source (VFROG) and is activated in accordance with the data to be written which has been latched by the latch circuit (L), to thereby supply the program power source (V.sub.PROG) to the bit line (BL0). This circuit, in accordance with the data to be written, sets the bit line (BL0) to which a memory cell (M) is connected, to a state of being applied by the program power source (V.sub.PROG) or a floating state.
摘要翻译：数据写入电路包括：选择虚拟接地的单元阵列的位线（BL0）的传输门（TG）; 经由传输门（TG）连接到位线（BL0）的锁存电路（L），用于锁存给定位置的待写入数据; 连接在位线（BL0）和程序电源（VFROG）之间的开关电路（PM），并根据由锁存电路（L）锁存的要写入的数据而被激活，由此提供程序电源（VPROG）到位线（BL0）。该电路根据要写入的数据将与存储单元（M）连接的位线（BL0）设置为由程序电源（VPROG）或浮置状态施加的状态。

28. 发明授权

US08297826B2 Backlight unit and display device including the same 有权
标题翻译：背光单元和显示设备包括相同
公开(公告)号：US08297826B2
公开(公告)日：2012-10-30
申请号：US12958452
申请日：2010-12-02
申请人： Kenichi Murakoshi , Tsuyoshi Ono , Hidekazu Fujii , Yasuaki Hirano , Makoto Hirota
发明人： Kenichi Murakoshi , Tsuyoshi Ono , Hidekazu Fujii , Yasuaki Hirano , Makoto Hirota
IPC分类号： F21V7/04
CPC分类号： G02B6/0068 , G02B6/0073 , G02B6/0083 , G02F1/133603 , G02F1/133611 , G02F1/133615
摘要： Provided is a backlight unit capable of reducing luminance unevenness. The backlight unit includes a plurality of dot light sources and a light guide plate in which a predetermined side surface serves as a light incident surface for introducing light from the plurality of dot light sources. The plurality of dot light sources are classified into a first light source group and a second light source group. A mount point of the first light source group and a mount point of the second light source group are displaced from each other in a thickness direction of the light guide plate. A total luminance of the first light source group is higher than a total luminance of the second light source group.
摘要翻译：提供能够降低亮度不均匀性的背光单元。背光单元包括多个点光源和导光板，其中预定侧表面用作用于引入来自多个点光源的光的光入射表面。多个点光源分为第一光源组和第二光源组。第一光源组的安装点和第二光源组的安装点在导光板的厚度方向上彼此偏移。第一光源组的总亮度高于第二光源组的总亮度。

29. 发明授权

US06831858B2 Non-volatile semiconductor memory device and data write control method for the same 有权
公开(公告)号：US06831858B2
公开(公告)日：2004-12-14
申请号：US10637923
申请日：2003-08-08
申请人： Yasuaki Hirano , Shuichiro Kouchi
发明人： Yasuaki Hirano , Shuichiro Kouchi
IPC分类号： G11C1604
CPC分类号： G11C29/50004 , G11C11/5628 , G11C16/04 , G11C16/30 , G11C29/006
摘要： A non-volatile semiconductor memory device, is provided, which comprises a plurality of memory cells capable of electrically writing and erasing data and a voltage control section for controlling a control voltage to be applied to each of the plurality of row lines. The voltage control section comprises a storing section and a voltage output section. The storing section stores the value of the control voltage, which is calculated to permit a threshold voltage distribution to be within a predetermined range, in accordance with the threshold voltage distribution of the plurality of memory cells in each chip. The voltage output section outputs the control voltage having the value stored in the storing section to each of the plurality of row lines.

30. 发明授权

US06768676B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US06768676B2
公开(公告)日：2004-07-27
申请号：US10350332
申请日：2003-01-24
申请人： Yasuaki Hirano
发明人： Yasuaki Hirano
IPC分类号： G11C1604
CPC分类号： G11C16/30 , G11C8/14 , G11C11/5628 , G11C16/08
摘要： This nonvolatile semiconductor memory device includes a word line regulator circuit 22, which supplies a voltage to a word line, a program/erase control circuit 21, which outputs a write control signal to the word line regulator circuit 22, and a pulse voltage step width storage circuit 23, which stores information of a voltage increment &Dgr;Vg. The word line regulator circuit 22 supplies a voltage to a word line according to the write control signal from the program/erase control circuit 21 based on the information of a voltage increment &Dgr;Vg stored in the pulse voltage step width storage circuit 23. A voltage increment &Dgr;Vg by which a threshold voltage change of a memory cell becomes a predetermined voltage can be set for each chip by the pulse voltage step width storage circuit 23. Consequently, a highly reliable multi-valued write operation can be performed.
摘要翻译：该非易失性半导体存储器件包括向字线提供电压的字线调节器电路22，向字线调节器电路22输出写入控制信号的编程/擦除控制电路21以及脉冲电压阶跃宽度存储电路23，其存储电压增量DeltaVg的信息。字线调整电路22根据存储在脉冲电压阶跃宽度存储电路23中的电压增量DeltaVg的信息，根据来自编程/擦除控制电路21的写入控制信号向字线提供电压。电压增量可以通过脉冲电压阶跃宽度存储电路23为每个芯片设置存储单元的阈值电压变化为预定电压的ΔVg。因此，可以执行高度可靠的多值写入操作。

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