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22. 发明授权

US6016065A Charges recycling differential logic(CRDL) circuit and storage elements and devices using the same 有权
标题翻译：收费回收差分逻辑（CRDL）电路和使用其的存储元件和器件
公开(公告)号：US6016065A
公开(公告)日：2000-01-18
申请号：US234517
申请日：1999-01-21
申请人： Bai-Sun Kong
发明人： Bai-Sun Kong
IPC分类号： G11C11/41 , G11C7/00 , G11C11/412 , H03K3/356 , H03K19/00 , H03K19/0944 , H03K19/096 , H03K19/173 , H03K19/21
CPC分类号： G11C11/412 , H03K19/0019 , H03K19/0963 , H03K19/1738 , H03K19/215 , H03K3/356147 , G06F2207/3884
摘要： A storage element for a semiconductor device in accordance with preferred embodiments exhibit less noise and consumes less power with faster speed. A first circuit maintains a first storage node at a same signal level of a previous state when an input signal at an input electrode transits from one of (i) first signal level to second signal level and (ii) third signal level to second signal level. The first circuit includes a first plurality of transistors coupled to the input electrode, and a first pair of transistors coupled to said first plurality of transistors and coupled to each other at the first storage node. A second circuit, coupled to said first circuit, changes a condition of said first storage node to one of (i) first signal level when the input signal transits from the second signal level to the first signal level and (ii) third signal level when the input signal transits from the second signal level to the third signal level.
摘要翻译：根据优选实施例的用于半导体器件的存储元件表现出较小的噪声并且以更快的速度消耗更少的功率。当输入电极的输入信号从（i）第一信号电平之一转换到第二信号电平时，第一电路将先前状态的第一存储节点维持在相同的信号电平，以及（ii）第三信号电平转换到第二信号电平。第一电路包括耦合到输入电极的第一多个晶体管，以及耦合到所述第一多个晶体管并在第一存储节点处彼此耦合的第一对晶体管。当所述输入信号从所述第二信号电平转换到所述第一信号电平时，耦合到所述第一电路的第二电路将所述第一存储节点的状态改变为（i）第一信号电平之一，以及（ii）第三信号电平，输入信号从第二信号电平转换到第三信号电平。

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