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21. 发明申请

US20100042955A1 Method of Minimizing Early-mode Violations Causing Minimum Impact to a Chip Design 有权
标题翻译：最大限度地减少对芯片设计造成最小影响的早期模式违规方法
公开(公告)号：US20100042955A1
公开(公告)日：2010-02-18
申请号：US12191435
申请日：2008-08-14
申请人： POOJA M. KOTECHA , Frank J. Musante , Veena S. Pureswaran , Louise H. Trevillyan , Paul G. Villarrubia
发明人： POOJA M. KOTECHA , Frank J. Musante , Veena S. Pureswaran , Louise H. Trevillyan , Paul G. Villarrubia
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A system and a method for correcting early-mode timing violations that operate across the process space of a circuit design. Optimizations are performed to replace padding that increase path delays on fast paths. At the stage in the design process where early-mode violations are addressed, placement, late-mode timing closure, routing, and detailed electrical and timing analysis are assumed to have been completed. The optimizations are designed to be effective in delaying fast paths while minimizing the impact on already-completed work on the chip, in contrast to relying only on adding pads that can have a negative impact on all of these quantities. The optimizations are classified according to their invasiveness and are followed by their deployment. The deployment is designed to minimize using delay pads, reduce design disruptions, and minimize effects on other aspects of the design.
摘要翻译：一种用于校正在电路设计的处理空间中工作的早期模式定时违反的系统和方法。执行优化来替代在快速路径上增加路径延迟的填充。在处理早期模式违规的设计过程的阶段，假设已经完成了放置，延迟模式定时关闭，路由以及详细的电气和时序分析。优化设计是有效延迟快速路径，同时最大限度地减少对已经完成的芯片上的工作的影响，而不是仅依靠添加可能对所有这些量产生负面影响的焊盘。优化根据其入侵性进行分类，其后进行部署。该部署旨在最大限度地减少使用延迟焊盘，减少设计中断，并尽量减少对设计其他方面的影响。

22. 发明授权

US07549137B2 Latch placement for high performance and low power circuits 有权
标题翻译：用于高性能和低功耗电路的锁存放置
公开(公告)号：US07549137B2
公开(公告)日：2009-06-16
申请号：US11610567
申请日：2006-12-14
申请人： Charles J. Alpert , Shyam Ramji , Chin Ngai Sze , Paul G. Villarrubia
发明人： Charles J. Alpert , Shyam Ramji , Chin Ngai Sze , Paul G. Villarrubia
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A novel iterative latch placement scheme wherein the latches are gradually pulled by increasing attraction force until they are eventually placed next to a clock distribution structure such as a local clock buffer (LCB). During the iterations, timing optimizations such as gate sizing and re-buffering are invoked in order to keep the timing estimation accurate. By applying the iterative clock net weighting adjustment, the present invention allows tighter interaction between logic placement and clock placement which leads to higher quality timing and significant power savings.
摘要翻译：一种新颖的迭代锁存器放置方案，其中锁存器通过增加吸引力而逐渐拉动，直到它们最终被放置在诸如本地时钟缓冲器（LCB）之类的时钟分布结构旁边。在迭代期间，调用诸如门尺寸和重新缓冲之类的定时优化，以便使时序估计保持准确。通过应用迭代时钟网络加权调整，本发明允许逻辑放置和时钟布置之间的更紧密的交互，这导致更高的质量定时和显着的功率节省。

23. 发明申请

US20080066037A1 METHOD TO REDUCE THE WIRELENGTH OF ANALYTICAL PLACEMENT TECHNIQUES BY MODULATION OF SPREADING FORCES VECTORS 审中-公开
标题翻译：通过扩展力矢量调制降低分析放置技术的线性的方法
公开(公告)号：US20080066037A1
公开(公告)日：2008-03-13
申请号：US11531322
申请日：2006-09-13
申请人： Charles J. Alpert , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method of force directed placement programming is presented. The method includes sorting objects of a netlist for placement by magnitude of their spreading force and selecting a plurality of the objects. The method further includes waiving (or nullifying) the spreading force for the selected objects in a subsequent non-linear program solver step of the force directed placement program. The positions of the objects after the subsequent non-linear program solver step are based only on their connections to other objects in the netlist. The selected objects no longer retain their relative ordering as obtained during a previous non-linear program solve step of the force directed placement program. An alternative method of force directed placement programming is also present, which includes identifying objects from a netlist for placement that have a very high spreading force magnitude. The method further includes controlling the spreading force magnitude for the objects identified in the force directed placement programming to reduce wirelength in a chip design without sacrificing spreading of the objects.
摘要翻译：提出了一种强制定向布置程序的方法。该方法包括对网表的对象进行排序，以便按照其展开力的大小进行放置并选择多个对象。该方法还包括在力定向放置程序的随后非线性程序解算器步骤中放弃（或消除）所选对象的展开力。在后续非线性程序求解器步骤之后的对象的位置仅基于它们与网表中其他对象的连接。所选择的对象不再保留在力定向放置程序的先前非线性程序解决步骤中获得的相对排序。还存在一种替代的力定向放置编程的方法，其包括从具有非常高的铺展力量级的用于放置的网表识别对象。该方法还包括控制在力定向放置编程中识别的物体的展开力大小以减少芯片设计中的线长度，而不牺牲物体的扩展。

24. 发明申请

US20110320992A1 BUFFER-AWARE ROUTING IN INTEGRATED CIRCUIT DESIGN 有权
标题翻译：集成电路设计中的BUFFER-AWARE路由
公开(公告)号：US20110320992A1
公开(公告)日：2011-12-29
申请号：US12823232
申请日：2010-06-25
申请人： Chuck ALPERT , Zhuo Li , Michael David Moffitt , Chin Ngai Sze , Paul G. Villarrubia
发明人： Chuck ALPERT , Zhuo Li , Michael David Moffitt , Chin Ngai Sze , Paul G. Villarrubia
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method, system, and computer usable program product for buffer-aware routing in integrated circuit design are provided in the illustrative embodiments. The design has cells, and the circuit includes buffers and wires. A route is received from a set of routes. The route couples a first point in the circuit to a second point in the circuit and including at least one buffer between the first point and the second point. A determination is made whether the route violates a set of hard constraints for a part of the circuit, where the set of hard constraints includes a reach length constraint. In response to the route not violating any hard constraint in the set of hard constraints, the route is selected as a buffer-aware routing solution between the first and the second points in the circuit.
摘要翻译：在说明性实施例中提供了用于集成电路设计中用于缓冲器感知路由的方法，系统和计算机可用程序产品。该设计有电池，电路包括缓冲器和电线。从一组路由接收到路由。路线将电路中的第一点耦合到电路中的第二点，并且包括在第一点和第二点之间的至少一个缓冲器。确定路线是否违反了电路的一部分的一组硬约束，其中硬约束集合包括到达长度约束。响应于路由不违反硬约束集合中的任何硬约束，路由被选择为电路中的第一和第二点之间的缓冲器感知路由解决方案。

25. 发明申请

US20110302545A1 DETAILED ROUTABILITY BY CELL PLACEMENT 有权
标题翻译：细节放置的详细的不可靠性
公开(公告)号：US20110302545A1
公开(公告)日：2011-12-08
申请号：US12796501
申请日：2010-06-08
申请人： Charles J. Alpert , Andrew D. Huber , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Taraneh Taghavi , Gustavo E. Tellez , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Andrew D. Huber , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Taraneh Taghavi , Gustavo E. Tellez , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles, wherein some tiles have cells. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that are high detailed routing cost tiles. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell and a selected tile. The expander places an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile. The expander expands the selected cell within the bounding box to form a modified design, determines an aggregate routing cost among other steps, and affirms the modified design for further processing.
摘要翻译：一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。扩展器将单元格分配给图块，其中某些图块具有单元格。扩展器确定高详细路由成本瓦片类，其中高详细路由成本瓦片类是作为高详细路由成本瓦片的瓦片类。扩展器选择高详细路由代价块类别的块内的单元，以形成所选择的单元和所选择的块。扩展器将扩展的边界框放置在所选择的单元周围，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片。扩展器在边界框内扩展所选单元格以形成修改的设计，确定其他步骤之间的汇总路由成本，并确认修改后的设计以进行进一步处理。

26. 发明授权

US07996812B2 Method of minimizing early-mode violations causing minimum impact to a chip design 有权
标题翻译：最小化早期模式违规的方法，对芯片设计造成的影响最小
公开(公告)号：US07996812B2
公开(公告)日：2011-08-09
申请号：US12191435
申请日：2008-08-14
申请人： Pooja M. Kotecha , Frank J. Musante , Veena S. Pureswaran , Louise H. Trevillyan , Paul G. Villarrubia
发明人： Pooja M. Kotecha , Frank J. Musante , Veena S. Pureswaran , Louise H. Trevillyan , Paul G. Villarrubia
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A system and a method for correcting early-mode timing violations that operate across the process space of a circuit design. Optimizations are performed to replace padding that increase path delays on fast paths. At the stage in the design process where early-mode violations are addressed, placement, late-mode timing closure, routing, and detailed electrical and timing analysis are assumed to have been completed. The optimizations are designed to be effective in delaying fast paths while minimizing the impact on already-completed work on the chip, in contrast to relying only on adding pads that can have a negative impact on all of these quantities. The optimizations are classified according to their invasiveness and are followed by their deployment. The deployment is designed to minimize using delay pads, reduce design disruptions, and minimize effects on other aspects of the design.
摘要翻译：一种用于校正在电路设计的处理空间中工作的早期模式定时违反的系统和方法。执行优化来替代在快速路径上增加路径延迟的填充。在处理早期模式违规的设计过程的阶段，假设已经完成了放置，延迟模式定时关闭，路由以及详细的电气和时序分析。优化设计是有效延迟快速路径，同时最大限度地减少对已经完成的芯片上的工作的影响，而不是仅依靠添加可能对所有这些量产生负面影响的焊盘。优化根据其入侵性进行分类，其后进行部署。该部署旨在最大限度地减少使用延迟焊盘，减少设计中断，并尽量减少对设计其他方面的影响。

27. 发明申请

US20100192155A1 SCHEDULING FOR PARALLEL PROCESSING OF REGIONALLY-CONSTRAINED PLACEMENT PROBLEM 有权
标题翻译：并行处理区域性约束放置问题的调度
公开(公告)号：US20100192155A1
公开(公告)日：2010-07-29
申请号：US12359369
申请日：2009-01-26
申请人： Gi-Joon Nam , Shyam Ramji , Taraneh Taghavi , Paul G. Villarrubia
发明人： Gi-Joon Nam , Shyam Ramji , Taraneh Taghavi , Paul G. Villarrubia
IPC分类号： G06F9/50 , G06F9/46
CPC分类号： G06F17/50 , G06F9/5066
摘要： Scheduling of parallel processing for regionally-constrained object placement selects between different balancing schemes. For a small number of movebounds, computations are assigned by balancing the placeable objects. For a small number of objects per movebound, computations are assigned by balancing the movebounds. If there are large numbers of movebounds and objects per movebound, both objects and movebounds are balanced amongst the processors. For object balancing, movebounds are assigned to a processor until an amortized number of objects for the processor exceeds a first limit above an ideal number, or the next movebound would raise the amortized number of objects above a second, greater limit. For object and movebound balancing, movebounds are sorted into descending order, then assigned in the descending order to host processors in successive rounds while reversing the processor order after each round. The invention provides a schedule in polynomial-time while retaining high quality of results.
摘要翻译：区域约束对象放置的并行处理调度在不同的平衡方案之间进行选择。对于少量的移动端口，通过平衡可放置对象来分配计算。对于每次移动的少量对象，通过平衡移动端口分配计算。如果每次移动都有大量的移动和对象，则处理器之间的对象和移动对象都是平衡的。对于对象平衡，移动端口被分配给一个处理器，直到处理器的对象的摊销数量超过理想数量以上的第一个限制，或者下一个移动端口将提高超过第二个更大限制的对象数量。对于对象和移动平衡，移动排列按降序排列，然后按顺序分配给主机处理器，连续回合，同时在每轮之后反转处理器顺序。本发明提供多项式时间的时间表，同时保持高质量的结果。

28. 发明授权

US07624366B2 Clock aware placement 失效
标题翻译：时钟感知放置
公开(公告)号：US07624366B2
公开(公告)日：2009-11-24
申请号：US11554637
申请日：2006-10-31
申请人： Charles J. Alpert , David J. Hathaway , William R. Migatz , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia
发明人： Charles J. Alpert , David J. Hathaway , William R. Migatz , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： The layout of latches in a common clock domain is efficiently optimized to shrink the physical size of the domain while maintaining timing requirements. The latches are placed in a first layout preferably using quadratic placement, and a star object is built representing an interim clock structure. The latches are weighted based on wire distance from a source of the star object, and then re-placed using the weighting. The weighted placement and repartitioning may be iteratively repeated until a target number of bins is reached. The boundary of the latches in the final global placement is used to define a movebound for further detailed placement.
摘要翻译：锁存器在公共时钟域中的布局被有效优化，以缩小域的物理大小，同时保持时序要求。锁存器优选地使用二次放置放置在第一布局中，并且构建代表中间时钟结构的星形物体。锁存器根据与星形物体源的线距离进行加权，然后使用加权重新放置。可以迭代地重复加权放置和重新分配，直到达到目标数量的箱。最终全局放置中的锁存器的边界用于定义移动以进一步详细放置。

29. 发明申请

US20080127018A1 Clock Aware Placement 失效
标题翻译：时钟感知放置
公开(公告)号：US20080127018A1
公开(公告)日：2008-05-29
申请号：US11554637
申请日：2006-10-31
申请人： Charles J. Alpert , David J. Hathaway , William R. Migatz , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia
发明人： Charles J. Alpert , David J. Hathaway , William R. Migatz , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： The layout of latches in a common clock domain is efficiently optimized to shrink the physical size of the domain while maintaining timing requirements. The latches are placed in a first layout preferably using quadratic placement, and a star object is built representing an interim clock structure. The latches are weighted based on wire distance from a source of the star object, and then re-placed using the weighting. The weighted placement and repartitioning may be iteratively repeated until a target number of bins is reached. The boundary of the latches in the final global placement is used to define a movebound for further detailed placement.
摘要翻译：锁存器在公共时钟域中的布局被有效优化，以缩小域的物理大小，同时保持时序要求。锁存器优选地使用二次放置放置在第一布局中，并且构建代表中间时钟结构的星形物体。锁存器根据与星形物体源的线距离进行加权，然后使用加权重新放置。可以迭代地重复加权放置和重新分配，直到达到目标数量的箱。最终全局放置中的锁存器的边界用于定义移动以进一步详细放置。

30. 发明申请

US20070283301A1 System and Method of Eliminating Electrical Violations 审中-公开
标题翻译：消除电气违规的制度和方法
公开(公告)号：US20070283301A1
公开(公告)日：2007-12-06
申请号：US11422174
申请日：2006-06-05
申请人： Arvind K. Karandikar , Charles J. Alpert , Mehmet C. Yildiz , Stephen T. Quay , Tuhin Mahmud , Paul G. Villarrubia
发明人： Arvind K. Karandikar , Charles J. Alpert , Mehmet C. Yildiz , Stephen T. Quay , Tuhin Mahmud , Paul G. Villarrubia
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5081 , G06F17/5045
摘要： A system and method for correcting electrical violations, the method including examining a plurality of nets for at least one electrical violation in a sequential order of a first output-to-input traversal, and determining a net correction in each net of the plurality of nets having an electrical violation prior to examining a next net in the sequential order of the first output-to-input traversal.
摘要翻译：一种用于校正电气违规的系统和方法，所述方法包括以第一输出到输入遍历的顺序检查多个网络中的至少一个电气违规，以及确定多个网络的每个网络中的净校正在按照第一输出到输入遍历的顺序检查下一个网络之前具有电气违规。

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