专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20140372821A1 Scan Chain Stitching For Test-Per-Clock 审中-公开
标题翻译：扫描链拼接为每个时钟测试
公开(公告)号：US20140372821A1
公开(公告)日：2014-12-18
申请号：US13920004
申请日：2013-06-17
申请人： Mentor Graphics Corporation
发明人： Janusz Rajski , Jedrzej Solecki , Jerzy Tyszer , Grzegorz Mrugalski
IPC分类号： G01R31/3177
CPC分类号： G01R31/318575 , G01R31/318547
摘要： Various aspects of the present invention relate to scan chain stitching techniques for test-per-clock. With various implementations of the invention, a plurality of scan cell partitions are generated based on combinational paths between scan cells. Scan cells may be assigned to one or more pairs of scan cell partitions based on combinational paths between the scan cells. Each pair of the scan cell partitions comprises one stimuli partition and one compacting partition. Using the plurality of scan cell partitions generated, scan chains are formed based on at least information of combinational paths between scan cell partitions in the plurality of scan cell partitions. The formed scan chains are to be dynamically divided into three groups during a test, which are configured to operate in a shifting-launching mode, a capturing-compacting-shifting mode and a mission mode, respectively.
摘要翻译：本发明的各个方面涉及用于每个时钟测试的扫描链拼接技术。通过本发明的各种实现，基于扫描单元之间的组合路径生成多个扫描单元分区。可以基于扫描单元之间的组合路径将扫描单元分配给一对或多对扫描单元分区。每对扫描单元分区包括一个刺激分区和一个压缩分区。使用生成的多个扫描单元分区，至少基于多个扫描单元分区中的扫描单元分区之间的组合路径的信息形成扫描链。所形成的扫描链在测试期间被动态分为三组，分别被配置为以移动发射模式，捕获 - 压缩移动模式和任务模式操作。

22. 发明申请

US20140372820A1 Fault-Driven Scan Chain Configuration For Test-Per-Clock 有权
标题翻译：故障驱动的扫描链配置用于每个时钟测试
公开(公告)号：US20140372820A1
公开(公告)日：2014-12-18
申请号：US13919998
申请日：2013-06-17
申请人： Mentor Graphics Corporation
发明人： Janusz Rajski , Jedrzej Solecki , Jerzy Tyszer , Grzegorz Mrugalski
IPC分类号： G01R31/3177
CPC分类号： G01R31/3177 , G01R31/318536 , G01R31/318544 , G01R31/318575
摘要： Aspects of the invention relate to using fault-driven techniques to generate scan chain configurations for test-per-clock. A plurality of test cubes that detect a plurality of faults are first generated. Scan chains for loading specified bits of the test cubes are then assigned to a stimuli group. From the plurality of test cubes, a test cube that detects a large number of faults that do not propagate exclusively to scan chains in the stimuli group is selected. One or more scan chains that are not in the stimuli group and are needed for observing the large number of faults are assigned to a compacting group. The number of scan chains either in the compacting group or in both of the compacting group and the stimuli group may be limited to a predetermined number.
摘要翻译：本发明的方面涉及使用故障驱动技术来产生用于每个时钟测试的扫描链配置。首先生成检测多个故障的多个测试立方体。然后将用于加载测试立方体的指定位的扫描链分配给刺激组。从多个测试立方体中，选择检测大量不排斥到刺激组中的扫描链的故障的测试立方体。一个或多个不在刺激组中并且用于观察大量故障所需的扫描链被分配给压实组。压实组中或在压实组和刺激组中的扫描链的数量可以被限制为预定数量。

23. 发明申请

US20140229779A1 SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST 有权
标题翻译：用于系统级测试的扫描链的选择性周期性掩蔽
公开(公告)号：US20140229779A1
公开(公告)日：2014-08-14
申请号：US14257918
申请日：2014-04-21
申请人： Mentor Graphics Corporation
发明人： Janusz Rajski , Dariusz Czysz , Grzegorz Mrugalski , Nilanjan Mukherjee , Jerzy Tyszer
IPC分类号： G01R31/3177
CPC分类号： G01R31/31703 , G01R31/31723 , G01R31/31724 , G01R31/3177 , G01R31/318547 , G06F11/27
摘要： Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon.
摘要翻译：用于处理未知状态问题的集成电路的内置自检技术。一些实现使用与时间压缩器相连的专用扫描链选择器。专门的扫描链选择器的存在提高了掩蔽X状态的效率。还公开了：（1）与多个扫描链和时间压实器一起工作的选择器的架构，（2）用于确定和编码随后抑制X状态的每个周期扫描链选择掩模的方法，以及（3）以处理过度掩蔽现象。

24. 发明申请

US20210018563A1 FLEXIBLE ISOMETRIC DECOMPRESSOR ARCHITECTURE FOR TEST COMPRESSION 有权
公开(公告)号：US20210018563A1
公开(公告)日：2021-01-21
申请号：US16982299
申请日：2019-03-21
申请人： Mentor Graphics Corporation
发明人： Janusz Rajski , Yu Huang , Sylwester Milewski , Jerzy Tyszer
IPC分类号： G01R31/3185 , G01R31/3181
摘要： A system for testing a circuit comprises scan chains, a controller, and hold-toggle circuitry. The hold-toggle circuitry is configured to allow, according to a control signal generated by the controller, some scan chains in the scan chains to operate in a full-toggle mode and some other scan chains in the scan chains to operate in a hold-toggle mode when a test pattern is being shifted into the scan chains. The control signal also contains information of a hold-toggle pattern for the scan chains operating in the hold-toggle mode. The hold-toggle pattern repeats multiple times when the test pattern is being shifted into the scan chains.

25. 发明授权

US10509072B2 Test application time reduction using capture-per-cycle test points 有权
公开(公告)号：US10509072B2
公开(公告)日：2019-12-17
申请号：US15884369
申请日：2018-01-30
申请人： Mentor Graphics Corporation
发明人： Janusz Rajski , Sylwester Milewski , Nilanjan Mukherjee , Jedrzej Solecki , Jerzy Tyszer , Justyna Zawada
IPC分类号： G01R31/3177 , G01R31/317 , G01R31/3185
摘要： Various aspects of the disclosed technology relate to using capture-per-cycle test points to reduce test application time. A scan-based testing system includes a plurality of regular scan chains and one or more capture-per-cycle scan chains on which scan cells capture and compact test responses at predetermined observation points per shift clock cycle.

26. 发明申请

US20180252768A1 Test Application Time Reduction Using Capture-Per-Cycle Test Points 审中-公开
公开(公告)号：US20180252768A1
公开(公告)日：2018-09-06
申请号：US15884369
申请日：2018-01-30
申请人： Mentor Graphics Corporation
发明人： Janusz Rajski , Sylwester Milewski , Nilanjan Mukherjee , Jedrzej Solecki , Jerzy Tyszer , Justyna Zawada
IPC分类号： G01R31/3177 , G01R31/317
CPC分类号： G01R31/3177 , G01R31/31724 , G01R31/31727 , G01R31/318538 , G01R31/318547 , G01R31/318563
摘要： Various aspects of the disclosed technology relate to using capture-per-cycle test points to reduce test application time. A scan-based testing system includes a plurality of regular scan chains and one or more capture-per-cycle scan chains on which scan cells capture and compact test responses at predetermined observation points per shift clock cycle.

27. 发明申请

US20180017622A1 CONTINUOUS APPLICATION AND DECOMPRESSION OF TEST PATTERNS AND SELECTIVE COMPACTION OF TEST RESPONSES 审中-公开
公开(公告)号：US20180017622A1
公开(公告)日：2018-01-18
申请号：US15608716
申请日：2017-05-30
申请人： Mentor Graphics Corporation
发明人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
IPC分类号： G01R31/3183 , G01R31/3185
CPC分类号： G01R31/318385 , G01R31/318547
摘要： A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.

28. 发明申请

US20160252573A1 TEST-PER-CLOCK BASED ON DYNAMICALLY-PARTITIONED RECONFIGURABLE SCAN CHAINS 有权
标题翻译：基于动态分布式可重构扫描链的测试周期
公开(公告)号：US20160252573A1
公开(公告)日：2016-09-01
申请号：US15150147
申请日：2016-05-09
申请人： Mentor Graphics Corporation
发明人： Janusz Rajski , Jedrzej Solecki , Jerzy Tyszer , Grzegorz Mrugalski
IPC分类号： G01R31/3177 , G01R31/317
CPC分类号： G01R31/318555 , G01R31/31704 , G01R31/3177 , G01R31/318544 , G01R31/318547 , G01R31/318575
摘要： Aspects of the invention relate to a test-per-clock scheme based on dynamically-partitioned reconfigurable scan chains. Every clock cycle, scan chains configured by a control signal to operate in a shifting-launching mode shift in test stimuli one bit and immediately applies the newly formed test pattern to the circuit-under-test; and scan chains configured by the control signal to operate in a capturing-compacting-shifting mode shift out one bit of previously compacted test response data while compacting remaining bits of the previously compacted test response data with a currently-captured test response to form currently compacted test response data. A large number of scan chains may be configured by the control signal to work in a mission mode. After a predetermined number of clock cycles, a different control signal may be applied to reconfigure and partition the scan chains for applying different test stimuli.
摘要翻译：本发明的方面涉及基于动态分配的可重构扫描链的基于每时钟的测试方案。每个时钟周期，由控制信号配置的扫描链在移位启动模式下运行，测试刺激一位移位，并立即将新形成的测试模式应用于待测电路; 以及由控制信号配置的扫描链，以捕捉 - 压缩 - 移位模式运行，移除先前压缩的一个测试响应数据，同时用当前捕获的测试响应压缩先前压缩的测试响应数据的剩余位以形成当前压缩测试响应数据。可以通过控制信号来配置大量扫描链，以在任务模式下工作。在预定数量的时钟周期之后，可以应用不同的控制信号来重新配置和划分扫描链以施加不同的测试刺激。

29. 发明申请

US20140372819A1 Scan Chain Configuration For Test-Per-Clock Based On Circuit Topology 有权
标题翻译：基于电路拓扑的每个时钟测试的扫描链配置
公开(公告)号：US20140372819A1
公开(公告)日：2014-12-18
申请号：US13919991
申请日：2013-06-17
申请人： Mentor Graphics Corporation
发明人： Janusz Rajski , Jedrzej Solecki , Jerzy Tyszer , Grzegorz Mrugalski
IPC分类号： G01R31/3177
CPC分类号： G01R31/3177 , G01R31/318547 , G01R31/318563 , G01R31/318583
摘要： Aspects of the invention relate to generating scan chain configurations for test-per-clock based on circuit topology. With various implementations of the invention, weight vectors between scan chains in a circuit are first determined. Based on the weight vectors, a scan chain configuration is generated by assigning some scan chains in the scan chains to a stimuli group and some other scan chains in the scan chains to a compacting group. Here, the stimuli group comprises scan chains to operate in a shifting-launching mode, and the compacting group comprises scan chains to operate in a capturing-compacting-shifting mode.
摘要翻译：本发明的方面涉及基于电路拓扑生成针对每个时钟测试的扫描链配置。利用本发明的各种实施方式，首先确定电路中扫描链之间的权重向量。基于权重向量，通过将扫描链中的一些扫描链分配给扫描链中的刺激组和一些其它扫描链到生成组来生成扫描链配置。这里，刺激组包括以移动发射模式操作的扫描链，并且压实组包括扫描链以在捕获 - 压缩移动模式下操作。

30. 发明授权

US08914694B2 On-chip comparison and response collection tools and techniques 有权
标题翻译：片上比较和响应收集工具和技术
公开(公告)号：US08914694B2
公开(公告)日：2014-12-16
申请号：US13858737
申请日：2013-04-08
申请人： Mentor Graphics Corporation
发明人： Nilanjan Mukherjee , Janusz Rajski , Jerzy Tyszer
IPC分类号： G01R31/28 , G01R31/3185 , G01R31/3177
CPC分类号： G01R31/3177 , G01R31/2851 , G01R31/31723 , G01R31/31727 , G01R31/318547 , G01R31/318563 , G01R31/318566
摘要： Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.
摘要翻译：这里公开了所谓的“X-press”测试响应压实机的示例性实施例。所公开的压实机的某些实施例包括过驱动部分和扫描链选择逻辑。所公开技术的某些实施例提供大约1000×的压实比。所公开的压实机的示例性实施例可以保持与传统的基于扫描的测试场景相同的覆盖范围和大约相同的诊断分辨率。扫描链选择方案的一些实施例可以显着地减少或完全消除在进入压实机的测试响应中发生的未知状态。本文还公开了片上比较器电路和用于产生用于屏蔽选择电路的控制电路的方法的实施例。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式