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21. 发明授权

US06165891A Damascene structure with reduced capacitance using a carbon nitride, boron nitride, or boron carbon nitride passivation layer, etch stop layer, and/or cap layer 有权
标题翻译：使用碳氮化物，氮化硼或氮化硼钝化层，蚀刻停止层和/或覆盖层的具有降低的电容的镶嵌结构
公开(公告)号：US06165891A
公开(公告)日：2000-12-26
申请号：US435434
申请日：1999-11-22
申请人： Simon Chooi , Yi Xu , Mei Sheng Zhou
发明人： Simon Chooi , Yi Xu , Mei Sheng Zhou
IPC分类号： H01L21/311 , H01L21/318 , H01L21/768 , H01L23/522 , H01L23/532 , H01L21/4763 , G03C5/00 , H01L21/302 , H01L23/48
CPC分类号： H01L21/76835 , H01L21/31122 , H01L21/318 , H01L21/76802 , H01L21/76807 , H01L21/76829 , H01L21/76834 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for forming a damascene structure with reduced capacitance by forming one or more of: the passivation layer, the etch stop layer, and the cap layer using a low dielectric constant material comprising carbon nitride, boron nitride, or boron carbon nitride. The method begins by providing a semiconductor structure having a first conductive layer thereover. A passivation layer is formed on the first conductive layer. A first dielectric layer is formed over the passivation layer, and an etch stop layer is formed over the first dielectric layer. A second dielectric layer is formed over the etch stop layer, and an optional cap layer can be formed over the second dielectric layer. The cap layer, the second dielectric layer, the etch stop layer, and the first dielectric layer are patterned to form a via opening stopping on said passivation layer and a trench opening stopping on the first conductive layer. A carbon nitride passivation layer, etch stop layer, or cap layer can be formed by magnetron sputtering from a graphite target in a nitrogen atmosphere. A boron nitride passivation layer, etch stop layer, or cap layer can be formed by PECVD using B.sub.2 H.sub.6, ammonia, and nitrogen. A boron carbon nitride passivatation layer, etch stop layer, or cap layer can be formed by magnetron sputtering from a graphite target in a nitrogen and B.sub.2 H.sub.6 atmosphere.
摘要翻译：通过使用包含碳氮化物，氮化硼或碳氮化硼的低介电常数材料通过形成钝化层，蚀刻停止层和盖层中的一个或多个来形成具有降低的电容的镶嵌结构的方法和结构。该方法开始于提供其上具有第一导电层的半导体结构。在第一导电层上形成钝化层。第一电介质层形成在钝化层之上，并且在第一介电层上形成蚀刻停止层。第二介电层形成在蚀刻停止层上方，并且可以在第二介电层上形成任选的盖层。图案化盖层，第二电介质层，蚀刻停止层和第一介电层，以形成在所述钝化层上停止的通孔开口和在第一导电层上停止的沟槽开口。碳氮化物钝化层，蚀刻停止层或盖层可以通过在氮气气氛中的石墨靶磁控溅射来形成。可以通过使用B2H6，氨和氮的PECVD形成氮化硼钝化层，蚀刻停止层或盖层。硼氮化物钝化层，蚀刻停止层或盖层可以通过在氮气和B2H6气氛中的石墨靶的磁控溅射形成。

22. 发明授权

US5795699A Langmuir-blodgett (LB) films as ARC and adhesion promoters for patterning of semiconductor devices 失效
标题翻译： Langmuir-blodgett（LB）膜作为ARC和用于图案化半导体器件的粘合促进剂
公开(公告)号：US5795699A
公开(公告)日：1998-08-18
申请号：US679858
申请日：1996-07-15
申请人： Mei Sheng Zhou , Ron-Fu Chu
发明人： Mei Sheng Zhou , Ron-Fu Chu
IPC分类号： G03F7/09 , G03F7/16 , G03C5/00
CPC分类号： G03F7/091 , G03F7/165 , Y10S438/939
摘要： A method for forming upon a reflective layer, such as a reflective conducting layer, within an integrated circuit an Anti-Reflective Coating (ARC) which simultaneously possesses adhesion promotion characteristics for an organic layer to be formed upon the reflective layer. There is first formed upon a semiconductor wafer a reflective integrated circuit layer which may be a hydrophilic reflective integrated circuit layer or a hydrophobic integrated circuit layer. The semiconductor wafer is then immersed into and withdrawn from a Langmuir trough having formed therein a Langmuir-Blodgett (LB) monolayer film of a dye surfactant molecule ordered upon a surface of water. Upon withdrawing the wafer from the Langmuir trough, there is formed upon the reflective integrated circuit layer an ordered LB film of the dye surfactant molecule. The chromophore groups within the dye surfactant molecule and ordered LB film provide ARC characteristics to the reflective layer.
摘要翻译：一种用于在集成电路内的反射层（例如反射导电层）上形成抗反射涂层（ARC）的方法，该抗反射涂层同时具有将在反射层上形成的有机层的粘附促进特性。首先在半导体晶片上形成反射集成电路层，反射集成电路层可以是亲水反射集成电路层或疏水性集成电路层。然后将半导体晶片浸入Langmuir槽中并从Langmuir槽中取出，Langmuir槽中形成了在水表面上排列的染料表面活性剂分子的Langmuir-Blodgett（LB）单层膜。当从Langmuir槽中取出晶片时，在反射集成电路层上形成染料表面活性剂分子的有序LB膜。染料表面活性剂分子内的发色团和有序的LB膜为反射层提供ARC特性。

23. 发明授权

US08546873B2 Integrated circuit and method of fabrication thereof 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US08546873B2
公开(公告)日：2013-10-01
申请号：US13241215
申请日：2011-09-23
申请人： Jinping Liu , Hai Cong , Binbin Zhou , Alex Kh See , Mei Sheng Zhou , Liang Choo Hsia
发明人： Jinping Liu , Hai Cong , Binbin Zhou , Alex Kh See , Mei Sheng Zhou , Liang Choo Hsia
IPC分类号： H01L29/66
CPC分类号： H01L21/823468 , H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/165 , H01L29/66636 , H01L29/7848
摘要： A method of forming an integrated circuit structure comprising the steps of forming a first and second device region on a surface of a wafer, forming a spacer of a first width on a sidewall of a first gate stack in the first device region, forming a spacer of a second width on a sidewall of a second gate stack in the second device region, with the first width being different from the second width.
摘要翻译：一种形成集成电路结构的方法，包括以下步骤：在晶片的表面上形成第一和第二器件区域，在第一器件区域中的第一栅极堆叠的侧壁上形成第一宽度的间隔物，形成间隔物在第二装置区域中的第二栅极堆叠的侧壁上具有第二宽度，第一宽度不同于第二宽度。

24. 发明授权

US08058123B2 Integrated circuit and method of fabrication thereof 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US08058123B2
公开(公告)日：2011-11-15
申请号：US11946843
申请日：2007-11-29
申请人： Jinping Liu , Hai Cong , Binbin Zhou , Alex K H See , Mei Sheng Zhou , Liang Choo Hsia
发明人： Jinping Liu , Hai Cong , Binbin Zhou , Alex K H See , Mei Sheng Zhou , Liang Choo Hsia
IPC分类号： H01L21/8238
CPC分类号： H01L21/823468 , H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/165 , H01L29/66636 , H01L29/7848
摘要： A method of forming an integrated circuit structure comprising the steps of forming a first and second device region on a surface of a wafer, forming a spacer of a first width on a sidewall of a first gate stack in the first device region, forming a spacer of a second width on a sidewall of a second gate stack in the second device region, with the first width being different from the second width.
摘要翻译：一种形成集成电路结构的方法，包括以下步骤：在晶片的表面上形成第一和第二器件区域，在第一器件区域中的第一栅极堆叠的侧壁上形成第一宽度的间隔物，形成间隔物在第二装置区域中的第二栅极堆叠的侧壁上具有第二宽度，第一宽度不同于第二宽度。

25. 发明授权

US07902066B2 Damascene contact structure for integrated circuits 有权
标题翻译：集成电路的镶嵌接触结构
公开(公告)号：US07902066B2
公开(公告)日：2011-03-08
申请号：US11535069
申请日：2006-09-26
申请人： Jian Hui Ye , Mei Sheng Zhou
发明人： Jian Hui Ye , Mei Sheng Zhou
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/31144 , H01L21/76846 , H01L21/76895 , H01L21/76897 , H01L23/485 , H01L23/53238
摘要： Interconnects for integrated circuits, such as damascene structures are formed using a hard mask. The hard mask is formed from, for example, high-k dielectric material such as hafnium oxide or other materials having high etch selectivity to the interconnect dielectric material. This enables a thin mask to etch vias and trenches in the interconnect dielectric layer, avoiding the problems associated with the use of thick mask layers, such as contact hole striations and small depth of focus, which can result in shorts or opens.
摘要翻译：集成电路的互连（如镶嵌结构）使用硬掩模形成。硬掩模由例如高k电介质材料形成，例如氧化铪或对互连电介质材料具有高蚀刻选择性的其它材料。这使得薄掩模能够蚀刻互连电介质层中的通孔和沟槽，从而避免与使用厚掩模层（例如接触孔条纹和小焦点深度）相关联的问题，这可能导致短路或打开。

26. 发明授权

US07745320B2 Method for reducing silicide defects in integrated circuits 有权
标题翻译：降低集成电路中硅化物缺陷的方法
公开(公告)号：US07745320B2
公开(公告)日：2010-06-29
申请号：US12124177
申请日：2008-05-21
申请人： Jeff Jianhui Ye , Huang Liu , Alex K H See , Wei Lu , Hai Cong , Hui Peng Koh , Mei Sheng Zhou , Liang Choo Hsia
发明人： Jeff Jianhui Ye , Huang Liu , Alex K H See , Wei Lu , Hai Cong , Hui Peng Koh , Mei Sheng Zhou , Liang Choo Hsia
IPC分类号： H01L29/00 , H01L21/311
CPC分类号： H01L29/665 , H01L21/31116 , H01L29/6653 , H01L29/78
摘要： A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the occurrence of silicide pipe defects. The spacer pull-back etch can be performed after a first annealing step to form the silicide contacts.
摘要翻译：描述了在集成电路（IC）中形成硅化物触点的方法。在水解过程期间进行间隔物拉回蚀刻以减少间隔物与间隔物底切下的源/漏硅化物接触之间的应力。这样可以防止表面缺陷进入衬底，从而使硅化物管缺陷的发生最小化。间隔物拉回蚀刻可以在第一退火步骤之后进行以形成硅化物接触。

27. 发明申请

US20100096695A1 HIGH STRESS FILM 审中-公开
标题翻译：高应力膜
公开(公告)号：US20100096695A1
公开(公告)日：2010-04-22
申请号：US12252368
申请日：2008-10-16
申请人： Han Guan Chew , Jinping Liu , Alex Kh See , Mei Sheng Zhou
发明人： Han Guan Chew , Jinping Liu , Alex Kh See , Mei Sheng Zhou
IPC分类号： H01L47/00 , H01L21/336
CPC分类号： H01L29/4966 , H01L21/31155 , H01L29/7843 , H01L29/7846 , H01L29/7849
摘要： A semiconductor device that includes a substrate having an active region prepared with a transistor is presented. The semiconductor device includes a stress structure adjacent to the substrate. The stress structure includes a dielectric layer having nanocrystals embedded therein. The nanocrystals induce a first or a second stress on a channel region of the transistor which improves carrier mobility of the transistor.
摘要翻译：提出了一种包括具有由晶体管制备的有源区的衬底的半导体器件。半导体器件包括与衬底相邻的应力结构。应力结构包括其中嵌有纳米晶体的电介质层。纳米晶体在晶体管的沟道区域上引起第一或第二应力，这改善了晶体管的载流子迁移率。

28. 发明授权

US07071281B2 Poly(arylene ether) dielectrics 失效
标题翻译：聚（亚芳基醚）电介质
公开(公告)号：US07071281B2
公开(公告)日：2006-07-04
申请号：US11028773
申请日：2005-01-04
申请人： Christopher Lim , Siu Choon Ng , Hardy Chan , Simon Chooi , Mei Sheng Zhou
发明人： Christopher Lim , Siu Choon Ng , Hardy Chan , Simon Chooi , Mei Sheng Zhou
IPC分类号： C08G65/00
CPC分类号： C08G65/40 , C08G65/4006 , Y10T428/17 , Y10T428/31678
摘要： The present invention relates to poly(arylene ethers) used as low k dielectric layers in electronic applications and articles containing such poly(arylene ethers) comprising the structure: wherein n=5 to 10000 and monovalent Ar1 and divalent Ar2 are selected from a group of heteroaromatic compounds that incorporate O, N, Se, S, or Te or combinations of the aforesaid elements, including but not limited to:
摘要翻译：本发明涉及在电子应用中用作低k电介质层的聚（亚芳基醚）和含有这种聚（亚芳基醚）的制品，其包含以下结构：其中n = 5至10000和一价Ar 1和二价Ar 2 H 2选自一组包含O，N，Se，S或Te的杂芳族化合物或上述组分的组合，包括但不限于：

29. 发明授权

US06846899B2 Poly(arylene ether) dielectrics 失效
标题翻译：聚（亚芳基醚）电介质
公开(公告)号：US06846899B2
公开(公告)日：2005-01-25
申请号：US10262144
申请日：2002-10-01
申请人： Christopher Lim , Siu Choon Ng , Hardy Chan , Simon Chooi , Mei Sheng Zhou
发明人： Christopher Lim , Siu Choon Ng , Hardy Chan , Simon Chooi , Mei Sheng Zhou
IPC分类号： C08G65/40 , H01L21/312 , H01L21/768 , C08G65/00
CPC分类号： C08G65/40 , C08G65/4006 , Y10T428/17 , Y10T428/31678
摘要： The present invention relates to poly(arylene ethers) used as low k dielectric layers in electronic applications and articles containing such poly(arylene ethers) comprising the structure: wherein n=5 to 10000 and monovalent Ar1 and divalent Ar2 are selected from a group of heteroaromatic compounds that incorporate O, N, Se, S, or Te or combinations of the aforesaid elements, including but not limited to:
摘要翻译：本发明涉及在电子应用中用作低k电介质层的聚（亚芳基醚）和含有这种聚（亚芳基醚）的制品，其包含以下结构：其中n = 5至10000，一价Ar 1和二价Ar 2选自包含O，N，Se，S或Te的杂芳族化合物或上述元素的组合，包括但不限于：

30. 发明授权

US06813796B2 Apparatus and methods to clean copper contamination on wafer edge 失效
标题翻译：清洁晶圆边缘铜污染的设备和方法
公开(公告)号：US06813796B2
公开(公告)日：2004-11-09
申请号：US10357137
申请日：2003-02-03
申请人： Sudipto Ranendra Roy , Subhash Gupta , Simon Chooi , Xu Yi , Yakub Aliyu , Mei Sheng Zhou , John Leonard Sudijono , Paul Kwok Keung Ho
发明人： Sudipto Ranendra Roy , Subhash Gupta , Simon Chooi , Xu Yi , Yakub Aliyu , Mei Sheng Zhou , John Leonard Sudijono , Paul Kwok Keung Ho
IPC分类号： B08B700
CPC分类号： B08B1/04 , B08B3/04
摘要： A new apparatus is provided that can be applied to clean outer edges of semiconductor substrates. Under the first embodiment of the invention, a brush is mounted on the surface of the substrate around the periphery of the substrate, chemicals are fed to the surface that is being cleaned by means of a hollow core on which the cleaning brush is mounted. The surface that is being cleaned rotates at a relatively high speed thereby causing the chemicals that are deposited on this surface (by the brush) to remain in the edge of the surface. Under the second embodiment of the invention, a porous roller is mounted between a chemical reservoir and the surface that is being cleaned, the surface that is being cleaned rotates at a relatively high speed. The chemicals that are deposited by the interfacing porous roller onto the surface that is being cleaned therefore remain at the edge of this surface thereby causing optimum cleaning action of the edge of the surface. After contaminants have been removed in this manner from the surface, the surface can be further cleaned by applying DI water.
摘要翻译：提供了可用于清洁半导体衬底的外边缘的新设备。在本发明的第一实施例中，刷子安装在基板周围的基板的表面上，化学品通过其上安装有清洁刷的中空芯被供给到被清洁的表面。待清洁的表面以相对高的速度旋转，从而使沉积在该表面（由刷子）上的化学物质残留在表面的边缘。在本发明的第二实施例中，多孔辊安装在化学容器和待清洁的表面之间，待清洁的表面以相对较高的速度旋转。因此，由界面多孔辊沉积在待清洗的表面上的化学物质保留在该表面的边缘，从而引起表面边缘的最佳清洁作用。污染物以这种方式从表面除去后，可以通过加入去离子水进一步清洁表面。

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