专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US07684970B2 Graphical user interface for use during processor simulation 失效
标题翻译：在处理器模拟期间使用的图形用户界面
公开(公告)号：US07684970B2
公开(公告)日：2010-03-23
申请号：US10877922
申请日：2004-06-25
申请人： Donald F. Hooper , Eric Walker , Dennis Rivard , Mark B. Rosenbluth
发明人： Donald F. Hooper , Eric Walker , Dennis Rivard , Mark B. Rosenbluth
IPC分类号： G06F9/44 , G06F3/00
CPC分类号： G06F11/3664 , G06F11/3636
摘要： In accordance with one exemplary embodiment, the present disclosure includes a method for executing application software during a simulation that models a processor for which the application software was developed. The method may include capturing results of the simulation to produce a simulation history. The method may also include providing a graphical user interface (GUI) that includes one or more cross-linked packet-centric views of the simulation history for packets operated on by the application software during the simulation. The cross-linked packet-centric views may include a packet status list GUI, a packet event list GUI, a packet dataflow GUI, a thread list GUI, and a thread history GUI. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：根据一个示例性实施例，本公开包括一种用于在仿真期间执行应用软件的方法，其对开发应用软件的处理器进行建模。该方法可以包括捕获模拟的结果以产生模拟历史。该方法还可以包括提供图形用户界面（GUI），其包括在模拟期间由应用软件操作的分组的模拟历史的一个或多个以交叉分组为中心的视图。以交叉分组为中心的视图可以包括分组状态列表GUI，分组事件列表GUI，分组数据流GUI，线程列表GUI和线程历史GUI。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

22. 发明授权

US07555630B2 Method and apparatus to provide efficient communication between multi-threaded processing elements in a processor unit 失效
标题翻译：用于在处理器单元中的多线程处理元件之间提供有效通信的方法和装置
公开(公告)号：US07555630B2
公开(公告)日：2009-06-30
申请号：US11018579
申请日：2004-12-21
申请人： Sanjeev Jain , Gilbert M. Wolrich , Mark B. Rosenbluth
发明人： Sanjeev Jain , Gilbert M. Wolrich , Mark B. Rosenbluth
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F13/4252
摘要： A context forwarding bus efficiently communicates control and data between processing elements in a processor unit having a plurality of processing elements. Control and data information is transferred over a first bus from processing element to processing element.
摘要翻译：上下文转发总线在具有多个处理元件的处理器单元中有效地传送处理元件之间的控制和数据。控制和数据信息通过第一总线从处理元件传送到处理元件。

23. 发明授权

US07554908B2 Techniques to manage flow control 有权
标题翻译：管理流量控制的技术
公开(公告)号：US07554908B2
公开(公告)日：2009-06-30
申请号：US11009861
申请日：2004-12-10
申请人： Sanjeev Jain , Mark B. Rosenbluth , Gilbert Wolrich , Hugh M. Wilkinson
发明人： Sanjeev Jain , Mark B. Rosenbluth , Gilbert Wolrich , Hugh M. Wilkinson
IPC分类号： G06F11/00 , H04J3/14 , H04L12/26
CPC分类号： H04L47/10 , H04L49/15 , H04L49/254 , H04L49/30 , H04L2012/5678
摘要： Method and apparatus to manage flow control for a network device are described.
摘要翻译：描述了一种用于管理网络设备的流量控制的方法和装置。

24. 发明授权

US07443836B2 Processing a data packet 有权
标题翻译：处理数据包
公开(公告)号：US07443836B2
公开(公告)日：2008-10-28
申请号：US10463217
申请日：2003-06-16
申请人： Donald F. Hooper , Mark B. Rosenbluth , Gilbert Wolrich , Matthew J. Adiletta , Hugh M. Wilkinson, III , Robert J. Kushlis
发明人： Donald F. Hooper , Mark B. Rosenbluth , Gilbert Wolrich , Matthew J. Adiletta , Hugh M. Wilkinson, III , Robert J. Kushlis
IPC分类号： H04L12/66
CPC分类号： G06F9/3851 , H04L49/90 , H04L49/901 , H04L49/9031 , H04L49/9057 , H04L49/9094
摘要： A device and method for processing a data packet at a device are described. The device receives data packets and determines available memory in one or more of local memories of a plurality of execution threads. The device stores packet information in an available one of the local memories of the execution threads.
摘要翻译：描述用于在设备处理数据分组的设备和方法。设备接收数据分组并且确定多个执行线程的一个或多个本地存储器中的可用存储器。该设备将分组信息存储在执行线程的本地存储器中的可用的一个中。

25. 发明授权

US07412584B2 Data alignment micro-architecture systems and methods 失效
标题翻译：数据对齐微架构系统和方法
公开(公告)号：US07412584B2
公开(公告)日：2008-08-12
申请号：US10838078
申请日：2004-05-03
申请人： Jose S. Niell , Gilbert M. Wolrich , Thomas L. Dmukauskas , Mark B. Rosenbluth
发明人： Jose S. Niell , Gilbert M. Wolrich , Thomas L. Dmukauskas , Mark B. Rosenbluth
IPC分类号： G06F12/00
CPC分类号： G06F9/3824 , G06F9/30043 , G06F9/3816 , G06F9/3842 , G06F12/04
摘要： Systems and methods are disclosed for aligning data in memory access and other applications. In one embodiment a system is provided that includes a memory unit, a shifter, and control logic operable to route data from the memory unit to the shifter and to send an indication to the shifter of an amount by which the data is to be shifted. In one embodiment, the control logic provides support for speculative execution. The control logic may also permit multiplexing of big endian and little endian data alignment operations, and/or multiplexing of data alignment operations with non-data alignment operations. In one embodiment, the memory unit, shifter, and control logic are integrated within a processing unit, such as a microengine in a network processor.
摘要翻译：公开了用于在存储器访问和其他应用中对准数据的系统和方法。在一个实施例中，提供了一种系统，其包括存储器单元，移位器和可操作以将数据从存储器单元路由到移位器的控制逻辑，并向移位器发送数据要被移位的量的指示。在一个实施例中，控制逻辑提供对推测执行的支持。控制逻辑还可以允许大端和小端数据对准操作的复用，和/或数据对准操作与非数据对准操作的复用。在一个实施例中，存储器单元，移位器和控制逻辑集成在处理单元内，诸如网络处理器中的微引擎。

26. 发明授权

US07313140B2 Method and apparatus to assemble data segments into full packets for efficient packet-based classification 有权
标题翻译：将数据段组合成完整分组的方法和装置，用于有效的基于分组的分类
公开(公告)号：US07313140B2
公开(公告)日：2007-12-25
申请号：US10188087
申请日：2002-07-03
申请人： Sridhar Lakshmanamurthy , Charles E. Narad , Lawrence B. Huston , Yim Pun , Raymond Ng , Debra Bernstein , Mark B. Rosenbluth
发明人： Sridhar Lakshmanamurthy , Charles E. Narad , Lawrence B. Huston , Yim Pun , Raymond Ng , Debra Bernstein , Mark B. Rosenbluth
IPC分类号： H04L12/28
CPC分类号： H04L49/9094 , H04L49/90 , H04L49/9047
摘要： A method may be used for assembling received data segments into full packets in an initial processing stage in a processor. The method may include receiving a plurality of data segments from a packet and determining a first storage location for each of the plurality of data segments. The method may further include storing each of the plurality of data segments in its determined first storage location and determining a second storage location for each of the plurality of data segments, the second storage locations being logically ordered to represent the order the data segments originally occurred in the packet. The method may also include storing each of the plurality of data segments in its determined second storage location to re-assemble the packet and releasing the first storage location associated with each data segment after storing the data segment in its determined second storage location. The method may additionally include, upon the storing of an end of packet data segment from the packet in its determined second storage location, passing control of the plurality of related data segments to a next processing stage in the processor.
摘要翻译：可以在处理器的初始处理阶段中使用一种方法将接收的数据段组装成全分组。该方法可以包括从分组接收多个数据段并且确定多个数据段中的每一个的第一存储位置。该方法还可以包括将多个数据段中的每一个存储在其确定的第一存储位置中，并且为多个数据段中的每一个确定第二存储位置，第二存储位置被逻辑地排序以表示数据段最初发生的顺序在包中。该方法还可以包括将多个数据段中的每一个存储在其确定的第二存储位置中以在将数据段存储在其确定的第二存储位置之后重新组合分组并释放与每个数据段相关联的第一存储位置。该方法可以另外包括在从分组在其确定的第二存储位置中存储分组数据段的结束时，将多个相关数据段的控制传递到处理器中的下一个处理阶段。

27. 发明申请

US20130132622A1 PCI EXPRESS ENHANCEMENTS AND EXTENSIONS 审中-公开
标题翻译： PCI EXPRESS增强和扩展
公开(公告)号：US20130132622A1
公开(公告)日：2013-05-23
申请号：US13713635
申请日：2012-12-13
申请人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
发明人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
IPC分类号： G06F13/42
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
摘要： A method and apparatus forenhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
摘要翻译：这里描述了诸如外围组件互连Express（PCIe）之类的串行点到点互连体系结构的增强/扩展的方法和装置。提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。包括有功功率子状态及其设置以允许更有效的电源管理。并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。

28. 发明申请

US20130111086A1 PCI EXPRESS ENHANCEMENTS AND EXTENSIONS 审中-公开
标题翻译： PCI EXPRESS增强和扩展
公开(公告)号：US20130111086A1
公开(公告)日：2013-05-02
申请号：US13691106
申请日：2012-11-30
申请人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
发明人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
IPC分类号： G06F13/38
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
摘要翻译：这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。包括有功功率子状态及其设置以允许更有效的电源管理。并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。

29. 发明申请

US20130097353A1 PCI EXPRESS ENHANCEMENTS AND EXTENSIONS 审中-公开
公开(公告)号：US20130097353A1
公开(公告)日：2013-04-18
申请号：US13706575
申请日：2012-12-06
申请人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
发明人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
IPC分类号： G06F13/40
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

30. 发明授权

US07689867B2 Multiprocessor breakpoint 失效
标题翻译：多处理器断点
公开(公告)号：US07689867B2
公开(公告)日：2010-03-30
申请号：US11148804
申请日：2005-06-09
申请人： Mark B. Rosenbluth , Xiao-Feng Li , Dz-ching (Roy) Ju , Aaron R. Kunze
发明人： Mark B. Rosenbluth , Xiao-Feng Li , Dz-ching (Roy) Ju , Aaron R. Kunze
IPC分类号： G06F11/00
CPC分类号： G06F11/3648
摘要： Techniques that may be utilized in a multiprocessor system are described. In one embodiment, one or more signals are generated to indicate that a breakpoint instruction is executed by one of the plurality of processors in the multiprocessor system. For example, a signal may be generated to indicate whether a processor is to be halted once it receives the a signal that indicates the breakpoint instruction. Other embodiments are also disclosed.
摘要翻译：描述可在多处理器系统中使用的技术。在一个实施例中，生成一个或多个信号以指示断点指令由多处理器系统中的多个处理器之一执行。例如，可以生成信号以指示一旦接收到指示断点指令的信号，处理器是否被停止。还公开了其他实施例。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式