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    • 21. 发明授权
    • Developer agitating system, electrophotographic image forming apparatus and cartridge
    • 显影搅拌系统,电子照相成像设备和墨盒
    • US06654566B1
    • 2003-11-25
    • US09585606
    • 2000-06-02
    • Seiji YamaguchiMasahide KinoshitaMotoki Adachi
    • Seiji YamaguchiMasahide KinoshitaMotoki Adachi
    • G03G1500
    • G03G21/1889G03G15/0822G03G2221/1823
    • A developer agitating system for agitating a developer includes a cartridge detachably mountable to a main body of an electrophotographic image forming apparatus and including a developing member for developing an electrostatic latent image formed on an electrophotographic photosensitive member, a developer container for containing the developer used for development of the electrostatic latent image by the developing member, an agitating member for agitating the developer contained in the developer container, and an informing member having information for indicating that the cartridge is a given cartridge, and a detector for detecting the information in the informing member when the cartridge is mounted to the main body of the electrophotographic image forming apparatus. As a result of detecting the information by the detector, if the cartridge is the given cartridge, a period of time of agitating the developer by the agitating member is made longer than that in a case where the cartridge is not the given cartridge.
    • 用于搅拌显影剂的显影剂搅拌系统包括可拆卸地安装到电子照相图像形成装置的主体的盒,并且包括用于显影形成在电子照相感光构件上的静电潜像的显影剂构件,用于容纳用于 通过显影构件显影静电潜像,用于搅拌包含在显影剂容器中的显影剂的搅拌构件以及具有用于指示盒是给定盒的信息的通知构件以及用于检测通知中的信息的检测器 当墨盒安装到电子照相图像形成装置的主体时。 作为检测器检测到信息的结果,如果盒是给定的盒,则搅拌部件搅拌显影剂的时间长于盒不是给定盒的情况。
    • 26. 发明授权
    • Microwave densitometer
    • 微波密度计
    • US5581191A
    • 1996-12-03
    • US524251
    • 1995-09-06
    • Seiji Yamaguchi
    • Seiji Yamaguchi
    • G01N9/24G01N22/00G01R27/04G01R27/32
    • G01N9/24G01N22/00
    • A microwave densitometer comprises a phase difference detecting section for detecting a phase difference between a microwave generated from a microwave generator and a microwave received by a microwave receiver, a rotation number updating section for varying a value of number of rotations "n", a correcting section for obtaining a difference value .DELTA..THETA. indicating a difference between a true phase difference .THETA..sub.2 and a reference phase difference .THETA..sub.1 ' a signal converter for converting the difference value .DELTA..THETA. to a concentration signal an operation mode setter for setting a operation mode, and a holding circuit for holding the number of rotations "n" and the apparent phase difference .THETA..sub.2 ' when a concentration measuring operation of the fluid to be measured is switched to a non-measuring operation in response to a change of the operation mode set to the operation mode setter.
    • 微波密度计包括相位差检测部分,用于检测由微波发生器产生的微波与由微波接收器接收的微波之间的相位差,用于改变旋转数“n”的转数更新部分, 用于获得表示真相相位差THETA2和参考相位差THETA 1'之间的差的差值DELTA THETA,用于将差值DELTA THETA转换为浓度信号的信号转换器,用于设置操作模式的操作模式设定器, 以及保持电路,用于当要测量的流体的浓度测量操作根据操作模式设置的变化切换到非测量操作时,保持转数“n”和视在相位差THETA 2' 到操作模式设置器。
    • 27. 发明授权
    • Microprocessor with dual-port cache memory for reducing penalty of
consecutive memory address accesses
    • 具有双端口缓存存储器的微处理器,用于减少连续存储器地址访问的损失
    • US5465344A
    • 1995-11-07
    • US352445
    • 1994-12-09
    • Koutarou HiraiSeiji Yamaguchi
    • Koutarou HiraiSeiji Yamaguchi
    • G06F12/08G06F13/00G06F13/14
    • G06F12/0855G06F12/0853G06F12/0831
    • A microprocessor has a CPU, an address converter which converts a logical address to a physical address, first and second latches which are controlled by a control signal and store the physical addresses, and a dual port cache memory device. The dual port cache memory device has decoders which operate according to second parts of outputs of the latches, dual port memory arrays which can be independently accessed by outputs of the decoders, a comparator which compares a physical address output from the dual port memory array and a first part of an output of the first latch to determine if they are the same, and a second comparator which compares a physical address output from the dual port memory array and a first part of an output of the second latch to determine if they are the same. The microprocessor is configured to effectively utilize the two ports of the dual port memory array of the dual port cache memory device, significantly improving the operating speed of the overall system by reducing the occurrence of penalties when consecutive instructions operating the cache memory are executed.
    • 微处理器具有CPU,将逻辑地址转换为物理地址的地址转换器,由控制信号控制并存储物理地址的第一和第二锁存器以及双端口高速缓存存储器件。 双端口高速缓冲存储器设备具有根据锁存器的输出的第二部分操作的解码器,可以由解码器的输出独立访问的双端口存储器阵列,将来自双端口存储器阵列的物理地址输出和 第一锁存器的输出的第一部分以确定它们是否相同;以及第二比较器,其比较来自双端口存储器阵列的物理地址输出和第二锁存器的输出的第一部分,以确定它们是否是 一样。 微处理器被配置为有效地利用双端口高速缓冲存储器设备的双端口存储器阵列的两个端口,通过在执行连续指令操作高速缓冲存储器时减少发生的惩罚,显着地提高整个系统的操作速度。
    • 28. 发明授权
    • Phase locked loop having plural selectable voltage controlled oscillators
    • 锁相环具有多个可选择的压控振荡器
    • US5389898A
    • 1995-02-14
    • US79530
    • 1993-06-22
    • Osamu TaketoshiTsuguyasu HatsudaSeiji Yamaguchi
    • Osamu TaketoshiTsuguyasu HatsudaSeiji Yamaguchi
    • H03L7/089H03L7/099H03L7/10H03L7/183H03L7/18
    • H03L7/089H03L7/099H03L7/0997H03L7/10H03L7/183
    • The invention discloses a PLL formed by a phase detector, a filter, three VCO's (VCO1, VCO2, and VCO3), a multiplexer, and a frequency divider. The VCO1, VCO2, and VCO3 have different mean frequencies, each oscillating at a frequency controlled according to the voltage value of a phase control signal from the filter. The multiplexer selects one of the VCO's which operate in parallel. If a pulse of a digital phase difference signal UP indicating that an internal signal is delayed in phase with respect to a reference signal is output twice in succession, or if a pulse of a digital phase difference signal DOWN indicating that an internal signal is advanced in phase with respect to a reference signal is output twice in succession, a counter makes the multiplexer change its current VCO selection via a shift register. Accordingly, high-speed PLL pulling is achievable even if a PLL frequency variable-range is expanded.
    • 本发明公开了一种由相位检测器,滤波器,三个VCO(VCO1,VCO2和VCO3),多路复用器和分频器组成的PLL。 VCO1,VCO2和VCO3具有不同的平均频率,每个频率在根据来自滤波器的相位控制信号的电压值控制的频率下振荡。 复用器选择并行操作的VCO中的一个。 如果相对于参考信号指示内部信号相位延迟的数字相位差信号UP的脉冲连续输出两次,或者如果指示内部信号提前的数字相位差信号DOWN的脉冲 相对于参考信号的相位被连续输出两次,计数器使多路复用器通过移位寄存器改变其当前的VCO选择。 因此,即使PLL频率可变范围扩大,也可以实现高速PLL拉动。