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21. 发明申请

US20080005374A1 System and Method for Flexible Multiple Protocols 有权
标题翻译：灵活多协议的系统和方法
公开(公告)号：US20080005374A1
公开(公告)日：2008-01-03
申请号：US11844336
申请日：2007-08-23
申请人： Scott Clark , Charles Johns , James Kahle
发明人： Scott Clark , Charles Johns , James Kahle
IPC分类号： G06F3/00
CPC分类号： G06F13/385
摘要： A system and method for flexible multiple protocols are presented. A device's logical layer may be dynamically configured on a per interface basis to communicate with external devices in a coherent or a non-coherent mode. In coherent mode, commands such as coherency protocol, system commands, and snoop response pass from the device's internal system bus to an external device, thereby creating a logical extension of the devices internal system bus. In non-coherent mode, the input-output bus unit receives commands from the internal system bus and generates non-coherent input-output commands, which are eventually received by an external device.
摘要翻译：介绍了灵活多协议的系统和方法。可以在每个接口的基础上动态地配置设备的逻辑层，以以相干或非相干模式与外部设备进行通信。在相干模式下，诸如一致性协议，系统命令和侦听响应的命令从设备的内部系统总线传递到外部设备，从而创建设备内部系统总线的逻辑扩展。在非相干模式下，输入 - 输出总线单元从内部系统总线接收命令，并产生最终由外部设备接收的非相干输入 - 输出命令。

22. 发明申请

US20060179168A1 System and method for flexible multiple protocols 有权
标题翻译：灵活多协议的系统和方法
公开(公告)号：US20060179168A1
公开(公告)日：2006-08-10
申请号：US11050022
申请日：2005-02-03
申请人： Scott Clark , Charles Johns , James Kahle
发明人： Scott Clark , Charles Johns , James Kahle
IPC分类号： G06F3/00
CPC分类号： G06F13/385
摘要： A system and method for flexible multiple protocols are presented. A device's logical layer may be dynamically configured on a per interface basis to communicate with external devices in a coherent or a non-coherent mode. In coherent mode, commands such as coherency protocol, system commands, and snoop response pass from the device's internal system bus to an external device, thereby creating a logical extension of the devices internal system bus. In non-coherent mode, the input-output bus unit receives commands from the internal system bus and generates non-coherent input-output commands, which are eventually received by an external device.
摘要翻译：介绍了灵活多协议的系统和方法。可以在每个接口的基础上动态地配置设备的逻辑层，以以相干或非相干模式与外部设备进行通信。在相干模式下，诸如一致性协议，系统命令和侦听响应的命令从设备的内部系统总线传递到外部设备，从而创建设备内部系统总线的逻辑扩展。在非相干模式下，输入 - 输出总线单元从内部系统总线接收命令，并产生最终由外部设备接收的非相干输入 - 输出命令。

23. 发明申请

US20050216610A1 Method to provide cache management commands for a DMA controller 失效
标题翻译：为DMA控制器提供高速缓存管理命令的方法
公开(公告)号：US20050216610A1
公开(公告)日：2005-09-29
申请号：US10809553
申请日：2004-03-25
申请人： Charles Johns , James Kahle , Peichun Liu , Thuong Truong
发明人： Charles Johns , James Kahle , Peichun Liu , Thuong Truong
IPC分类号： G06F12/08 , G06F13/28
CPC分类号： G06F13/28 , G06F12/0835 , G06F12/0837 , G06F12/0862
摘要： The present invention provides a method and a system for providing cache management commands in a system supporting a DMA mechanism and caches. A DMA mechanism is set up by a processor. Software running on the processor generates cache management commands. The DMA mechanism carries out the commands, thereby enabling the software program management of the caches. The commands include commands for writing data to the cache, loading data from the cache, and for marking data in the cache as no longer needed. The cache can be a system cache or a DMA cache.
摘要翻译：本发明提供了一种用于在支持DMA机制和高速缓存的系统中提供高速缓存管理命令的方法和系统。 DMA机制由处理器设置。处理器上运行的软件会生成缓存管理命令。 DMA机制执行命令，从而实现高速缓存的软件程序管理。这些命令包括用于将数据写入缓存的命令，从高速缓存加载数据，以及用于在不再需要的情况下将数据标记在缓存中。缓存可以是系统缓存或DMA高速缓存。

24. 发明申请

US20060251070A1 Methods and apparatus for facilitating coherency management in distributed multi-processor system 有权
标题翻译：用于促进分布式多处理器系统中的一致性管理的方法和装置
公开(公告)号：US20060251070A1
公开(公告)日：2006-11-09
申请号：US11098621
申请日：2005-04-04
申请人： Takeshi Yamazaki , Jeffrey Brown , Scott Clark , Charles Johns
发明人： Takeshi Yamazaki , Jeffrey Brown , Scott Clark , Charles Johns
IPC分类号： H04L12/56
CPC分类号： G06F12/0831 , G06F12/0813 , G06F2212/251 , G06F2212/253
摘要： Methods and apparatus provide for sending a data command from a first of a plurality of devices to a first address concentrator within a first of a plurality of processing systems; selecting one of the other processing systems, the selected processing system having data addressed by the data command stored therein; sending the data command to a first address concentrator of the selected processing system; and broadcasting the data command from the first address concentrator of the selected processing system to a second address concentrator in each of the processing systems.
摘要翻译：方法和装置提供从多个设备中的第一设备向多个处理系统中的第一个内的第一地址集中器发送数据命令; 选择其他处理系统之一，所选择的处理系统具有由其中存储的数据命令寻址的数据; 将所述数据命令发送到所选择的处理系统的第一地址集中器; 以及从所选择的处理系统的第一地址集中器将数据命令广播到每个处理系统中的第二地址集中器。

25. 发明申请

US20060206657A1 Single port/multiple ring implementation of a hybrid crossbar partially non-blocking data switch 审中-公开
标题翻译：单端口/多环实现混合交叉开关部分非阻塞数据交换
公开(公告)号：US20060206657A1
公开(公告)日：2006-09-14
申请号：US11077330
申请日：2005-03-10
申请人： Scott Clark , Charles Johns , David Krolak , Takeshi Yamazaki , Jeffrey Brown
发明人： Scott Clark , Charles Johns , David Krolak , Takeshi Yamazaki , Jeffrey Brown
IPC分类号： G06F13/00
CPC分类号： G06F13/362 , G06F1/3237 , G06F1/3253 , Y02D10/128 , Y02D10/151
摘要： A ring-based crossbar data switch, a method and a computer program are provided for the transfer of data between multiple bus units in a memory system. Each bus unit is connected to a corresponding data ramp. Each data ramp is only directly connected to the adjacent data ramps. This forms at least one data ring that enables the transfer of data from each bus unit to any other bus unit in the memory system. A central arbiter manages the transfer of data between the data ramps and the transfer of data between the data ramp and its corresponding bus unit. A preferred embodiment contains four data rings, wherein two data rings transfer data clockwise and two data rings transfer data counter-clockwise.
摘要翻译：提供了一种基于环的交叉开关数据开关，方法和计算机程序，用于在存储器系统中的多个总线单元之间传送数据。每个总线单元连接到相应的数据斜坡。每个数据斜坡仅直接连接到相邻的数据斜坡。这形成至少一个数据环，其使得能够将数据从每个总线单元传送到存储器系统中的任何其它总线单元。中央仲裁器管理数据斜坡之间的数据传输和数据斜坡与其对应的总线单元之间的数据传输。优选实施例包含四个数据环，其中两个数据环顺时针传送数据，两个数据环逆时针传送数据。

26. 发明申请

US20050111478A1 Distributed control load shaping method and apparatus 审中-公开
标题翻译：分布式控制负载整形方法及装置
公开(公告)号：US20050111478A1
公开(公告)日：2005-05-26
申请号：US10718936
申请日：2003-11-20
申请人： Jeffrey Brown , Michael Day , Charles Johns , Thuong Truong , Takeshi Yamazaki
发明人： Jeffrey Brown , Michael Day , Charles Johns , Thuong Truong , Takeshi Yamazaki
IPC分类号： H04L12/56 , H04L12/42
CPC分类号： H04L47/822 , H04L47/13 , H04L47/20 , H04L47/22 , H04L47/2441 , H04L47/39 , H04L47/70 , H04L47/72 , H04L47/781 , H04L47/803 , H04L47/821
摘要： Disclosed is an apparatus for controlling or managing the transmission of data packets over a multiplexed communication path, referred to herein as a bus, on a priority basis up to a given authorized BW (Bandwidth), in a given operational time period, for presently authorized devices or applications. Non-managed (not presently authorized) bus requests are handled in a prior art “best effort” basis.
摘要翻译：公开了一种用于在给定的操作时间段内，在给定的操作时间段内优先地基于多路通信路径（这里称为总线）来控制或管理数据分组的传输的装置，用于当前授权的设备或应用程序。非管理（未授权）总线请求以现有技术“尽力而为”为基础来处理。

27. 发明申请

US20050055478A1 Proxy direct memory access 有权
标题翻译：代理直接内存访问
公开(公告)号：US20050055478A1
公开(公告)日：2005-03-10
申请号：US10655370
申请日：2003-09-04
申请人： Charles Johns , Peichun Liu , Thuong Truong , Asano Shigehiro , Takeshi Yamazaki
发明人： Charles Johns , Peichun Liu , Thuong Truong , Asano Shigehiro , Takeshi Yamazaki
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A system and method are provided for setting up a direct memory access for a first processor. The system includes the first processor and a local memory. The local memory is coupled to the first processor. A first direct memory access controller (DMAC) is coupled to the first processor and the local memory. A system memory is in communication with the first DMAC. A second processor is in communication with the first DMAC such that the second processor sets up the first DMAC to handle data transfer between the local memory and the system memory. The second processor is interrupted when the first DMAC finishes handling the data transfer.
摘要翻译：提供了一种用于为第一处理器建立直接存储器访问的系统和方法。该系统包括第一处理器和本地存储器。本地存储器耦合到第一处理器。第一直接存储器存取控制器（DMAC）耦合到第一处理器和本地存储器。系统存储器与第一DMAC通信。第二处理器与第一DMAC通信，使得第二处理器设置第一DMAC来处理本地存储器和系统存储器之间的数据传输。当第一个DMAC完成处理数据传输时，第二个处理器中断。

28. 发明申请

US20060026309A1 Memory barriers primitives in an asymmetric heterogeneous multiprocessor environment 有权
标题翻译：非对称异构多处理器环境中的内存障碍原语
公开(公告)号：US20060026309A1
公开(公告)日：2006-02-02
申请号：US10902474
申请日：2004-07-29
申请人： Michael Day , Charles Johns , Peichun Liu , Thuong Truong , Takeshi Yamazaki
发明人： Michael Day , Charles Johns , Peichun Liu , Thuong Truong , Takeshi Yamazaki
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： The present invention provides a method and apparatus for creating memory barriers in a Direct Memory Access (DMA) device. A memory barrier command is received and a memory command is received. The memory command is executed based on the memory barrier command. A bus operation is initiated based on the memory barrier command. A bus operation acknowledgment is received based on the bus operation. The memory barrier command is executed based on the bus operation acknowledgment. In a particular aspect, memory barrier commands are direct memory access sync (dmasync) and direct memory access enforce in-order execution of input/output (dmaeieio) commands.
摘要翻译：本发明提供了一种用于在直接存储器访问（DMA）设备中创建存储障碍的方法和装置。接收到存储器屏障命令并接收存储器命令。内存命令是根据内存屏障命令执行的。基于内存障碍命令启动总线操作。基于总线操作接收总线操作确认。基于总线操作确认执行存储器障碍命令。在特定方面，存储器屏障命令是直接存储器访问同步（dmasync），并且直接存储器访问强制执行输入/输出（dmaeie））命令的按顺序执行。

29. 发明申请

US20050125581A1 Method of resource arbitration 失效
标题翻译：资源仲裁方法
公开(公告)号：US20050125581A1
公开(公告)日：2005-06-09
申请号：US10730952
申请日：2003-12-09
申请人： Jeffrey Brown , Scott Clark , Charles Johns , Takeshi Yamazaki
发明人： Jeffrey Brown , Scott Clark , Charles Johns , Takeshi Yamazaki
IPC分类号： G06F13/14 , G06F13/362
CPC分类号： G06F13/3625
摘要： An improved method and apparatus for resource arbitration. Four priority classes, managed high (MH), managed low (ML), opportunistic high (OH) and opportunistic low (OL), are defined. A priority class is assigned to each resource access request. An access request concentrator (ARC) is created for each resource, through which the resource is accessed. An access request is chosen at each ARC using the priority order MH, ML, OH, and OL, in decreasing order of priority. If OH priority class resource access requests are locked out, the priority order is temporarily changed to OH, OL, MH, and ML, in decreasing order of priority. If OL priority class resource access requests are locked out, the priority order is temporarily changed to MH, OL, OH, and ML, in decreasing order of priority.
摘要翻译：一种改进的资源仲裁方法和装置。定义了四个优先级，管理高（MH），管理低（ML），机会高（OH）和机会主义低（OL）。优先级分配给每个资源访问请求。为每个资源创建访问请求集中器（ARC），通过该资源访问资源。在优先级顺序为MH，ML，OH和OL的每个ARC中选择访问请求。如果OH优先级资源访问请求被锁定，优先级顺序将按照优先级的降序暂时更改为OH，OL，MH和ML。如果OL优先级资源访问请求被锁定，优先级顺序将按照优先级的降序临时更改为MH，OL，OH和ML。

30. 发明申请

US20060015652A1 Establishing command order in an out of order DMA command queue 失效
标题翻译：在命令行DMA命令队列中建立命令顺序
公开(公告)号：US20060015652A1
公开(公告)日：2006-01-19
申请号：US10891772
申请日：2004-07-15
申请人： Michael Day , Charles Johns , Peichun Liu , Thuong Truong , Takeshi Yamazaki
发明人： Michael Day , Charles Johns , Peichun Liu , Thuong Truong , Takeshi Yamazaki
IPC分类号： G06F13/14
CPC分类号： G06F13/28
摘要： A method, an apparatus, and a computer program are provided for controlling memory access. Direct Memory Access (DMA) units have become commonplace in a number of bus architectures. However, managing limited system resources has become a challenge with multiple DMA units. In order to mange the multitude of commands generated and preserve dependencies, embedded flags in commands or a barrier command are used. These operations then can control the order in which commands are executed so as to preserve dependencies.
摘要翻译：提供了一种用于控制存储器访问的方法，装置和计算机程序。直接存储器访问（DMA）单元已经在许多总线架构中变得普遍。然而，管理有限的系统资源已成为多个DMA单元的挑战。为了管理生成的多个命令并保留依赖关系，使用命令中的嵌入式标志或障碍命令。这些操作然后可以控制执行命令的顺序，以便保留依赖性。

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