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1. 发明申请

US20060206657A1 Single port/multiple ring implementation of a hybrid crossbar partially non-blocking data switch 审中-公开
标题翻译：单端口/多环实现混合交叉开关部分非阻塞数据交换
公开(公告)号：US20060206657A1
公开(公告)日：2006-09-14
申请号：US11077330
申请日：2005-03-10
申请人： Scott Clark , Charles Johns , David Krolak , Takeshi Yamazaki , Jeffrey Brown
发明人： Scott Clark , Charles Johns , David Krolak , Takeshi Yamazaki , Jeffrey Brown
IPC分类号： G06F13/00
CPC分类号： G06F13/362 , G06F1/3237 , G06F1/3253 , Y02D10/128 , Y02D10/151
摘要： A ring-based crossbar data switch, a method and a computer program are provided for the transfer of data between multiple bus units in a memory system. Each bus unit is connected to a corresponding data ramp. Each data ramp is only directly connected to the adjacent data ramps. This forms at least one data ring that enables the transfer of data from each bus unit to any other bus unit in the memory system. A central arbiter manages the transfer of data between the data ramps and the transfer of data between the data ramp and its corresponding bus unit. A preferred embodiment contains four data rings, wherein two data rings transfer data clockwise and two data rings transfer data counter-clockwise.
摘要翻译：提供了一种基于环的交叉开关数据开关，方法和计算机程序，用于在存储器系统中的多个总线单元之间传送数据。每个总线单元连接到相应的数据斜坡。每个数据斜坡仅直接连接到相邻的数据斜坡。这形成至少一个数据环，其使得能够将数据从每个总线单元传送到存储器系统中的任何其它总线单元。中央仲裁器管理数据斜坡之间的数据传输和数据斜坡与其对应的总线单元之间的数据传输。优选实施例包含四个数据环，其中两个数据环顺时针传送数据，两个数据环逆时针传送数据。

2. 发明申请

US20080052472A1 METHODS AND APPARATUS FOR REDUCING COMMAND PROCESSING LATENCY WHILE MAINTAINING COHERENCE 失效
标题翻译：在保持协调的同时减少指令处理的方法和装置
公开(公告)号：US20080052472A1
公开(公告)日：2008-02-28
申请号：US11846697
申请日：2007-08-29
申请人： Jeffrey Brown , Scott Clark , Mark Fredrickson , Charles Johns , David Krolak
发明人： Jeffrey Brown , Scott Clark , Mark Fredrickson , Charles Johns , David Krolak
IPC分类号： G06F12/16
CPC分类号： G06F12/0804 , G06F12/0831
摘要： In a first aspect, a first method of reducing command processing latency while maintaining memory coherence is provided. The first method includes the steps of (1) providing a memory map including memory addresses available to a system; and (2) arranging the memory addresses into a plurality of groups. At least one of the groups does not require the system, in response to a command that requires access to a memory address in the group from a bus unit, to get permission from all remaining bus units included in the system to maintain memory coherence. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种在维持存储器一致性的同时降低命令处理等待时间的方法。第一种方法包括以下步骤：（1）提供包括可用于系统的存储器地址的存储器映射; 和（2）将存储器地址排列成多个组。响应于需要访问来自总线单元的组中的存储器地址的命令，组中的至少一个不需要系统以从包括在系统中的所有剩余总线单元获得许可以维持存储器一致性。提供了许多其他方面。

3. 发明申请

US20070073949A1 Fair hierarchical arbiter 有权
公开(公告)号：US20070073949A1
公开(公告)日：2007-03-29
申请号：US11239615
申请日：2005-09-29
申请人： Mark Fredrickson , David Krolak
发明人： Mark Fredrickson , David Krolak
IPC分类号： G06F13/14
CPC分类号： G06F13/362
摘要： A fair hierarchical arbiter comprises a number of arbitration mechanisms, each arbitration mechanism forwarding winning requests from requestors in round robin order by requestor. In addition to the winning requests, each arbitration mechanism forwards valid request bits, the valid request bits providing information about which requestor originated a current winning request, and, in some embodiments, about how many separate requesters are arbitrated by that particular arbitration mechanism. The fair hierarchical arbiter outputs requests from the total set of separate requestors in a round robin order.

4. 发明申请

US20070234159A1 METHOD AND APPARATUS FOR TESTING A RING OF NON-SCAN LATCHES WITH LOGIC BUILT-IN SELF-TEST 失效
标题翻译：用逻辑内置自测测试非线性锁存环的方法和装置
公开(公告)号：US20070234159A1
公开(公告)日：2007-10-04
申请号：US11278313
申请日：2006-03-31
申请人： LOUIS BUSHARD , Nathan Chelstrom , Naoki Kiryu , David Krolak
发明人： LOUIS BUSHARD , Nathan Chelstrom , Naoki Kiryu , David Krolak
IPC分类号： G01R31/28
CPC分类号： G01R31/318525 , G01R31/3187
摘要： A method and apparatus for loading a ring of non-scan latches for a logic built-in self-test. A logic built-in self-test value is loaded into a scannable latch from the logic built-in self-test. An override control signal is asserted in response to loading the logic built-in self-test value into the scannable latch. A non-scan latch is forced to load the logic built-in self-test value from the scannable latch in response to asserting the override control signal. Logic paths in the ring of non-scan latches are exercised. The non-scan latch is part of the logical paths. The test results are captured from the logic paths and the test results are compared against expected test results to determine if the logic paths within the ring of non-scan latches are functioning properly.
摘要翻译：一种用于加载用于逻辑内置自检的非扫描锁存器环的方法和装置。逻辑内置自检值从逻辑内置自检中加载到可扫描锁存器中。响应于将逻辑内置自检值加载到可扫描锁存器中，覆盖控制信号被断言。响应于断言覆盖控制信号，非扫描锁存器被强制从可扫描锁存器加载逻辑内置自检值。执行非扫描锁存器环中的逻辑路径。非扫描锁存器是逻辑路径的一部分。从逻辑路径捕获测试结果，并将测试结果与预期测试结果进行比较，以确定非扫描锁存器环内的逻辑路径是否正常工作。

5. 发明申请

US20070174556A1 Methods and apparatus for reducing command reissue latency 审中-公开
标题翻译：减少命令重发延迟的方法和装置
公开(公告)号：US20070174556A1
公开(公告)日：2007-07-26
申请号：US11340751
申请日：2006-01-26
申请人： Jeffrey Brown , Michael Carnevale , Charles Johns , David Krolak , Thuong Truong
发明人： Jeffrey Brown , Michael Carnevale , Charles Johns , David Krolak , Thuong Truong
IPC分类号： G06F13/00
CPC分类号： G06F12/0831
摘要： In a first aspect, a first method of reducing reissue latency of a command received in a command processing pipeline from one of a plurality of units coupled to a bus is provided. The first method includes the steps of (1) from a first unit coupled to the bus, receiving a first command on the bus requiring access to a cacheline; (2) determining a state of the cacheline required by the first command by accessing cacheline state information stored in each of the plurality of units; (3) determining whether a second command received on the bus requires access to the cacheline before the state of the cacheline is returned to the first unit; and (4) if so, storing the second command in a buffer. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种减少在命令处理流水线中从耦合到总线的多个单元之一接收的命令的重发等待时间的第一方法。第一种方法包括以下步骤：（1）从耦合到总线的第一单元接收需要访问高速缓存线的总线上的第一命令; （2）通过访问存储在所述多个单元中的每个单元中的高速缓存行状态信息来确定所述第一命令所需的高速缓存行的状态; （3）在高速缓存行的状态返回到第一单元之前，确定在总线上接收的第二命令是否需要访问高速缓存线; 和（4）如果是，则将第二命令存储在缓冲器中。提供了许多其他方面。

6. 发明申请

US20070186052A1 Methods and apparatus for reducing command processing latency while maintaining coherence 审中-公开
标题翻译：减少命令处理延迟同时保持一致性的方法和装置
公开(公告)号：US20070186052A1
公开(公告)日：2007-08-09
申请号：US11348969
申请日：2006-02-07
申请人： Jeffrey Brown , Scott Clark , Mark Fredrickson , Charles Johns , David Krolak
发明人： Jeffrey Brown , Scott Clark , Mark Fredrickson , Charles Johns , David Krolak
IPC分类号： G06F13/28
CPC分类号： G06F12/0804 , G06F12/0831
摘要： In a first aspect, a first method of reducing command processing latency while maintaining memory coherence is provided. The first method includes the steps of (1) providing a memory map including memory addresses available to a system; and (2) arranging the memory addresses into a plurality of groups. At least one of the groups does not require the system, in response to a command that requires access to a memory address in the group from a bus unit, to get permission from all remaining bus units included in the system to maintain memory coherence. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种在维持存储器一致性的同时降低命令处理等待时间的方法。第一种方法包括以下步骤：（1）提供包括可用于系统的存储器地址的存储器映射; 和（2）将存储器地址排列成多个组。响应于需要访问来自总线单元的组中的存储器地址的命令，组中的至少一个不需要系统以从包括在系统中的所有剩余总线单元获得许可以维持存储器一致性。提供了许多其他方面。

7. 发明申请

US20070186027A1 Method and apparatus for implementing control of a multiple ring hybrid crossbar partially non-blocking data switch 审中-公开
标题翻译：用于实现多环混合交叉开关部分非阻塞数据交换机的控制的方法和装置
公开(公告)号：US20070186027A1
公开(公告)日：2007-08-09
申请号：US11348825
申请日：2006-02-07
申请人： Danny Klema , David Krolak
发明人： Danny Klema , David Krolak
IPC分类号： G06F13/00 , G06F13/14 , G06F13/38
CPC分类号： G06F13/4009 , G06F13/14
摘要： A method and control apparatus are provided for implementing control of a multiple-ring hybrid crossbar partially non-blocking data switch, the data switch including a plurality of bus units, each bus unit coupled to a respective data ramp and a plurality of data rings connected between each of the data ramps, with each data ramp device only connected to the two adjacent data ramp devices. Control apparatus includes one request handler per bus unit, one destination arbiter per bus unit, and one ring arbiter per ring. The request handler receives a request from an associated bus unit and saves the pending request state until a grant to the bus unit occurs. The request includes a destination unit identifier. The request handler forwards the request to the destination arbiter for the destination unit and the destination arbiter grants the request. Responsive to the destination arbiter granting the request, the request handler individually asks one of the ring arbiters to use the respective ring. One of the ring arbiters arbitrates between its request handler requests and issues a grant and then controls the flow of data around the ring.
摘要翻译：提供了一种用于实现多环混合交叉开关部分非阻塞数据交换机的控制的方法和控制装置，数据交换机包括多个总线单元，每个总线单元耦合到相应的数据斜坡和连接的多个数据环在每个数据斜坡之间，每个数据斜坡装置仅连接到两个相邻的数据斜坡装置。控制装置包括每个总线单元一个请求处理器，每个总线单元一个目的仲裁器和每个环一个环仲裁器。请求处理器从相关联的总线单元接收请求，并保存待处理的请求状态，直到发生对总线单元的授予。该请求包括目的地单元标识符。请求处理程序将请求转发到目标单元的目标仲裁器，目的仲裁器授予请求。响应于授予请求的目的地仲裁器，请求处理程序单独地请求其中一个环仲裁器使用相应的环。其中一个环仲裁器在其请求处理程序请求之间进行仲裁，并发出授权，然后控制环上的数据流。

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