专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20110070713A1 METHOD OF MANUFACTURING ELECTRONIC COMPONENT 有权
标题翻译：制造电子元件的方法
公开(公告)号：US20110070713A1
公开(公告)日：2011-03-24
申请号：US12882649
申请日：2010-09-15
申请人： Hiroyuki Nansei
发明人： Hiroyuki Nansei
IPC分类号： H01L21/02
CPC分类号： H01L45/16 , H01L27/0207 , H01L27/24
摘要： According to one embodiment, a lower wiring layer is formed by using a sidewall transfer process for forming a sidewall film having a closed loop along a sidewall of a sacrificed or dummy pattern and, after removing the sacrificed pattern to leave the sidewall film, selectively removing the base material with the sidewall film as a mask. One or more upper wiring layers are formed in an upper layer of the lower wiring layer via another layer using the sidewall transfer process. Etching for cutting each of the lower wiring layer and the upper wiring layers is collectively performed, whereby closed-loop cut is applied to the lower wiring layer and the upper wiring layers.
摘要翻译：根据一个实施例，通过使用侧壁转移工艺形成下部布线层，所述侧壁转移工艺用于形成具有沿牺牲或虚拟图案的侧壁的闭环的侧壁膜，并且在去除牺牲图案以离开侧壁膜之后，选择性地去除该基材以侧壁膜为掩模。使用侧壁转移工艺，通过另一层在下布线层的上层中形成一个或多个上布线层。共同进行用于切割下布线层和上布线层的蚀刻，由此对下布线层和上布线层施加闭环切割。

22. 发明授权

US07274592B2 Non-volatile memory and method of controlling the same 有权
标题翻译：非易失性存储器及其控制方法
公开(公告)号：US07274592B2
公开(公告)日：2007-09-25
申请号：US11342947
申请日：2006-01-30
申请人： Yukio Hayakawa , Hiroyuki Nansei
发明人： Yukio Hayakawa , Hiroyuki Nansei
IPC分类号： G11C16/04
CPC分类号： H01L29/66833 , G11C16/0475 , H01L27/115 , H01L27/11568 , H01L29/7923
摘要： A single cell that has a gate insulating film formed with an ONO film is provided in a region in which two bit lines cross one word line. The single cell is a four-bit multi-value cell, and has four charge accumulation regions. Two plug-like control electrodes are provided in the region surrounded by the word line and the bit lines. A bias is applied to one of the plug-like control electrodes and the word line so that the portion on the surface of the semiconductor substrate that is located immediately below the word line and corresponds to the location of the bias-applied control electrode is put into an accumulation state or a depletion state. In this manner, the width of the channel is adjusted, and the charge holding state of each of the four charge accumulation regions is controlled through the channel width adjustment.
摘要翻译：在两个位线交叉一个字线的区域中设置具有由ONO膜形成的栅极绝缘膜的单电池。单个单元是四位多值单元，并具有四个电荷累积区。在由字线和位线包围的区域中设置两个插塞状控制电极。对一个插塞状控制电极和字线施加偏压，使得位于字线正下方并对应于施加偏压的控制电极的位置的半导体衬底的表面上的部分被放置成为累积状态或耗尽状态。以这种方式，调节通道的宽度，并且通过通道宽度调节来控制四个电荷累积区域中的每一个的电荷保持状态。

23. 发明授权

US08357965B2 Semiconductor device having multiple storage regions 有权
标题翻译：具有多个存储区域的半导体器件
公开(公告)号：US08357965B2
公开(公告)日：2013-01-22
申请号：US12005869
申请日：2007-12-28
申请人： Hiroyuki Nansei
发明人： Hiroyuki Nansei
IPC分类号： H01L29/76 , H01L29/788 , H01L29/792 , G11C11/34 , G11C16/04 , H01L21/336
CPC分类号： H01L29/42336 , H01L29/42352 , H01L29/7881 , H01L29/792
摘要： One embodiment in accordance with the invention can include a semiconductor device that includes: a groove that is formed in a semiconductor substrate; bottom oxide films that are formed on both side faces of the groove; two charge storage layers that are formed on side faces of the bottom oxide films; top oxide films that are formed on side faces of the two charge storage layers; and a silicon oxide layer that is formed on the bottom face of the groove, and has a smaller film thickness than the top oxide films.
摘要翻译：根据本发明的一个实施例可以包括半导体器件，其包括：形成在半导体衬底中的沟槽; 形成在槽的两个侧面上的底部氧化物膜; 形成在底部氧化物膜的侧面上的两个电荷存储层; 形成在两个电荷存储层的侧面上的顶部氧化物膜; 以及形成在所述槽的底面上并且具有比所述顶部氧化物膜更薄的膜厚度的氧化硅层。

24. 发明申请

US20090020799A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20090020799A1
公开(公告)日：2009-01-22
申请号：US12005869
申请日：2007-12-28
申请人： Hiroyuki Nansei
发明人： Hiroyuki Nansei
IPC分类号： H01L29/788
CPC分类号： H01L29/42336 , H01L29/42352 , H01L29/7881 , H01L29/792
摘要： One embodiment in accordance with the invention can include a semiconductor device that includes: a groove that is formed in a semiconductor substrate; bottom oxide films that are formed on both side faces of the groove; two charge storage layers that are formed on side faces of the bottom oxide films; top oxide films that are formed on side faces of the two charge storage layers; and a silicon oxide layer that is formed on the bottom face of the groove, and has a smaller film thickness than the top oxide films.
摘要翻译：根据本发明的一个实施例可以包括半导体器件，其包括：形成在半导体衬底中的沟槽; 形成在槽的两个侧面上的底部氧化物膜; 形成在底部氧化物膜的侧面上的两个电荷存储层; 形成在两个电荷存储层的侧面上的顶部氧化物膜; 以及形成在所述槽的底面上并且具有比所述顶部氧化物膜更薄的膜厚度的氧化硅层。

25. 发明申请

US20080217673A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080217673A1
公开(公告)日：2008-09-11
申请号：US12026421
申请日：2008-02-05
申请人： Takayuki Maruyama , Yukio Hayakawa , Hiroyuki Nansei
发明人： Takayuki Maruyama , Yukio Hayakawa , Hiroyuki Nansei
IPC分类号： H01L29/94 , H01L21/02 , H01L21/336
CPC分类号： H01L29/7923 , G11C16/0475 , H01L27/115 , H01L27/11568 , H01L27/11582 , H01L29/40117 , H01L29/7926
摘要： A semiconductor device includes a stack structure in which multiple channel layers are stacked on a substrate so as to be sandwiched between bit line layers, a gate electrode that is provided to the side of the lateral surface of an interior of a groove portion formed within the stack structure, and a charge storage layer that is provided between the gate electrode and the channel layer.
摘要翻译：半导体器件包括堆叠结构，其中多个沟道层堆叠在衬底上以被夹在位线层之间，栅电极设置在形成在衬底内的沟槽部分的内部的侧表面侧堆叠结构，以及设置在栅电极和沟道层之间的电荷存储层。

26. 发明授权

US08691645B2 Method of manufacturing convex shaped thin-film transistor device 有权
标题翻译：制造凸形薄膜晶体管器件的方法
公开(公告)号：US08691645B2
公开(公告)日：2014-04-08
申请号：US13572487
申请日：2012-08-10
申请人： Yukio Hayakawa , Hiroyuki Nansei
发明人： Yukio Hayakawa , Hiroyuki Nansei
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/76
CPC分类号： H01L27/11517 , H01L21/28273 , H01L21/28282 , H01L21/84 , H01L23/5283 , H01L27/115 , H01L27/11521 , H01L27/11556 , H01L27/11563 , H01L27/11568 , H01L27/1203 , H01L29/42332 , H01L29/42348 , H01L29/66757 , H01L29/66825 , H01L29/66833 , H01L29/788 , H01L29/7881 , H01L29/792 , H01L29/7926 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a semiconductor device that has a shorter distance between the bit lines and easily achieves higher storage capacity and density, and a method of manufacturing such a semiconductor device. The semiconductor device includes: first bit lines formed on a substrate; an insulating layer that is provided between the first bit lines on the substrate, and has a higher upper face than the first bit lines; channel layers that are provided on both side faces of the insulating layer, and are coupled to the respective first bit lines; and charge storage layers that are provided on the opposite side faces of the channel layers from the side faces on which the insulating layers are formed.
摘要翻译：本发明提供一种半导体器件，其位线之间的距离较短，并且容易实现更高的存储容量和密度，以及制造这种半导体器件的方法。半导体器件包括：形成在衬底上的第一位线; 绝缘层，设置在所述基板上的所述第一位线之间，并且具有比所述第一位线更高的上表面; 沟道层，其设置在绝缘层的两个侧面上，并且耦合到相应的第一位线; 并且从形成有绝缘层的侧面向沟道层的相对侧面设置电荷存储层。

27. 发明授权

US08536048B2 Method of manufacturing electronic component 有权
公开(公告)号：US08536048B2
公开(公告)日：2013-09-17
申请号：US12882649
申请日：2010-09-15
申请人： Hiroyuki Nansei
发明人： Hiroyuki Nansei
IPC分类号： H01L21/4763
CPC分类号： H01L45/16 , H01L27/0207 , H01L27/24
摘要： According to one embodiment, a lower wiring layer is formed by using a sidewall transfer process for forming a sidewall film having a closed loop along a sidewall of a sacrificed or dummy pattern and, after removing the sacrificed pattern to leave the sidewall film, selectively removing the base material with the sidewall film as a mask. One or more upper wiring layers are formed in an upper layer of the lower wiring layer via another layer using the sidewall transfer process. Etching for cutting each of the lower wiring layer and the upper wiring layers is collectively performed, whereby closed-loop cut is applied to the lower wiring layer and the upper wiring layers.

28. 发明授权

US08431919B2 Resistive change non-volatile semiconductor memory device 有权
标题翻译：电阻变化非易失性半导体存储器件
公开(公告)号：US08431919B2
公开(公告)日：2013-04-30
申请号：US12883593
申请日：2010-09-16
申请人： Hiroyuki Nansei
发明人： Hiroyuki Nansei
IPC分类号： H01L45/00
CPC分类号： H01L27/2481 , H01L27/2409 , H01L27/2472 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/1253 , H01L45/146 , H01L45/147
摘要： According to one embodiment, a non-volatile semiconductor memory device includes: a semiconductor substrate; a plurality of first lines; a plurality of second lines; and a plurality of non-volatile memory cells arranged at positions where the plurality of first lines intersect with the plurality of second lines, wherein each of the plurality of non-volatile memory cells includes a resistance change element and a rectifying element connected in series to the resistance change element, and a resistance change film continuously extending over the plurality of second lines is arranged between the plurality of first lines and the plurality of second lines, and the resistance change element includes a portion where the first line intersect with the second line in the resistance change film.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括：半导体衬底; 多条第一行; 多条第二线; 以及多个非易失性存储单元，其布置在所述多个第一线与所述多条第二线相交的位置处，其中所述多个非易失性存储单元中的每一个包括电阻变化元件和整流元件，电阻变化元件和连续延伸在多条第二线上的电阻变化膜配置在多条第一线和多条第二线之间，电阻变化元件包括第一线与第二线相交的部分在电阻变化膜。

29. 发明授权

US08143661B2 Memory cell system with charge trap 有权
标题翻译：带电荷陷阱的记忆体系统
公开(公告)号：US08143661B2
公开(公告)日：2012-03-27
申请号：US11539984
申请日：2006-10-10
申请人： Shenqing Fang , Rinji Sugino , Jayendra Bhakta , Takashi Orimoto , Hiroyuki Nansei , Yukio Hayakawa , Takayuki Maruyama , Hidehiko Shiraiwa , Kuo-Tung Chang , Lei Xue , Meng Ding , Amol Ramesh Joshi , YouSeok Suh , Harpreet Sachar
发明人： Shenqing Fang , Rinji Sugino , Jayendra Bhakta , Takashi Orimoto , Hiroyuki Nansei , Yukio Hayakawa , Takayuki Maruyama , Hidehiko Shiraiwa , Kuo-Tung Chang , Lei Xue , Meng Ding , Amol Ramesh Joshi , YouSeok Suh , Harpreet Sachar
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L21/28273 , H01L27/115 , H01L27/11568
摘要： A memory cell system is provided including a first insulator layer over a semiconductor substrate, a charge trap layer over the first insulator layer, and slot where the charge trap layer includes a second insulator layer having the characteristic of being grown.
摘要翻译：提供一种存储单元系统，包括半导体衬底上的第一绝缘体层，第一绝缘体层上的电荷陷阱层和电荷陷阱层包括具有生长特性的第二绝缘体层的槽。

30. 发明授权

US07888209B2 Non-volatile sonos-type memory device 有权
标题翻译：非挥发性声像型存储器件
公开(公告)号：US07888209B2
公开(公告)日：2011-02-15
申请号：US12574884
申请日：2009-10-07
申请人： Hiroyuki Nansei
发明人： Hiroyuki Nansei
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115 , H01L29/66833 , H01L29/792
摘要： A semiconductor memory device with the thickness of both a tunnel film and a top film provided thereon configured to be in the FN tunneling region (4 nm or more). Data retention characteristics can be improved by configuring both a tunnel film and a top film to have a thickness in the FN tunneling region. Secondly, a high-concentration impurity region of a conductivity type the same as that of the substrate is provided in a substrate region arranged between assist gates provided adjacently to each other. The aforementioned high-concentration impurity region makes a depletion layer extremely thin when bias is applied to the assist gates. Hot holes generated between bands in the depletion region are injected into a charge storage region and the holes and electrons make pairs and disappear, enabling easy data erasing.
摘要翻译：一种半导体存储器件，其具有设置在其中的隧道膜和顶膜的厚度，配置为处于FN隧穿区域（4nm以上）。通过配置隧道膜和顶部膜以在FN隧道区域中具有厚度可以改善数据保持特性。其次，在布置在彼此相邻设置的辅助栅之间的衬底区域中设置与衬底相同的导电类型的高浓度杂质区。当向辅助栅极施加偏压时，上述高浓度杂质区域使耗尽层非常薄。在耗尽区域中的带之间产生的热孔注入电荷存储区域，并且空穴和电子成对并消失，从而使数据清除容易。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式