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21. 发明授权

US5212104A Method for manufacturing an MOS transistor 失效
标题翻译：制造MOS晶体管的方法
公开(公告)号：US5212104A
公开(公告)日：1993-05-18
申请号：US848238
申请日：1992-03-09
申请人： Helmut Klose
发明人： Helmut Klose
IPC分类号： H01L29/78 , H01L21/336 , H01L29/10 , H01L29/423 , H01L29/772
CPC分类号： H01L29/7725 , H01L29/105 , H01L29/66636 , H01L29/78
摘要： A method for the manufacture of an MOS transistor. A channel region is produced by selective epitaxy on a substrate (1) doped with a first conductivity type, said channel region containing a delta-shaped layer (5) doped with the first conductivity type. Source region (13) and drain region (14) are formed, in particular, by drive-out from a doped glass layer (12).
摘要翻译：一种用于制造MOS晶体管的方法。通过在掺杂有第一导电类型的衬底（1）上的选择性外延生产沟道区，所述沟道区包含掺杂有第一导电类型的δ形层（5）。源区（13）和漏区（14）特别是通过从掺杂玻璃层（12）的驱出而形成。

22. 发明授权

US06637554B2 Rail brake element 失效
标题翻译：轨道制动元件
公开(公告)号：US06637554B2
公开(公告)日：2003-10-28
申请号：US10161045
申请日：2002-05-31
申请人： Helmut Klose
发明人： Helmut Klose
IPC分类号： B61H1300
CPC分类号： B61K7/04
摘要： A rail brake element, in particular in connection with rail brake buffer blocks, comprising a pair of clamping plates C-shaped in cross section and having upper and lower leg portions, the clamping plates engaging a rail head on opposite sides, at least one braking block element having a flat lower surface which engages the top surface of the rail head and two upper roof-like tapered surfaces, whereby the block element and the brake linings are pressed against the rail head, characterized in that the tapered surfaces of the block element have an angle relative to a horizontal plane of at least 20° and the block element and the clamping plates are dimensioned such that the end of the upper leg portions of the clamping plates have a significant distance from the upper edge of the associated tapered surface if the rail head is not worn.
摘要翻译：轨道制动元件，特别是与轨道制动缓冲块结合，包括一对横截面为C形的夹紧板，并具有上部和下部腿部，夹紧板与相对侧的轨道头部接合，至少一个制动阻挡元件具有与轨头的顶表面接合的平坦的下表面和两个上顶部顶部的锥形表面，由此阻挡元件和制动衬片被压靠在轨头上，其特征在于，块元件的锥形表面具有相对于至少20°的水平面的角度，并且阻挡元件和夹紧板的尺寸被设计成使得夹持板的上腿部的端部与相关联的锥形表面的上边缘具有相当大的距离，如果轨头不磨损。

23. 发明授权

US06583464B1 Memory cell using amorphous material to stabilize the boundary face between polycrystalline semiconductor material of a capacitor and monocrystalline semiconductor material of a transistor 有权
标题翻译：使用非晶材料的存储单元稳定电容器的多晶半导体材料与晶体管的单晶半导体材料之间的边界面
公开(公告)号：US06583464B1
公开(公告)日：2003-06-24
申请号：US09201733
申请日：1998-11-30
申请人： Emmerich Bertagnolli , Gustav Beckmann , Michael Bianco , Helmut Klose
发明人： Emmerich Bertagnolli , Gustav Beckmann , Michael Bianco , Helmut Klose
IPC分类号： H01L27108
CPC分类号： H01L27/10861 , H01L27/10829
摘要： A memory cell array has memory cells in which there is an electrical connection between a polycrystalline semiconductor material of a capacitor electrode and a monocrystalline semiconductor region. Islands made of an amorphous material are disposed in a vicinity of the electrical connection between the polycrystalline semiconductor material and the monocrystalline semiconductor region. The islands are produced in particular by thermally breaking up an amorphous layer which has been formed by thermal oxidation. The memory cell array is in particular a DRAM array with a trench capacitor.
摘要翻译：存储单元阵列具有存储单元，其中在电容器电极的多晶半导体材料和单晶半导体区域之间存在电连接。由非晶材料制成的岛状物设置在多晶半导体材料和单晶半导体区域之间的电连接附近。这些岛特别是通过热分解由热氧化形成的非晶层而产生的。存储单元阵列特别是具有沟槽电容器的DRAM阵列。

24. 发明授权

US06211019B1 Read-only memory cell device and method for its production 有权
标题翻译：只读存储单元器件及其生产方法
公开(公告)号：US06211019B1
公开(公告)日：2001-04-03
申请号：US09130051
申请日：1998-08-06
申请人： Helmut Klose , Emmerich Bertagnolli
发明人： Helmut Klose , Emmerich Bertagnolli
IPC分类号： H01L218234
CPC分类号： H01L27/1126 , H01L27/112
摘要： A read-only memory cell device includes a substrate formed of semiconductor material and having a main area. Memory cells in the vicinity of the main area are disposed in matrix form in columns and rows in a cell field. Each memory cell has in each case at least one MOS transistor with a source region, a drain region, a channel region, a gate dielectric and a gate electrode. The MOS transistors of a column are connected in series one after the other. Each column is connected to a bit line and the gate electrodes of the MOS transistors of a row are connected to a word line. The source and drain regions of the MOS transistors of a column are formed in source/drain webs running substantially parallel to one another at a predetermined spacing, are electrically insulated from one another, are produced from the semiconductor material of the substrate and have a predetermined web depth, starting from the main area of the substrate. The word lines for connection of the gate electrodes of the MOS transistors run transversely with respect to the longitudinal direction of the source/drain webs.
摘要翻译：只读存储单元器件包括由半导体材料形成并具有主区域的衬底。在主区域附近的存储单元以矩阵形式在单元格区域中的列和行中排列。每个存储单元在每种情况下都具有至少一个具有源极区，漏极区，沟道区，栅极电介质和栅电极的MOS晶体管。柱的MOS晶体管一个接一个地串联连接。每列连接到位线，并且一行的MOS晶体管的栅电极连接到字线。柱的MOS晶体管的源极和漏极区域以预定的间隔彼此电绝缘的方式形成在源极/漏极幅片中，彼此电绝缘，由基板的半导体材料制成，并且具有预定的纸幅深度，从基材的主要区域开始。用于连接MOS晶体管晶体管的栅电极的字线相对于源极/漏极引线的纵向方向横向延伸。

25. 发明授权

US6022786A Method for manufacturing a capacitor for a semiconductor arrangement 失效
标题翻译：半导体装置用电容器的制造方法
公开(公告)号：US6022786A
公开(公告)日：2000-02-08
申请号：US32484
申请日：1998-02-27
申请人： Martin Franosch , Wolfgang Hoenlein , Helmut Klose , Gerrit Lange , Volker Lehmann , Hans Reisinger , Herbert Schaefer , Reinhard Stengl , Hermann Wendt , Dietrich Widmann
发明人： Martin Franosch , Wolfgang Hoenlein , Helmut Klose , Gerrit Lange , Volker Lehmann , Hans Reisinger , Herbert Schaefer , Reinhard Stengl , Hermann Wendt , Dietrich Widmann
IPC分类号： H01L21/306 , H01L21/8242 , H01L27/108 , H01L21/20
CPC分类号： H01L27/10861
摘要： For manufacturing a capacitor, in particular for a dynamic memory cell arrangement, a trench is etched in a substrate. In the trench, a layer sequence is produced that contains, in alternating fashion, layers of doped silicon and germanium-containing layers. By anisotropic etching, the surface of the semiconductor substrate (12) is exposed in the region of the trench floor. The trenches are filled with a conductive support structure (20). The germanium-containing layers are removed selectively to the layers of doped silicon. The exposed surface of the layers of doped silicon (17) and of the support structure (20) are provided with a capacitor dielectric (22), onto which is applied a counter-electrode (23).
摘要翻译：为了制造电容器，特别是用于动态存储单元布置，在衬底中蚀刻沟槽。在沟槽中，产生层序列，其交替地包含掺杂的硅和含锗层的层。通过各向异性蚀刻，半导体衬底（12）的表面暴露在沟槽底板的区域中。沟槽填充有导电支撑结构（20）。含锗层被选择性地去除掺杂硅层。掺杂硅（17）和支撑结构（20）的层的暴露表面设置有电容器电介质（22），其上施加有对电极（23）。

26. 发明授权

US5741733A Method for the production of a three-dimensional circuit arrangement 失效
标题翻译：制作三维电路装置的方法
公开(公告)号：US5741733A
公开(公告)日：1998-04-21
申请号：US676164
申请日：1996-07-15
申请人： Emmerich Bertagnolli , Helmut Klose
发明人： Emmerich Bertagnolli , Helmut Klose
IPC分类号： H01L21/768 , H01L21/02 , H01L21/822 , H01L27/00 , H01L27/06 , H01L27/12 , H01L21/84 , H01L21/00
CPC分类号： H01L21/76898 , H01L21/8221 , H01L23/481 , H01L27/0688 , H01L2924/0002
摘要： To produce a three-dimensional circuit arrangement, a first substrate (1) is thinned, stacked onto a second substrate (2) and fixedly connected to the latter. The first substrate (1) and the second substrate (2) in this case each comprise circuit structures (12, 22) and metallization planes (13, 23). At least one first contact hole (16) and one second contact hole (4) are opened, which reach the metallization plane (13, 23) in the first substrate (1) and second substrate (2), respectively, the second contact hole (4) passing through the first substrate (1). The metallization planes (13, 23) of the two substrates (1, 2) are electrically connected to one another via a conductive layer (7).
摘要翻译： PCT No.PCT / DE95 / 00031 Sec。 371日期：1996年7月15日 102（e）日期1996年7月15日PCT提交1995年1月12日PCT公布。 WO95 / 19642 PCT出版物日期1995年7月20日为了制造三维电路装置，将第一衬底（1）变薄，层叠到第二衬底（2）上并且固定地连接到第二衬底（2）。在这种情况下，第一基板（1）和第二基板（2）分别包括电路结构（12,22）和金属化平面（13,23）。至少一个第一接触孔（16）和一个第二接触孔（4）分别到达第一基板（1）和第二基板（2）中的金属化平面（13,23），第二接触孔（4）穿过第一基板（1）。两个基板（1,2）的金属化平面（13,23）经由导电层（7）彼此电连接。

27. 发明授权

US5610531A Testing method for semiconductor circuit levels 失效
标题翻译：半导体电路级的测试方法
公开(公告)号：US5610531A
公开(公告)日：1997-03-11
申请号：US369391
申请日：1995-01-06
申请人： Werner Weber , Siegmar Koeppe , Helmut Klose , Holger Huebner
发明人： Werner Weber , Siegmar Koeppe , Helmut Klose , Holger Huebner
IPC分类号： G01R31/26 , G01R31/28 , H01L21/66 , H01L21/70 , H01L23/544
CPC分类号： H01L22/34 , H01L2924/0002
摘要： A function test is implemented for an individual circuit level (1) that is provided for vertical integration in a semiconductor component. Stacks of circuit levels respectively provided over or under this circuit level in the finished component are simulated as test heads (2, 3). These test heads are provided with terminal contacts for reversible contacting. The circuit level (1) under test is connected to these test heads (2, 3) during the function test, and the test heads are removed after the test.
摘要翻译：对于为半导体部件中的垂直集成提供的单独电路电平（1）实现功能测试。在完成的部件中分别设置在该电路电平以下或以下的电路电平的堆叠被模拟为测试头（2,3）。这些测试头设置有用于可逆接触的端子触点。在功能测试期间，被测线路电平（1）连接到这些测试头（2,3），并在测试之后移除测试头。

28. 发明授权

US5498567A Method for manufacturing a laterally limited, single-crystal region on a substrate and the employment thereof for the manufacture of an MOS transistor and a bipolar transistor 失效
标题翻译：用于制造衬底上的横向受限的单晶区域的方法及其用于制造MOS晶体管和双极晶体管的方法
公开(公告)号：US5498567A
公开(公告)日：1996-03-12
申请号：US379861
申请日：1995-04-03
申请人： Helmut Klose , Thomas Meister , Hans-Willi Meul , Reinhard Stengl
发明人： Helmut Klose , Thomas Meister , Hans-Willi Meul , Reinhard Stengl
IPC分类号： H01L21/76 , H01L21/20 , H01L21/331 , H01L21/336 , H01L29/73 , H01L29/732 , H01L29/78
CPC分类号： H01L29/66287 , H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02505 , H01L21/02532 , H01L21/02639 , H01L29/66651 , Y10S148/011
摘要： A method for the manufacture of a laterally limited single crystal region that is suitable for use as an active part of a transistor, including the steps of: a) providing a substrate made of a single crystal semiconductor material; b) forming a first layer on a surface of the substrate, said first layer being selectively etchable with respect to the substrate; c) forming a second layer on the first layer, the second layer being selectively etchable with respect to the first layer; d) providing an opening in the first and second layers so as to expose an area on the surface of the substrate; e) selectively etching the first layer with respect to the substrate and the second layer so as to provide an undercut between the second layer and the surface of the substrate; f) forming a single crystal region on the exposed surface of the substrate by selective epitaxy: g) doping the second layer such that parts of the second layer adjoining the single-crystal region acting as a channel region form a source region and a drain region; h) producing a gate dielectric at a surface of the single-crystal region; and i) forming a gate electrode that is insulated from the source and drain regions on the gate dielectric.
摘要翻译：一种用于制造适合用作晶体管的有源部分的横向受限单晶区域的方法，包括以下步骤：a）提供由单晶半导体材料制成的衬底; b）在所述衬底的表面上形成第一层，所述第一层相对于所述衬底可选择性地蚀刻; c）在所述第一层上形成第二层，所述第二层可相对于所述第一层选择性地蚀刻; d）在所述第一层和所述第二层中设置开口以暴露所述基底表面上的区域; e）相对于所述基底和所述第二层选择性地蚀刻所述第一层，以便在所述第二层和所述基底的表面之间提供底切; f）通过选择性外延在衬底的暴露表面上形成单晶区域：g）掺杂第二层，使得与用作沟道区的单晶区相邻的第二层的部分形成源区和漏区 ; h）在单晶区域的表面产生栅电介质; 以及i）形成与栅极电介质上的源极和漏极区域绝缘的栅电极。

29. 发明授权

US5460982A Method for manufacturing lateral bipolar transistors 失效
标题翻译：制造横向双极晶体管的方法
公开(公告)号：US5460982A
公开(公告)日：1995-10-24
申请号：US261263
申请日：1994-06-14
申请人： Emmerich Bertagnolli , Helmut Klose
发明人： Emmerich Bertagnolli , Helmut Klose
IPC分类号： H01L21/316 , H01L21/331 , H01L29/73 , H01L21/265 , H01L21/20 , H01L21/302 , H01L21/76
CPC分类号： H01L29/66265 , H01L29/7317
摘要： Manufacturing method for lateral bipolar transistors, wherein a highly doped emitter zone and collector zone as well as a base terminal zone are manufactured in a region in the silicon layer of a SOI substrate having a basic doping. The zones are manufactured by implantation using a mask. A base zone is then produced by implantation of dopant using the mask. The base zone is produced between the emitter zone and the collector zone.
摘要翻译：在具有基本掺杂的SOI衬底的硅层中的区域中制造横向双极晶体管的制造方法，其中高掺杂发射极区和集电极区以及基极端区。这些区域通过使用掩模的植入来制造。然后通过使用掩模注入掺杂剂来制备基区。基区在发射区和集电区之间产生。

30. 发明授权

US5450754A Pressure sensor 失效
标题翻译：压力传感器
公开(公告)号：US5450754A
公开(公告)日：1995-09-19
申请号：US207067
申请日：1994-03-08
申请人： Markus Biebl , Thomas Scheiter , Helmut Klose
发明人： Markus Biebl , Thomas Scheiter , Helmut Klose
IPC分类号： G01L1/14 , G01L9/00 , G01L9/12 , G01L19/02 , H01L29/84
CPC分类号： G01L19/02 , G01L9/0073
摘要： A pressure sensor comprises a matrix of diaphragms of polysilicon which, via a structure of electrical conductors, are arranged at an upper side of a silicon substrate for the determination of their variable electrical capacitance dependent on the pressure stressing. These diaphragms are present in at least two different sizes. Capacitances of these diaphragms of a same size are respectively connected to form a sub-unit such that basic capacitances of these sub-units are of a respectively same size.
摘要翻译：压力传感器包括多晶硅膜的矩阵，其经由电导体的结构布置在硅衬底的上侧，用于根据压力应力确定其可变电容。这些隔膜以至少两种不同的尺寸存在。相同尺寸的这些隔膜的电容分别连接以形成子单元，使得这些子单元的基本电容具有相同的尺寸。

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