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21. 发明授权

US5517657A Segment register file read and write pipeline 失效
标题翻译：段寄存器文件读写管道
公开(公告)号：US5517657A
公开(公告)日：1996-05-14
申请号：US220693
申请日：1994-03-30
申请人： Scott D. Rodgers , Kamla P. Huck
发明人： Scott D. Rodgers , Kamla P. Huck
IPC分类号： G06F9/30 , G06F9/38 , G06F13/00
CPC分类号： G06F9/3885 , G06F9/30101 , G06F9/3824 , G06F9/3867 , G06F9/3875
摘要： A mechanism and procedure for providing an efficient pipeline for reading and writing information to a multiple ported segment register file (SRF) in different pipestages. The present invention is operable, in one embodiment, within an address generation unit (AGU) of a processor and is implemented to write the SRF during a particular clock phase of a pipestage and to read to the SRF during another clock phase of another pipestage of the AGU pipeline of a pipelined processor. The read and write of different pipestages associated with separate instructions may occur within a same clock cycle. The write occurs before the read. By reading and writing to the AGU in alternate clock phases, the read and write operations of the SRF do not conflict even though they span different pipestages of the pipeline. Therefore, pipestages of the present invention are not in resource conflict over the SRF read and write operations which occur in a same clock cycle. Specifically, within the scope of the present invention, the SRF may be read during the low phase of a clock cycle while the SRF may be written during the high phase of a clock cycle for different instructions. Alternatively, the above phase relationships may be inverted.
摘要翻译：一种用于在不同管道中为多端口段寄存器文件（SRF）读取和写入信息的有效管道的机制和过程。本发明在一个实施例中可在处理器的地址生成单元（AGU）内操作，并且被实现为在分支的特定时钟相位期间写入SRF，并且在另一个分支的另一个时间段期间读取到SRF 流水线处理器的AGU管道。与单独指令相关联的不同管道的读取和写入可以在相同的时钟周期内进行。写入发生在读取之前。通过在备用时钟阶段读取和写入AGU，SRF的读取和写入操作即使跨越管道的不同管道也不会发生冲突。因此，在相同的时钟周期中发生的SRF读和写操作，本发明的分支管理不是资源冲突的。具体地说，在本发明的范围内，可以在时钟周期的低相位期间读取SRF，同时可以在针对不同指令的时钟周期的高相位期间写入SRF。或者，上述相位关系可以反转。

22. 发明申请

US20150381442A1 Reporting Platform Information Using A Secure Agent 有权
标题翻译：使用安全代理报告平台信息
公开(公告)号：US20150381442A1
公开(公告)日：2015-12-31
申请号：US14317288
申请日：2014-06-27
申请人： Brian Delgado , Brian S. Payne , Barry E. Huntley , Scott D. Rodgers
发明人： Brian Delgado , Brian S. Payne , Barry E. Huntley , Scott D. Rodgers
IPC分类号： H04L12/26 , G06F9/455 , H04L29/06
CPC分类号： H04L43/065 , G06F9/45558 , G06F2009/45591 , H04L63/0807
摘要： In an embodiment, a processor includes at least one core to execute instructions and a system management monitor to receive a platform query request from an external system, obtain status information regarding a configuration of one or more privileged resources of the processor, and report the status information to the external system. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括执行指令的至少一个核心和用于从外部系统接收平台查询请求的系统管理监视器，获得关于处理器的一个或多个特权资源的配置的状态信息，并且报告状态信息给外部系统。描述和要求保护其他实施例。

23. 发明申请

US20130219143A1 VIRTUALIZING PHYSICAL MEMORY IN A VIRTUAL MACHINE SYSTEM 审中-公开
公开(公告)号：US20130219143A1
公开(公告)日：2013-08-22
申请号：US13837822
申请日：2013-03-15
申请人： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Rajesh Sankaran Madukkarumukumana , Richard UhligQ , Lawrence Smith, III , Scott D. Rodgers
发明人： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Rajesh Sankaran Madukkarumukumana , Richard UhligQ , Lawrence Smith, III , Scott D. Rodgers
IPC分类号： G06F12/14
CPC分类号： G06F12/1483 , G06F9/45533 , G06F9/45558 , G06F12/109 , G06F2009/45583 , G06F2212/151 , G06F2212/152 , G06F2212/657
摘要： A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine.

24. 发明授权

US5636374A Method and apparatus for performing operations based upon the addresses of microinstructions 失效
标题翻译：基于微指令地址执行操作的方法和装置
公开(公告)号：US5636374A
公开(公告)日：1997-06-03
申请号：US470842
申请日：1995-06-06
申请人： Scott D. Rodgers , Keshavan K. Tiruvallur , Michael W. Rhodehamel , Kris G. Konigsfeld , Andrew F. Glew , Haitham Akkary , Milind A. Karnik , James A. Brayton
发明人： Scott D. Rodgers , Keshavan K. Tiruvallur , Michael W. Rhodehamel , Kris G. Konigsfeld , Andrew F. Glew , Haitham Akkary , Milind A. Karnik , James A. Brayton
IPC分类号： G06F9/312 , G06F12/08 , G06F12/10 , G06F9/30
CPC分类号： G06F9/30043 , G06F12/0891 , G06F12/1027
摘要： In a microprocessor, an apparatus and method for performing memory functions and issuing bus cycles. Special microinstructions are stored in microcode ROM. These microinstructions are used to perform the memory functions and to generate the special bus cycles. Initially, an address corresponding to a requested operation to be performed is generated for one of these special microinstructions. That special microinstruction, along with its address, is then transmitted over the bus to the various units of the microprocessor. When each of the units receives the microinstruction, it determines whether that microinstruction is to be ignored based on the address. If a particular unit ignores the microinstruction, the microinstruction is forwarded to subsequent units in the pipeline for processing. Otherwise, if that particular unit performs the requested operation as specified by the microinstruction's address.
摘要翻译：在微处理器中，用于执行存储器功能并发布总线周期的装置和方法。特殊的微指令存储在微码ROM中。这些微指令用于执行存储器功能并产生特殊的总线周期。最初，对于这些特殊微指令之一产生与要执行的请求操作相对应的地址。该特殊微指令及其地址然后通过总线传输到微处理器的各个单元。当每个单元接收微指令时，它根据该地址确定该微指令是否被忽略。如果特定单元忽略微指令，则微指令将转发到管道中的后续单元进行处理。否则，如果该特定单元执行由微指令的地址指定的请求操作。

25. 发明申请

US20150178078A1 INSTRUCTIONS AND LOGIC TO PROVIDE BASE REGISTER SWAP STATUS VERIFICATION FUNCTIONALITY 审中-公开
标题翻译：说明和逻辑提供基地注册表交换状态验证功能
公开(公告)号：US20150178078A1
公开(公告)日：2015-06-25
申请号：US14138054
申请日：2013-12-21
申请人： H. Peter Anvin , Scott D. Rodgers
发明人： H. Peter Anvin , Scott D. Rodgers
IPC分类号： G06F9/30 , G06F9/34
CPC分类号： G06F9/30032 , G06F9/30101 , G06F9/30123 , G06F9/30189
摘要： Instructions and logic provide base register swap status verification functionality. Embodiments include a processor having a first model specific register (MSR) to store a first base address corresponding to a segment for a first execution context and a second MSR to store a second base address corresponding to a segment for a second context. A third register stores a base register swap status field corresponding to the segment of the first and second contexts. A decode unit decodes a swap instruction and execution logic executes an exchange of the first MSR value and the second MSR value responsive to the swap instruction. The execution logic determines if said exchange of the first MSR value and the second MSR value completed successfully, and changes a value of the base register swap status field responsive to a determination that said exchange completed successfully.
摘要翻译：说明和逻辑提供基本寄存器交换状态验证功能。实施例包括具有第一模型特定寄存器（MSR）的处理器，用于存储对应于第一执行上下文的段的第一基地址和第二MSR，以存储对应于第二上下文的段的第二基地址。第三寄存器存储对应于第一和第二上下文的段的基址寄存器交换状态字段。解码单元解码交换指令，并且执行逻辑响应于交换指令执行第一MSR值和第二MSR值的交换。执行逻辑确定第一MSR值和第二MSR值的所述交换是否成功完成，并且响应于所述交换成功完成的确定而改变基本寄存器交换状态字段的值。

26. 发明申请

US20130326519A1 VIRTUAL MACHINE CONTROL STRUCTURE SHADOWING 审中-公开
标题翻译：虚拟机控制结构阴影
公开(公告)号：US20130326519A1
公开(公告)日：2013-12-05
申请号：US13995317
申请日：2011-12-30
申请人： Andrew V. Anderson , Gilbert Neiger , Scott D. Rodgers , Lawrence O. Smith, III , Richard A. Uhlig , Steven M. Bennett
发明人： Andrew V. Anderson , Gilbert Neiger , Scott D. Rodgers , Lawrence O. Smith, III , Richard A. Uhlig , Steven M. Bennett
IPC分类号： G06F9/455
CPC分类号： G06F9/45533
摘要： Embodiments of apparatuses and methods for processing virtual machine control structure shadowing are disclosed. In one embodiment, an apparatus includes instruction hardware, execution hardware, and control logic. The instruction hardware is to receive instructions. A first instruction is to transfer the processor from a root mode to a non-root mode. The non-root mode is for executing guest software in a virtual machine, where the processor is the return to root mode upon the detection of a virtual machine exit event. A second instruction is to access a data structure for controlling a virtual machine. The execution hardware is to execute the instructions. The control logic is to cause the processor to access a shadow data structure instead of the data structure, without returning to the root mode for the access to be performed, when the second instruction is executed in the non-root mode.
摘要翻译：公开了用于处理虚拟机控制结构阴影的装置和方法的实施例。在一个实施例中，装置包括指令硬件，执行硬件和控制逻辑。指令硬件是接收指令。第一条指令是将处理器从根模式转移到非根模式。非根模式用于在虚拟机中执行客户软件，其中处理器在检测虚拟机退出事件时返回到根模式。第二条指令是访问用于控制虚拟机的数据结构。执行硬件是执行指令。当以非根模式执行第二指令时，控制逻辑是使处理器不用返回到执行访问的根模式而不是数据结构而不是数据结构。

27. 发明申请

US20130219152A1 INSTRUCTION SET EXTENSION USING 3-BYTE ESCAPE OPCODE 有权
标题翻译：使用3字节ESCAPE操作码的指令集扩展
公开(公告)号：US20130219152A1
公开(公告)日：2013-08-22
申请号：US13844471
申请日：2013-03-15
申请人： James S. Coke , Peter J. Ruscito , Masood Tahir , David B. Jackson , Ves A. Naydenov , Scott D. Rodgers , Bret L. Toll , Frank Binns
发明人： James S. Coke , Peter J. Ruscito , Masood Tahir , David B. Jackson , Ves A. Naydenov , Scott D. Rodgers , Bret L. Toll , Frank Binns
IPC分类号： G06F9/30
CPC分类号： G06F9/30149 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30185
摘要： A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.
摘要翻译：公开了用于对可变长度指令集中的指令进行解码的方法，装置和系统。该指令是一组新的指令之一，它使用长度为两个字节的新的转义码值来指示第三个操作码字节包含新指令的指令特定操作码。定义新指令，可以使用相同的一组输入来确定新的转义操作码值之一的操作码映射中每个指令的长度，其中每个输入与确定新指令中的每个指令的长度相关操作码地图。对于至少一个实施例，在不评估指令特定操作码的情况下确定新指令之一的长度。

28. 发明申请

US20130174147A1 Low Latency Virtual Machine Page Table Management 有权
标题翻译：低延迟虚拟机页表管理
公开(公告)号：US20130174147A1
公开(公告)日：2013-07-04
申请号：US13341891
申请日：2011-12-30
申请人： Ravi L. Sahita , David M. Durham , Gilbert Neiger , Andrew V. Anderson , Scott D. Rodgers
发明人： Ravi L. Sahita , David M. Durham , Gilbert Neiger , Andrew V. Anderson , Scott D. Rodgers
IPC分类号： G06F9/455
CPC分类号： G06F9/45558 , G06F2009/45583
摘要： Various embodiments of this disclosure may describe method, apparatus and system for reducing system latency caused by switching memory page permission views between programs while still protecting critical regions of the memory from attacks of malwares. Other embodiments may be disclosed and claimed.
摘要翻译：本公开的各种实施例可以描述用于减少由程序之间切换存储器页面许可视图而引起的系统延迟的方法，装置和系统，同时仍保护存储器的关键区域免受恶意软件的攻击。可以公开和要求保护其他实施例。

29. 发明授权

US08161269B2 Determining length of instruction with address form field exclusive of evaluating instruction specific opcode in three byte escape opcode 有权
标题翻译：用三字节转义操作码来排除指令特定操作码的地址格式字段的指令长度
公开(公告)号：US08161269B2
公开(公告)日：2012-04-17
申请号：US13070908
申请日：2011-03-24
申请人： James S. Coke , Peter J. Ruscito , Masood Tahir , David B. Jackson , Ves A. Naydenov , Scott D. Rodgers , Bret L. Toll , Frank Binns
发明人： James S. Coke , Peter J. Ruscito , Masood Tahir , David B. Jackson , Ves A. Naydenov , Scott D. Rodgers , Bret L. Toll , Frank Binns
IPC分类号： G06F9/30
CPC分类号： G06F9/30149 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30185
摘要： A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.
摘要翻译：公开了用于对可变长度指令集中的指令进行解码的方法，装置和系统。该指令是一组新的指令之一，它使用长度为两个字节的新的转义码值来指示第三个操作码字节包含新指令的指令特定操作码。定义新指令，可以使用相同的一组输入来确定新的转义操作码值之一的操作码映射中每个指令的长度，其中每个输入与确定新指令中的每个指令的长度相关操作码地图。对于至少一个实施例，在不评估指令特定操作码的情况下确定新指令之一的长度。

30. 发明授权

US5749084A Address generation unit with segmented addresses in a microprocessor 失效
标题翻译：在微处理器中具有分段地址的地址生成单元
公开(公告)号：US5749084A
公开(公告)日：1998-05-05
申请号：US634092
申请日：1996-04-17
申请人： Kamla P. Huck , Scott D. Rodgers , Andrew F. Glew
发明人： Kamla P. Huck , Scott D. Rodgers , Andrew F. Glew
IPC分类号： G06F9/34 , G06F12/02 , G06F12/08 , G06F12/10 , G06F12/06
CPC分类号： G06F12/1036 , G06F12/0292
摘要： A processor having an address generation unit (AGU) for generating an address corresponding to an entry that is to be fetched. The AGU includes a segment register file for storing address segments, and a circuit for rearranging noncontiguous base and limit bit positions of a first address segment in order to generate a second address segment having all base and limit bits in a contiguous order. The AGU further includes a circuit for executing a single microinstruction to perform read and write operations on a selected field of the second address segments stored in the segment register file.
摘要翻译：一种具有地址生成单元（AGU）的处理器，用于生成与要获取的条目相对应的地址。 AGU包括用于存储地址段的段寄存器文件和用于重新排列第一地址段的不连续基地址和限制位位置的电路，以便生成具有连续顺序的所有基址和限制位的第二地址段。 AGU还包括用于执行单个微指令以对存储在段寄存器堆中的第二地址段的选定字段执行读和写操作的电路。

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