专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US06362510B1 Semiconductor topography having improved active device isolation and reduced dopant migration 有权
标题翻译：半导体形貌具有改进的有源器件隔离和减少掺杂剂迁移
公开(公告)号：US06362510B1
公开(公告)日：2002-03-26
申请号：US09206550
申请日：1998-12-07
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
IPC分类号： H01L2976
CPC分类号： H01L21/28202 , H01L21/02381 , H01L21/02532 , H01L21/02573 , H01L21/0262 , H01L21/02639 , H01L21/2822 , H01L21/762 , H01L29/1083 , H01L29/36 , H01L29/518 , H01L29/6659 , H01L29/66651
摘要： A method for fabricating an integrated circuit is presented wherein a semiconductor substrate is provided having a dielectric layer formed on its upper surface. A groove is formed in the dielectric layer that extends from the upper surface of the semiconductor substrate to the upper surface of the dielectric layer. A silicon epitaxial layer is then grown within the groove. Barrier atoms are incorporated into the silicon epitaxial layer concurrently with the epitaxial growth process.
摘要翻译：提出一种用于制造集成电路的方法，其中提供了在其上表面上形成有电介质层的半导体衬底。在从半导体衬底的上表面延伸到电介质层的上表面的电介质层中形成凹槽。然后在沟槽内生长硅外延层。阻挡原子与外延生长工艺同时并入硅外延层。

22. 发明授权

US06222230B1 Method of making an elevated source/drain with enhanced graded sidewalls for transistor scaling integrated with spacer formation 有权
标题翻译：用增强的梯度侧壁制造升高的源极/漏极的方法，用于与间隔物形成集成的晶体管缩放
公开(公告)号：US06222230B1
公开(公告)日：2001-04-24
申请号：US09204967
申请日：1998-12-03
申请人： Mark I. Gardner , H. Jim Fulford , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford , Charles E. May
IPC分类号： H01L2976
CPC分类号： H01L29/66621 , H01L21/823418 , H01L21/823468 , H01L21/823487 , H01L29/4232 , H01L29/4238
摘要： An integrated circuit and a method of making a transistor thereof are provided. In one aspect, the integrated circuit includes a substrate and a plurality of transistors positioned on a plurality of active areas of the substrate. Each of the transistors has a doped region positioned in the substrate, an insulating layer positioned in a tapered trench in the substrate that extends through and sub-divides the doped region into a first source/drain region and a second source/drain region. The insulating layer is channel-shaped with a base, a first upwardly sloping sidewall and a second upwardly sloping sidewall. A gate electrode is positioned on the insulating layer. The channel-shaped gate dielectric layer requires less horizontal substrate area, enabling higher packing density for a given substrate. The sloped sidewalls double as spacers, enabling process simplification.
摘要翻译：提供集成电路及其制造晶体管的方法。在一个方面，集成电路包括基板和位于基板的多个有源区上的多个晶体管。每个晶体管具有位于衬底中的掺杂区域，位于衬底中的锥形沟槽中的绝缘层，其延伸穿过并将掺杂区域划分为第一源极/漏极区域和第二源极/漏极区域。绝缘层是具有基部的沟道形状，第一向上倾斜的侧壁和第二向上倾斜的侧壁。栅电极位于绝缘层上。通道形栅极电介质层需要较少的水平衬底面积，使给定衬底具有更高的堆积密度。倾斜的侧壁作为间隔件加倍，使工艺简化。

23. 发明授权

US06207544B1 Method of fabricating ultra thin nitride spacers and device incorporating same 有权
标题翻译：制造超薄氮化物间隔物的方法和结合其的装置
公开(公告)号：US06207544B1
公开(公告)日：2001-03-27
申请号：US09207808
申请日：1998-12-09
申请人： Thien T. Nguyen , Mark I. Gardner , Charles E. May
发明人： Thien T. Nguyen , Mark I. Gardner , Charles E. May
IPC分类号： H01L213065
CPC分类号： H01L29/6659 , H01L21/28247 , H01L21/31116 , H01L29/6656
摘要： The present invention is directed to a method of fabricating very thin silicon nitride spacers on a transistor, and to a device comprising such spacers. In one illustrative embodiment, the method comprises forming a gate dielectric above a surface of a semiconducting substrate, forming a gate conductor above the gate dielectric, and forming a layer of silicon nitride above the substrate. The method further comprises performing at least one anisotropic etching process on the layer of silicon nitride using an etching recipe comprised of helium (He), sulfur hexafluoride (SF6) and hydrogen bromide (HBr). The transistor of the present invention is comprised of a gate dielectric positioned above the surface of a semiconducting substrate and a gate conductor positioned above the gate dielectric. The transistor further comprises a plurality of source/drain regions formed in the substrate adjacent the gate dielectric and a plurality of sidewall spacers comprised of silicon nitride, each of the sidewall spacers having a thickness that ranges from approximately 200-350 Å.
摘要翻译：本发明涉及一种在晶体管上制造非常薄的氮化硅间隔物的方法以及包括这种间隔物的装置。在一个说明性实施例中，该方法包括在半导体衬底的表面上形成栅极电介质，在栅极电介质上形成栅极导体，并在衬底上方形成氮化硅层。该方法还包括使用由氦（He），六氟化硫（SF 6）和溴化氢（HBr）组成的蚀刻配方对氮化硅层进行至少一个各向异性蚀刻工艺。本发明的晶体管包括位于半导体衬底的表面上方的栅极电介质和位于栅极电介质上方的栅极导体。晶体管还包括形成在邻近栅极电介质的衬底中的多个源极/漏极区域和由氮化硅构成的多个侧壁间隔物，每个侧壁间隔物的厚度范围为约200-350埃。

24. 发明授权

US06188106B1 MOSFET having a highly doped channel liner and a dopant seal to provide enhanced device properties 有权
标题翻译： MOSFET具有高度掺杂的沟道衬垫和掺杂剂密封，以提供增强的器件特性
公开(公告)号：US06188106B1
公开(公告)日：2001-02-13
申请号：US09146410
申请日：1998-09-03
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
IPC分类号： H01L2978
CPC分类号： H01L29/51 , H01L21/26533 , H01L29/0649 , H01L29/1079 , H01L29/665 , H01L29/6659
摘要： A fabrication process and integrated circuit are provided in which a transistor having increased resistance to punchthrough and decreased channel capacitance is formed. A liner layer is formed within the active region of a transistor to minimize punchthrough. A barrier layer is then formed between the liner layer and the upper surface of the semiconductor substrate. The barrier layer preferably inhibits migration of the liner ions into the junction and channel regions of the transistors during subsequent processing steps. Such migration could deleteriously affect transistor function by, e.g., increasing the threshold voltage and thus decreasing the drive current. The barrier layer also preferably facilitates formation of shallow junctions. In an embodiment, the liner layer may include p-type ions such as boron and the barrier layer may include nitrogen implanted into the semiconductor substrate. Alternatively, the barrier layer may include nitrogen-incorporated epitaxially grown silicon.
摘要翻译：提供一种制造工艺和集成电路，其中形成具有增加的穿透电阻和降低的沟道电容的晶体管。在晶体管的有源区内形成衬垫层以最小化穿透。然后在衬垫层和半导体衬底的上表面之间形成阻挡层。阻挡层优选地在随后的处理步骤期间抑制衬里离子迁移到晶体管的结和沟道区中。这种迁移可以通过例如增加阈值电压并从而降低驱动电流来有害地影响晶体管功能。阻挡层还优选有利于形成浅结。在一个实施例中，衬垫层可以包括诸如硼的p型离子，并且阻挡层可以包括注入到半导体衬底中的氮。或者，阻挡层可以包括掺入氮的外延生长的硅。

25. 发明授权

US6159804A Disposable sidewall oxidation fabrication method for making a transistor having an ultra short channel length 失效
标题翻译：制造具有超短沟道长度的晶体管的一次性侧壁氧化制造方法
公开(公告)号：US6159804A
公开(公告)日：2000-12-12
申请号：US145663
申请日：1998-09-02
申请人： Mark I. Gardner , H. Jim Fulford , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford , Charles E. May
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8234 , H01L29/72
CPC分类号： H01L29/66659 , H01L21/28132 , H01L21/823425 , H01L21/823468
摘要： The present invention is directed to a method of making a transistor having a very short channel length. The method generally comprises forming a plurality of process layers above a surface of a semiconducting substrate, one of the process layers being comprised of a gate dielectric material and another of the process layers being comprised of a gate conductor material. The method further comprises patterning the plurality of process layers to define an opening and forming a first sidewall spacer in the opening adjacent at least the process layer comprised of a gate conductor material. The method continues with the formation of a gate conductor mask by oxidation of a portion of at least one of the process layers other than those layers comprised of a gate dielectric material and the gate conductor material. A portion of the process layer comprised of a gate conductor material is then removed to define a gate conductor positioned beneath the gate conductor mask, followed by the formation of a second sidewall spacer adjacent the gate conductor. Thereafter, at least one source/drain region is formed to complete the transistor formation. The present invention further comprises a transistor having a channel length of less than 1000 .ANG..
摘要翻译：本发明涉及一种制造具有非常短的通道长度的晶体管的方法。该方法通常包括在半导体衬底的表面上方形成多个工艺层，其中一个工艺层由栅极电介质材料构成，另一个工艺层由栅极导体材料构成。该方法还包括对多个处理层进行图案化以限定开口，并且在开口中形成邻近至少由栅极导体材料构成的工艺层的第一侧壁间隔物。该方法继续通过除了由栅极电介质材料和栅极导体材料构成的那些层之外的至少一个工艺层的一部分的氧化形成栅极导体掩模。然后移除由栅极导体材料构成的工艺层的一部分，以限定位于栅极导体掩模下方的栅极导体，随后形成邻近栅极导体的第二侧壁间隔物。此后，形成至少一个源极/漏极区以完成晶体管的形成。本发明还包括具有小于1000安培的通道长度的晶体管。

26. 发明授权

US6090694A Local interconnect patterning and contact formation 失效
标题翻译：局部互连图案和接触形成
公开(公告)号：US6090694A
公开(公告)日：2000-07-18
申请号：US991742
申请日：1997-12-16
申请人： Fred N. Hause , Charles E. May , Mark I. Gardner
发明人： Fred N. Hause , Charles E. May , Mark I. Gardner
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76802 , H01L21/76832 , Y10S438/952
摘要： A method for forming a semiconductor device to produce a more distortion free via for interconnecting levels within a device or forming a connection between an external surface and an internal layer within a device includes the step of substituting a material similar to an etch stop adjacent one of the layers for the ARC. In other words, an etch stop is placed over the metal layer formed on a layer within the device. This is followed by a layer of silicon dioxide (SiO.sub.2) and then by a layer of material similar to the etch stop. Photoresist is placed on the layer of material similar to etch stop. The photoresist is exposed to light to form the location of the vias. The layer of material similar to etch stop, and the SiO.sub.2 layer are then removed in separate etching steps to form the via pathway from the resist to the etch stop adjacent the metal of the layer selected to be interconnected by the via. The resist can then be removed. This leaves the material similar to the etch stop located adjacent one surface of the SiO.sub.2 layer, and leaves the etch stop covering the metal in the via opening. One etch step can now be used to remove the etch stop covering the metal in the via opening and to remove the material similar to the etch stop located on the SiO.sub.2.
摘要翻译：用于形成半导体器件以产生用于在器件内互连电平或形成器件中的外表面和内部层之间的连接的无失真通孔的方法包括以下步骤：将与蚀刻停止相邻的材料 ARC的层。换句话说，蚀刻停止放置在形成在器件内的层上的金属层上。之后是二氧化硅层（SiO 2），然后是与蚀刻停止层相似的材料层。光刻胶放置在与蚀刻停止相似的材料层上。光致抗蚀剂暴露于光以形成通孔的位置。类似于蚀刻停止的材料层，然后在单独的蚀刻步骤中去除SiO 2层，以形成从抗蚀剂到蚀刻停止件的通孔路径，该蚀刻停止件邻近选定为由通孔相互连接的层的金属。然后可以除去抗蚀剂。这使得材料类似于位于SiO 2层的一个表面附近的蚀刻停止层，并且使蚀刻停止件覆盖通孔孔中的金属。现在可以使用一个蚀刻步骤去除覆盖通孔开口中的金属的蚀刻停止层，并且去除类似于位于SiO 2上的蚀刻停止层的材料。

27. 发明授权

US5882983A Trench isolation structure partially bound between a pair of low K dielectric structures 失效
标题翻译：沟槽隔离结构部分地结合在一对低K电介质结构之间
公开(公告)号：US5882983A
公开(公告)日：1999-03-16
申请号：US994143
申请日：1997-12-19
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
IPC分类号： H01L21/762 , H01L21/326 , H01L21/76
CPC分类号： H01L21/76237
摘要： A process is provided for forming to dielectric structures having a relatively low dielectric constant arranged adjacent to the opposed lateral edges of a trench isolation structure. In an embodiment, an opening is etched vertically through a masking layer arranged upon a semiconductor substrate, thereby exposing the surface of the substrate. A patterned photoresist layer is formed upon the masking layer using optical lithography to define the region to be etched. Sidewall spacers made of a low K dielectric material are formed upon the opposed sidewall surfaces of the masking layer within the opening. The sidewall spacers are formed by CVD depositing a dielectric material within the opening and anisotropically etching the dielectric material until only a pre-defined thickness of the material remains upon the masking layer sidewall surfaces. Thereafter, a trench defined between the exposed lateral edges of the sidewall spacers is formed within the substrate. The sidewall spacers permit the lateral width of the spacers to be reduced below the minimum lateral dimension definable using lithography. A trench dielectric is formed within the trench such that the upper portion of the dielectric is bound by the sidewall spacers on opposite ends. The resulting trench isolation structure is less likely to experience current leakage when operating an ensuing integrated circuit which employs the isolation structure.
摘要翻译：提供了一种用于形成具有邻近沟槽隔离结构的相对侧边缘布置的相对低的介电常数的电介质结构的工艺。在一个实施例中，通过布置在半导体衬底上的掩模层垂直蚀刻开口，从而暴露衬底的表面。使用光刻法在掩模层上形成图案化的光致抗蚀剂层，以限定待蚀刻的区域。由低K电介质材料制成的侧壁隔离物形成在开口内的掩蔽层的相对的侧壁表面上。通过在开口内CVD沉积电介质材料并各向异性地蚀刻电介质材料形成侧壁间隔物，直到材料的预定厚度仅保留在掩模层侧壁表面上为止。此后，在衬底内形成限定在侧壁间隔物的暴露的横向边缘之间的沟槽。侧壁间隔件允许间隔物的横向宽度减小到使用光刻可定义的最小横向尺寸以下。在沟槽内形成沟槽电介质，使得电介质的上部由相对端上的侧壁间隔件结合。当使用隔离结构的随后集成电路进行操作时，所得到的沟槽隔离结构不太可能经历电流泄漏。

28. 发明授权

US06420220B1 Method of forming electrode for high performance semiconductor devices 有权
标题翻译：形成高性能半导体器件电极的方法
公开(公告)号：US06420220B1
公开(公告)日：2002-07-16
申请号：US09292913
申请日：1999-04-16
申请人： Mark I. Gardner , H. Jim Fulford , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford , Charles E. May
IPC分类号： H01L2100
CPC分类号： H01L21/28052 , H01L21/823835 , H01L21/82385
摘要： A method is provided for fabricating a semiconductor device, the method including forming a dielectric layer above a structure, forming a silicidable layer above the dielectric layer and forming a conductive layer above the silicidable layer. The method also includes forming a silicided layer by siliciding a portion of the conductive layer using at least a portion of the silicidable layer and forming a gate conductor having sides by patterning the silicided layer and the conductive layer.
摘要翻译：提供一种用于制造半导体器件的方法，该方法包括在结构之上形成电介质层，在介电层上方形成可硅化层，并在硅化层之上形成导电层。该方法还包括通过使用可硅化层的至少一部分硅化一部分导电层并通过图案化硅化物层和导电层形成具有侧面的栅极导体来形成硅化物层。

29. 发明授权

US06403445B1 Enhanced trench isolation structure 失效
标题翻译：增强沟槽隔离结构
公开(公告)号：US06403445B1
公开(公告)日：2002-06-11
申请号：US09286729
申请日：1999-04-06
申请人： Mark I. Gardner , Frederick N. Hause , Charles E. May
发明人： Mark I. Gardner , Frederick N. Hause , Charles E. May
IPC分类号： H01L21762
CPC分类号： H01L21/76888 , H01L21/76224 , H01L21/76834 , H01L21/76895 , H01L21/823878
摘要： An improved method of trench isolation formation includes, for one embodiment, applying a polysilicon layer above a planarized trench, and converting the polysilicon to oxide prior to etching the active areas. This converted oxide is denser than the materials usually used to fill the trench, such as TEOS, and results in less over-etching of the trench isolation region. The quality of the dielectric isolation is consequently improved, and in particular, less leakage current flows across the trench isolation region. Moreover, less leakage current flows from a subsequently formed local interconnect layer.
摘要翻译：对于一个实施例，沟槽隔离形成的改进方法包括在平坦化沟槽之上施加多晶硅层，并且在刻蚀有源区之前将多晶硅转化为氧化物。这种转化的氧化物比通常用于填充沟槽（例如TEOS）的材料更致密，并且导致较少的沟槽隔离区的过蚀刻。因此，电介质隔离的质量得到改善，特别是较小的漏电流流过沟槽隔离区。此外，较少的漏电流从随后形成的局部互连层流出。

30. 发明授权

US06268637B1 Method of making air gap isolation by making a lateral EPI bridge for low K isolation advanced CMOS fabrication 有权
标题翻译：通过制造用于低K隔离高级CMOS制造的横向EPI桥来制造气隙隔离的方法
公开(公告)号：US06268637B1
公开(公告)日：2001-07-31
申请号：US09178080
申请日：1998-10-22
申请人： Mark I. Gardner , Frederick N. Hause , Charles E. May
发明人： Mark I. Gardner , Frederick N. Hause , Charles E. May
IPC分类号： H01L2900
CPC分类号： H01L21/823878 , H01L21/764
摘要： An isolation structure and a method of making the same are provided. In one aspect, the method includes the steps of forming a trench in a substrate and forming a first insulating sidewall in the trench and a second insulating in the trench in spaced-apart relation to the first insulating sidewall. A bridge layer is formed between the first and the second sidewalls. The bridge layer, the first and second sidewalls, and the substrate define an air gap in the trench. The isolation structure exhibits a low capacitance in a narrow structure. Scaling is enhanced and the potential for parasitic leakage current due to non-planarity is reduced.
摘要翻译：提供隔离结构及其制造方法。在一个方面，该方法包括以下步骤：在衬底中形成沟槽并在沟槽中形成第一绝缘侧壁，并在沟槽中形成与第一绝缘侧壁间隔开的第二绝缘体。桥接层形成在第一和第二侧壁之间。桥接层，第一和第二侧壁以及衬底在沟槽中限定气隙。隔离结构在窄结构中表现出低电容。缩放增强，并且由于非平面性引起的寄生漏电流的可能性降低。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式