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21. 发明申请

US20120272009A1 METHODS AND APPARATUS FOR HANDLING A CACHE MISS 有权
标题翻译：处理缓存错误的方法和设备
公开(公告)号：US20120272009A1
公开(公告)日：2012-10-25
申请号：US13540684
申请日：2012-07-03
申请人： John D. Irish , Chad B. McBride , Andrew H. Wottreng
发明人： John D. Irish , Chad B. McBride , Andrew H. Wottreng
IPC分类号： G06F12/08
CPC分类号： G06F12/126 , G06F12/0862 , G06F12/1027 , G06F12/127 , G06F2212/654
摘要： In a first aspect, a first method is provided. The first method includes the steps of (1) providing a cache having a plurality of cache entries, each entry adapted to store data, wherein the cache is adapted to be accessed by hardware and software in a first operational mode; (2) determining an absence of desired data in one of the plurality of cache entries; (3) determining a status based on a current operational mode and a value of hint-lock bits associated with the plurality of cache entries; and (4) determining availability of at least one of the cache entries based on the status, wherein availability of a cache entry indicates that data stored in the cache entry can be replaced. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了第一种方法。第一种方法包括以下步骤：（1）提供具有多个高速缓存条目的高速缓存，每个条目适于存储数据，其中高速缓存适于在第一操作模式中由硬件和软件进行访问; （2）确定在所述多个高速缓存条目之一中不存在期望数据; （3）基于当前操作模式和与所述多个高速缓存条目相关联的提示锁定位的值来确定状态; 以及（4）基于所述状态来确定所述高速缓存条目中的至少一个的可用性，其中高速缓存条目的可用性指示可以替换存储在所述高速缓存条目中的数据。提供了许多其他方面。

22. 发明申请

US20100188126A1 Voltage Controlled Duty Cycle and Non-Overlapping Clock Generation Implementation 审中-公开
标题翻译：电压控制占空比和非重叠时钟发生实现
公开(公告)号：US20100188126A1
公开(公告)日：2010-07-29
申请号：US12359583
申请日：2009-01-26
申请人： Sharon W. Cheung , Chad B. McBride , Cheng-Fu Frank Tsai , Jianguo Yao
发明人： Sharon W. Cheung , Chad B. McBride , Cheng-Fu Frank Tsai , Jianguo Yao
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A method, system and apparatus for controlling the duty cycle of a clock to optimize duty cycle correction and non over-lapping clock generation. The first system generates a reference voltage and one or more clock signals. A comparison is made between the DC level of an output clock and the reference voltage. A correct duty cycle of the clock signal is equal to a predetermined ratio of high time to low time, within an acceptable margin, wherein the ratio of high time to low time is derived from a first resistor and a second resistor. A second system is developed to generate non-overlap clock signals with non-overlap gap control, wherein a reference voltage of a first circuit network is the reference voltage of a second circuit network; thereby generating a single reference signal for the non-overlap circuit network.
摘要翻译：用于控制时钟的占空比以优化占空比校正和非重叠时钟生成的方法，系统和装置。第一个系统产生参考电压和一个或多个时钟信号。比较输出时钟的直流电平和参考电压。在可接受的余量内，时钟信号的正确占空比等于高时间到低时间的预定比率，其中从第一电阻器和第二电阻器导出高时间与低电平的比率。开发了第二系统以产生具有非重叠间隙控制的非重叠时钟信号，其中第一电路网络的参考电压是第二电路网络的参考电压; 从而生成用于非重叠电路网络的单个参考信号。

23. 发明申请

US20080059672A1 Methods and Apparatus for Scheduling Prioritized Commands on a Bus 审中-公开
标题翻译：在总线上调度优先级命令的方法和装置
公开(公告)号：US20080059672A1
公开(公告)日：2008-03-06
申请号：US11468377
申请日：2006-08-30
申请人： John D. Irish , Chad B. McBride , David A. Norgaard , Dorothy M. Thelen
发明人： John D. Irish , Chad B. McBride , David A. Norgaard , Dorothy M. Thelen
IPC分类号： G06F13/36
CPC分类号： G06F13/36
摘要： In a first aspect, a first method of scheduling a command to be issued on a bus is provided. The first method includes the steps of (1) associating an address and priority with each of a plurality of commands to be issued on the bus, wherein the priority associated with each command is based on the address associated with the command; (2) updating the priority associated with each command after a predetermined time period; and (3) from the plurality of commands, selecting a command to be issued on the bus based on the address and updated priority associated with the command to be issued. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种调度在总线上发出的命令的方法。第一种方法包括以下步骤：（1）将地址和优先级与要在总线上发出的多个命令中的每一个相关联，其中与每个命令相关联的优先级基于与该命令相关联的地址; （2）在预定时间段之后更新与每个命令相关联的优先级; 和（3）根据多个命令，基于与要发出的命令相关联的地址和更新的优先级来选择要在总线上发出的命令。提供了许多其他方面。

24. 发明申请

US20070283121A1 Method and Apparatus for Handling Concurrent Address Translation Cache Misses and Hits Under Those Misses While Maintaining Command Order 失效
标题翻译：在维护命令顺序的同时处理并发地址转换缓存缺失和命中的方法和装置
公开(公告)号：US20070283121A1
公开(公告)日：2007-12-06
申请号：US11420884
申请日：2006-05-30
申请人： John D. Irish , Chad B. McBride , Ibrahim A. Ouda , Andrew H. Wottreng
发明人： John D. Irish , Chad B. McBride , Ibrahim A. Ouda , Andrew H. Wottreng
IPC分类号： G06F12/00
CPC分类号： G06F12/1027
摘要： A method and apparatus handles concurrent address translation cache misses and hits under those misses while maintaining command order based upon virtual channel. Commands are stored in a command processing unit that maintains ordering of the commands. A command buffer index is assigned to each address being sent from the command processing unit to an address translation unit. When an address translation cache miss occurs, a memory fetch request is sent. The CBI is passed back to the command processing unit with a signal to indicate that the fetch request has completed. The command processing unit uses the CBI to locate the command and address to be reissued to the address translation unit.
摘要翻译：一种方法和装置处理并发的地址转换高速缓存未命中和命中命中，同时维持基于虚拟通道的命令顺序。命令存储在维护命令排序的命令处理单元中。将命令缓冲器索引分配给从命令处理单元发送到地址转换单元的每个地址。当发生地址转换高速缓存未命中时，发送存储器提取请求。 CBI被传回给具有信号的命令处理单元，以指示提取请求已经完成。命令处理单元使用CBI将要重新发布的命令和地址定位到地址转换单元。

25. 发明授权

US06601122B1 Exceptions and interrupts with dynamic priority and vector routing 失效
标题翻译：具有动态优先级和向量路由的异常和中断
公开(公告)号：US06601122B1
公开(公告)日：2003-07-29
申请号：US09550753
申请日：2000-04-17
申请人： Robert N. Broberg, III , Jonathan W. Byrn , Chad B. McBride , Gary P. McClannahan
发明人： Robert N. Broberg, III , Jonathan W. Byrn , Chad B. McBride , Gary P. McClannahan
IPC分类号： G06F1324
CPC分类号： G06F9/4812
摘要： A method of handling an interrupt request in a computer system by programmably setting an override address associated with a specific interrupt service routine, and servicing an interrupt request based on the override address, which is different from a power-on default address associated with the same interrupt service routine. The method may determine whether the interrupt service routine is critical and, if so, set the override address to a physical location in the on-chip memory of the processing unit, instead of in the off-chip memory (RAM). Override address registers are accessed via the special purpose registers of the processing unit. A validation bit may be turned on in response to the setting of the override address, with both the default address and the override address being provided as separate inputs to a multiplexing device controlled by the validation bit. The override address is forwarded from the multiplexing device to an instruction fetch unit whenever the validation bit has been set. The result is decreased latency associated with interrupt handling, and increased flexibility in user definition of critical versus non-critical interrupts.
摘要翻译：一种在计算机系统中处理中断请求的方法，通过可编程地设置与特定中断服务程序相关联的覆盖地址，并且基于覆盖地址来服务中断请求，所述覆盖地址不同于与其相关联的开机默认地址中断服务程序。该方法可以确定中断服务程序是否是关键的，如果是，则将覆盖地址设置为处理单元的片上存储器中的物理位置，而不是在片外存储器（RAM）中。通过处理单元的专用寄存器访问覆盖地址寄存器。响应于覆盖地址的设置，可以打开验证位，将默认地址和覆盖地址作为单独输入提供给由验证位控制的多路复用器件。每当验证位被设置时，覆盖地址从多路复用器件转发到指令获取单元。结果是与中断处理相关联的延迟降低，以及用户对关键中断与非关键中断的定义的灵活性增加。

26. 发明授权

US06453366B1 Method and apparatus for direct memory access (DMA) with dataflow blocking for users 失效
标题翻译：用于直接存储器访问（DMA）的方法和装置，具有用户的数据流阻塞
公开(公告)号：US06453366B1
公开(公告)日：2002-09-17
申请号：US09251043
申请日：1999-02-18
申请人： Robert Neal Carlton Broberg, III , Jonathan William Byrn , Chad B. McBride , Gary Paul McClannahan
发明人： Robert Neal Carlton Broberg, III , Jonathan William Byrn , Chad B. McBride , Gary Paul McClannahan
IPC分类号： G06F1328
CPC分类号： G06F13/28
摘要： A method and apparatus are provided for implementing direct memory access (DMA) with dataflow blocking for users for processing data communications in a communications system. A DMA starting address register receives an initial DMA starting address and a DMA length register receives an initial DMA length. A DMA state machine receives a control input for starting the DMA. The DMA state machine updates the DMA starting address to provide a current DMA starting address. The DMA state machine loads a DMA ending address. A DMA blocking logic receives the current DMA starting address and the DMA ending address and blocks received memory requests only within a current active DMA region.
摘要翻译：提供了一种用于实现具有用于处理通信系统中的数据通信的用户的数据流阻塞的直接存储器访问（DMA）的方法和装置。 DMA起始地址寄存器接收初始DMA起始地址，DMA长度寄存器接收初始DMA长度。 DMA状态机接收用于启动DMA的控制输入。 DMA状态机更新DMA起始地址以提供当前的DMA起始地址。 DMA状态机加载DMA结束地址。 DMA阻塞逻辑接收当前DMA起始地址和DMA结束地址，并仅在当前活动DMA区域内阻止接收到的存储器请求。

27. 发明授权

US08589630B2 Methods and apparatus for handling a cache miss 有权
标题翻译：用于处理高速缓存未命中的方法和装置
公开(公告)号：US08589630B2
公开(公告)日：2013-11-19
申请号：US13540684
申请日：2012-07-03
申请人： John D. Irish , Chad B. McBride , Andrew H. Wottreng
发明人： John D. Irish , Chad B. McBride , Andrew H. Wottreng
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/126 , G06F12/0862 , G06F12/1027 , G06F12/127 , G06F2212/654
摘要： In a first aspect, a first method is provided. The first method includes the steps of (1) providing a cache having a plurality of cache entries, each entry adapted to store data, wherein the cache is adapted to be accessed by hardware and software in a first operational mode; (2) determining an absence of desired data in one of the plurality of cache entries; (3) determining a status based on a current operational mode and a value of hint-lock bits associated with the plurality of cache entries; and (4) determining availability of at least one of the cache entries based on the status, wherein availability of a cache entry indicates that data stored in the cache entry can be replaced. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了第一种方法。第一种方法包括以下步骤：（1）提供具有多个高速缓存条目的高速缓存，每个条目适于存储数据，其中高速缓存适于在第一操作模式中由硬件和软件进行访问; （2）确定在所述多个高速缓存条目之一中不存在期望数据; （3）基于当前操作模式和与所述多个高速缓存条目相关联的提示锁定位的值来确定状态; 以及（4）基于所述状态来确定所述高速缓存条目中的至少一个的可用性，其中高速缓存条目的可用性指示可以替换存储在所述高速缓存条目中的数据。提供了许多其他方面。

28. 发明授权

US08327075B2 Methods and apparatus for handling a cache miss 失效
标题翻译：用于处理高速缓存未命中的方法和装置
公开(公告)号：US08327075B2
公开(公告)日：2012-12-04
申请号：US11297312
申请日：2005-12-08
申请人： John D. Irish , Chad B. McBride , Andrew H. Wottreng
发明人： John D. Irish , Chad B. McBride , Andrew H. Wottreng
IPC分类号： G06F12/12
CPC分类号： G06F12/126 , G06F12/0862 , G06F12/1027 , G06F12/127 , G06F2212/654
摘要： In a first aspect, a first method is provided. The first method includes the steps of (1) providing a cache having a plurality of cache entries, each entry adapted to store data, wherein the cache is adapted to be accessed by hardware and software in a first operational mode; (2) determining an absence of desired data in one of the plurality of cache entries; (3) determining a status based on a current operational mode and a value of hint-lock bits associated with the plurality of cache entries; and (4) determining availability of at least one of the cache entries based on the status, wherein availability of a cache entry indicates that data stored in the cache entry can be replaced. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了第一种方法。第一种方法包括以下步骤：（1）提供具有多个高速缓存条目的高速缓存，每个条目适于存储数据，其中高速缓存适于在第一操作模式中由硬件和软件进行访问; （2）确定在所述多个高速缓存条目之一中不存在期望数据; （3）基于当前操作模式和与所述多个高速缓存条目相关联的提示锁定位的值来确定状态; 以及（4）基于所述状态来确定所述高速缓存条目中的至少一个的可用性，其中高速缓存条目的可用性指示可以替换存储在所述高速缓存条目中的数据。提供了许多其他方面。

29. 发明授权

US08127082B2 Method and apparatus for allowing uninterrupted address translations while performing address translation cache invalidates and other cache operations 失效
标题翻译：允许不间断地址转换同时执行地址转换高速缓存无效和其它高速缓存操作的方法和装置
公开(公告)号：US08127082B2
公开(公告)日：2012-02-28
申请号：US11344900
申请日：2006-02-01
申请人： Chad B. McBride , Andrew H. Wottreng , John D. Irish
发明人： Chad B. McBride , Andrew H. Wottreng , John D. Irish
IPC分类号： G06F12/00
CPC分类号： G06F12/1027
摘要： A method and apparatus for allowing multiple devices access to an address translation cache while cache maintenance operations are occurring at the same time. By interleaving the commands requiring address translation with maintenance operations that may normally take many cycles, address translation requests may have faster access to the address translation cache than if maintenance operations were allowed to stall commands requiring address translations until the maintenance operation was completed.
摘要翻译：一种用于允许多个设备访问地址转换高速缓存并且同时进行高速缓存维护操作的方法和装置。通过将需要地址转换的命令与可能通常需要许多周期的维护操作交错，与维护操作被允许停止需要地址转换的命令直到维护操作完成之前，地址转换请求可能具有对地址转换缓存的更快访问。

30. 发明授权

US07472227B2 Invalidating multiple address cache entries 有权
标题翻译：使多个地址缓存条目无效
公开(公告)号：US07472227B2
公开(公告)日：2008-12-30
申请号：US11201971
申请日：2005-08-11
申请人： Chad B. McBride , Andrew H. Wottreng
发明人： Chad B. McBride , Andrew H. Wottreng
IPC分类号： G06F12/00
CPC分类号： G06F12/0891
摘要： In a first aspect, a first method is provided for removing entries from an address cache. The first method includes the steps of (1) writing data to a register; and (2) removing a plurality of address cache entries from the address cache based on the data written to the register. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种从地址高速缓存中移除条目的第一方法。第一种方法包括以下步骤：（1）将数据写入寄存器; 和（2）基于写入寄存器的数据从地址高速缓存中移除多个地址高速缓存条目。提供了许多其他方面。

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