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21. 发明授权

US4806202A Field enhanced tunnel oxide on treated substrates 失效
标题翻译：处理基板上的场增强隧道氧化物
公开(公告)号：US4806202A
公开(公告)日：1989-02-21
申请号：US104837
申请日：1987-10-05
申请人： Daniel N. Tang , Himanshu Choksi , Simon Wang , Simon M. Tam
发明人： Daniel N. Tang , Himanshu Choksi , Simon Wang , Simon M. Tam
IPC分类号： H01L21/316 , H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/8247 , H01L29/788 , H01L29/792 , H01L21/312
CPC分类号： H01L21/28273 , Y10S148/058 , Y10S438/964
摘要： A method for growing tunnel oxides on a specially treated substrate surface. The method comprises steps for roughening the substrate surface to induce low tunneling voltage in the subsequently grown tunnel oxide layer. The tunnel oxide layer is grown in a low temperature steam cycle to further provide enhanced tunneling. The surface treatment comprises the steps of growing a first oxide layer to seal the surface of the substrate followed by growing a second oxide on the first oxide layer. In the preferred embodiment, a plasma etch utilizing an oxide etcher with high energy ion bombardment and an aluminum electrode is utilized to etch through the first and second oxide layers. The aluminum electrode causes sputtered aluminum on the second oxide layer's surface. The sputtered aluminum blocks the anisotropic etching leaving a grass type oxide residue on the substrate surface. The etching continues, overetching into the substrate surface. The grass type oxide residue causes pitting to occur on the substrate surface. This pitting, resulting in sharpened features on the surface, yields enhanced tunneling characteristics for a subsequently grown tunnel oxide layer. The residue is then removed and the surface cleaned. The tunnel oxide layer is grown in a low temperture steam cycle to preserve and enhance the sharp tips for the purpose of enhanced tunneling.
摘要翻译：在特殊处理的基材表面上生长隧道氧化物的方法。该方法包括用于使衬底表面粗糙化以在随后生长的隧道氧化物层中诱导低隧穿电压的步骤。隧道氧化物层在低温蒸汽循环中生长以进一步提供增强的隧道。表面处理包括生长第一氧化物层以密封衬底的表面，然后在第一氧化物层上生长第二氧化物的步骤。在优选实施例中，利用利用具有高能离子轰击的氧化物蚀刻器和铝电极的等离子体蚀刻蚀刻穿过第一和第二氧化物层。铝电极在第二氧化物层的表面上形成溅射的铝。溅射的铝阻挡各向异性蚀刻，在基板表面上留下草型氧化物残留物。蚀刻继续，过刻蚀进入衬底表面。草型氧化物残留物在基材表面产生点蚀。这种点蚀，导致在表面上锐化的特征，为随后生长的隧道氧化物层产生增强的隧穿特性。然后将残余物除去并清洁表面。隧道氧化物层在低温蒸汽循环中生长，以保护和增强锋利的尖端，以增强隧道的目的。

22. 发明授权

US4797856A Self-limiting erase scheme for EEPROM 失效
标题翻译： EEPROM的自限制擦除方案
公开(公告)号：US4797856A
公开(公告)日：1989-01-10
申请号：US39086
申请日：1987-04-16
申请人： Winston K. M. Lee , Duane H. Oto , Simon M. Tam
发明人： Winston K. M. Lee , Duane H. Oto , Simon M. Tam
IPC分类号： G11C17/00 , G11C16/02 , G11C16/14 , G11C16/34 , H01L21/8246 , H01L21/8247 , H01L27/112 , H01L29/788 , H01L29/792 , G11C7/00 , G11C11/40
CPC分类号： G11C16/3477 , G11C16/14 , G11C16/3468 , G11C16/3472
摘要： A self-limiting scheme to prevent an over-erase condition of a one-transistor EEPROM cell. During an erase cycle, a drain voltage is fed back to a floating gate to counteract a positive erase voltage on the source of the memory cell and therein reduce the electric field across the tunnel oxide leading to the cessation of erase. In another scheme, the drain voltage is fed back to deactivate the erase voltage when a predetermined drain voltage value is exceeded.
摘要翻译：用于防止单晶体管EEPROM单元的过擦除状态的自限制方案。在擦除周期期间，漏极电压被反馈到浮动栅极以抵消存储器单元的源极上的正的擦除电压，并且其中减少穿过隧道氧化物的电场，导致擦除停止。在另一方案中，当超过预定的漏极电压值时，漏极电压被反馈以去激活擦除电压。

23. 发明授权

US07409568B2 Power supply voltage droop compensated clock modulation for microprocessors 有权
标题翻译：用于微处理器的电源电压下降补偿时钟调制
公开(公告)号：US07409568B2
公开(公告)日：2008-08-05
申请号：US11481717
申请日：2006-07-05
申请人： Simon M. Tam , Rahul Limaye , Utpal Desai
发明人： Simon M. Tam , Rahul Limaye , Utpal Desai
IPC分类号： H03B19/00
CPC分类号： G06F1/305 , G06F1/04
摘要： A voltage source droop compensated clock modulation for microprocessors is described. Specifically, the circuit reduces the clock frequency if a voltage source droop is detected.
摘要翻译：描述了用于微处理器的电压源下降补偿时钟调制。具体来说，如果检测到电压源下降，电路会降低时钟频率。

24. 发明授权

US07225349B2 Power supply voltage droop compensated clock modulation for microprocessors 有权
标题翻译：用于微处理器的电源电压下降补偿时钟调制
公开(公告)号：US07225349B2
公开(公告)日：2007-05-29
申请号：US10627272
申请日：2003-07-25
申请人： Simon M. Tam , Rahul Limaye , Utpal Desai
发明人： Simon M. Tam , Rahul Limaye , Utpal Desai
IPC分类号： H03B19/00
CPC分类号： G06F1/305 , G06F1/04
摘要： A voltage source droop compensated clock modulation for microprocessors is described. Specifically, the circuit reduces the clock frequency if a voltage source droop is detected.
摘要翻译：描述了用于微处理器的电压源下降补偿时钟调制。具体来说，如果检测到电压源下降，电路会降低时钟频率。

25. 发明授权

US07144152B2 Apparatus for thermal management of multiple core microprocessors 有权
标题翻译：多核心微处理器热管理装置
公开(公告)号：US07144152B2
公开(公告)日：2006-12-05
申请号：US11035467
申请日：2005-01-13
申请人： Stefan Rusu , Simon M. Tam
发明人： Stefan Rusu , Simon M. Tam
IPC分类号： G01K1/08
CPC分类号： G06F1/206 , G01K1/026 , G01K7/42 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/16 , Y02D10/172
摘要： An apparatus for managing the temperature of an integrated circuit having a multiple core microprocessor is described. Specifically, thermal sensors are placed at potential hot spots throughout each microprocessor core. A thermal management unit monitors the thermal sensors. If a thermal sensor identifies a hot spot, the thermal management unit adjusts the operating frequency and voltage of that microprocessor core accordingly.
摘要翻译：描述了一种用于管理具有多核微处理器的集成电路的温度的装置。具体来说，热传感器放置在每个微处理器核心的潜在热点。热管理单元监视热传感器。如果热传感器识别热点，则热管理单元相应地调整该微处理器核心的工作频率和电压。

26. 发明授权

US06608528B2 Adaptive variable frequency clock system for high performance low power microprocessors 有权
标题翻译：用于高性能低功耗微处理器的自适应变频时钟系统
公开(公告)号：US06608528B2
公开(公告)日：2003-08-19
申请号：US10044865
申请日：2001-10-22
申请人： Simon M. Tam , Stefan Rusu
发明人： Simon M. Tam , Stefan Rusu
IPC分类号： H03L700
CPC分类号： G06F1/324 , G06F1/3203 , H03L7/06 , H03L7/0805 , Y02D10/126
摘要： A method for dynamically varying a clock frequency in a processor. The method of one embodiment comprises driving a clock distribution network with a clock output from a phased locked loop (PLL). An adjustable clock generator is locked with the phased locked loop. The adjustable clock generator is substituted for the PLL on the clock distribution network.
摘要翻译：一种在处理器中动态地改变时钟频率的方法。一个实施例的方法包括用来自相位锁定环（PLL）的时钟输出来驱动时钟分配网络。可调时钟发生器与锁相环锁定。可调时钟发生器代替时钟分配网络上的PLL。

27. 发明授权

US06172937B2 Multiple synthesizer based timing signal generation scheme 有权
标题翻译：基于多合成器的定时信号生成方案
公开(公告)号：US06172937B2
公开(公告)日：2001-01-09
申请号：US09309049
申请日：1999-05-10
申请人： Alper Ilkbahar , Simon M. Tam , Ian A. Young
发明人： Alper Ilkbahar , Simon M. Tam , Ian A. Young
IPC分类号： G11C800
CPC分类号： G06F1/06
摘要： A multiple synthesizer based timing signal generation scheme is described that allows accurate data and strobe generation in high speed source synchronous system interfaces. Multiple loop locked clock synthesizers (e.g., phase locked loops, delay locked loops) are used to generate multiple clock signals. Data and strobe signals are triggered off of transitions of one of the clock signals. Because multiple loop locked clock synthesizers are used to generate the clock signals, optimal or near optimal alignment of the data and strobe signals can be achieved. Improved alignment of the data and strobe signals provides improved data transmission rates.
摘要翻译：描述了基于多合成器的定时信号生成方案，其允许在高速源同步系统接口中进行准确的数据和频闪生成。多环路锁定时钟合成器（例如，锁相环，延迟锁定环）用于产生多个时钟信号。数据和选通信号从一个时钟信号的转换触发。由于使用多个环路锁定时钟合成器来产生时钟信号，所以可以实现数据和选通信号的最佳或接近最佳对准。改进的数据和选通信号的对准提供了改进的数据传输速率。

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