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1. 发明授权

US4916337A TTL to CMOS logic level translator 失效
标题翻译： TTL到CMOS逻辑电平转换器
公开(公告)号：US4916337A
公开(公告)日：1990-04-10
申请号：US320312
申请日：1989-03-07
申请人： Wingyu Leung , Winston K. M. Lee
发明人： Wingyu Leung , Winston K. M. Lee
IPC分类号： H03K19/0185 , H03K3/356 , H03K19/017 , H03K19/0948
CPC分类号： H03K3/356104
摘要： Four transistors, a pair of buffers, and an inverter are configured with the first transistor connected in a pull-up configuration, with the transistor drain connected to a first node and with the transistor gate connected to a second node. The second transistor is connected in a pull-down configuration, with the transistor gate connected to a (data) input line and with the transistor drain connected to the first node. The third transistor is also connected in the pull-up configuration, with the transistor gate connected to the first node and with the transistor drain connected to the second node. The fourth transistor is also connected in the pull-down configuration, with the transistor gate coupled by the inverter to the input line and with the transistor drain connected to the second node. The buffers are each connected between a respective one of the nodes and a respective one of two (data) output lines.

2. 发明授权

US5355391A High speed bus system 失效
标题翻译：高速总线系统
公开(公告)号：US5355391A
公开(公告)日：1994-10-11
申请号：US847635
申请日：1992-03-06
申请人： Mark A. Horowitz , Winston K. M. Lee
发明人： Mark A. Horowitz , Winston K. M. Lee
IPC分类号： G06F3/00 , G06F13/40 , H03K3/356 , H04L25/02 , H04B3/00 , H04L25/00
CPC分类号： H04L25/0298 , G06F13/4072 , H03K3/356043 , H04L25/0282 , Y02B60/1228 , Y02B60/1235
摘要： In the high speed bus system of the present invention, the bus configuration is one in which all master devices are clustered at one end of an unterminated end of the bus. The slaves are located along the remaining length of the bus and the opposite end of the transmission line of the bus is terminated. By eliminating the termination resistor at the end of the bus where the master devices are located the required drive current needed to produce a given output swing is reduced. The bus drivers and receivers are CMOS integrated circuits. The bus of the present invention is operable utilizing small swing signals which enable sufficient implementation of current mode drivers for low impedance bus signals. In particular, the bus input receiver of the present invention comprises a two stage buffered sampler/amplifier which receives a small swing signal from the bus and samples and amplifies the low swing signal to a full swing signal within a single clock cycle using CMOS circuits.
摘要翻译：在本发明的高速总线系统中，总线配置是其中所有主设备在总线的未端接端的一端集群的配置。从站沿着总线的剩余长度定位，并且总线的传输线的相对端终止。通过消除主器件所在总线末端的终端电阻，减少了产生给定输出摆幅所需的驱动电流。总线驱动器和接收器是CMOS集成电路。本发明的总线可利用小的摆动信号进行操作，这使得能够充分实现用于低阻抗总线信号的电流模式驱动器。特别地，本发明的总线输入接收机包括两级缓冲取样器/放大器，其从总线接收小的摆动信号，并使用CMOS电路在单个时钟周期内对低回波信号采样并放大到全摆幅信号。

3. 发明授权

US4797856A Self-limiting erase scheme for EEPROM 失效
标题翻译： EEPROM的自限制擦除方案
公开(公告)号：US4797856A
公开(公告)日：1989-01-10
申请号：US39086
申请日：1987-04-16
申请人： Winston K. M. Lee , Duane H. Oto , Simon M. Tam
发明人： Winston K. M. Lee , Duane H. Oto , Simon M. Tam
IPC分类号： G11C17/00 , G11C16/02 , G11C16/14 , G11C16/34 , H01L21/8246 , H01L21/8247 , H01L27/112 , H01L29/788 , H01L29/792 , G11C7/00 , G11C11/40
CPC分类号： G11C16/3477 , G11C16/14 , G11C16/3468 , G11C16/3472
摘要： A self-limiting scheme to prevent an over-erase condition of a one-transistor EEPROM cell. During an erase cycle, a drain voltage is fed back to a floating gate to counteract a positive erase voltage on the source of the memory cell and therein reduce the electric field across the tunnel oxide leading to the cessation of erase. In another scheme, the drain voltage is fed back to deactivate the erase voltage when a predetermined drain voltage value is exceeded.
摘要翻译：用于防止单晶体管EEPROM单元的过擦除状态的自限制方案。在擦除周期期间，漏极电压被反馈到浮动栅极以抵消存储器单元的源极上的正的擦除电压，并且其中减少穿过隧道氧化物的电场，导致擦除停止。在另一方案中，当超过预定的漏极电压值时，漏极电压被反馈以去激活擦除电压。

4. 发明授权

US5432823A Method and circuitry for minimizing clock-data skew in a bus system 失效
标题翻译：用于最小化总线系统中时钟数据偏移的方法和电路
公开(公告)号：US5432823A
公开(公告)日：1995-07-11
申请号：US178601
申请日：1994-01-07
申请人： James A. Gasbarro , Mark A. Horowitz , Richard M. Barth , Winston K. M. Lee , Wingyu Leung , Paul M. Farmwald
发明人： James A. Gasbarro , Mark A. Horowitz , Richard M. Barth , Winston K. M. Lee , Wingyu Leung , Paul M. Farmwald
IPC分类号： G06F1/10 , G06F1/12 , G06F12/00 , G06F13/42 , G11C11/401 , G11C11/407 , H04L7/00
CPC分类号： G06F1/10 , G06F13/4217 , H04L7/0008
摘要： A bus system is described that minimizes clock-data skew. The bus system includes a data bus, a clockline and synchronization circuitry. The clockline has two clockline segments. Each clockline segment extends the entire length of the data bus and is joined to the other clockline segment by a turnaround at one end of the data bus. The clockline ensures that clock and data signals travel in the same direction. Synchronization circuitry within transmitting devices synchronizes data signals to be coupled onto the data bus with the clock signal used by other devices to receive the data.
摘要翻译：描述了最小化时钟数据偏移的总线系统。总线系统包括数据总线，时钟线和同步电路。时钟线有两个时钟线段。每个时钟线段延伸数据总线的整个长度，并通过数据总线一端的转向连接到另一个时钟线段。时钟线确保时钟和数据信号沿同一方向行进。发送设备内的同步电路将数据信号与其他设备使用的时钟信号同步到数据总线上，以接收数据。

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