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21. 发明授权

US06894934B2 Non-volatile memory cell sensing circuit, particularly for low power supply voltages and high capacitive load values 有权
标题翻译：非易失性存储单元感应电路，特别适用于低电源电压和高容性负载值
公开(公告)号：US06894934B2
公开(公告)日：2005-05-17
申请号：US10728372
申请日：2003-12-04
申请人： Fabio De Santis , Marco Pasotti , Guido De Sandre
发明人： Fabio De Santis , Marco Pasotti , Guido De Sandre
IPC分类号： G11C7/06 , G11C11/56 , G11C16/28 , G11C7/00 , G11C16/06
CPC分类号： G11C7/062 , G11C7/067 , G11C11/5642 , G11C16/28
摘要： A sensing circuit for a memory cell includes a first bias current generator connected between a first voltage reference and a first inner circuit node, and a second reference current generator connected to the first voltage reference. A comparator having a first input terminal is connected to a comparison circuit node that is connected to the second reference current generator, a second input terminal is connected to a circuit node that is connected to the first inner circuit node, and an output terminal forms an output terminal of the sensing circuit. A cascode-configured bias circuit is connected between the inner circuit node and a matching circuit node. The cascode-configured bias circuit is also connected to a second voltage reference. A current/voltage conversion stage is connected to the matching circuit node, to the comparison circuit node, and to a third voltage reference.
摘要翻译：用于存储单元的感测电路包括连接在第一电压基准和第一内部电路节点之间的第一偏置电流发生器和连接到第一参考电压的第二参考电流发生器。具有第一输入端子的比较器连接到连接到第二参考电流发生器的比较电路节点，第二输入端子连接到连接到第一内部电路节点的电路节点，并且输出端子形成输出端子。在内部电路节点和匹配电路节点之间连接共源共栅偏置电路。共源共栅配置的偏置电路也连接到第二电压基准。电流/电压转换级连接到匹配电路节点，连接到比较电路节点和第三参考电压。

22. 发明授权

US06473340B1 Reading method and circuit for a non-volatile memory 有权
标题翻译：用于非易失性存储器的读取方法和电路
公开(公告)号：US06473340B1
公开(公告)日：2002-10-29
申请号：US09699043
申请日：2000-10-27
申请人： Marco Pasotti , Giovanni Guaitini , Pier Luigi Rolandi , Guido De Sandre
发明人： Marco Pasotti , Giovanni Guaitini , Pier Luigi Rolandi , Guido De Sandre
IPC分类号： G11C1300
CPC分类号： G11C11/5642 , G11C16/28
摘要： A reading circuit having an array branch connected via an array bit line to an array memory cell, the content of which is to be read; a reference branch connected via a reference bit line to a current generator stage supplying a reference current; a current/voltage converter stage connected to the array branch and to the reference branch, and supplying at an array node and at a reference node respectively an array potential and a reference potential, which are correlated to the currents flowing respectively in the array branch and in the reference branch; a comparator stage connected to the array node and the reference node for comparing the array and reference potentials; a sample and hold stage arranged between the array node and the comparator stage and selectively operable to sample and hold the array potential; and a switching off stage for switching off the array branch.
摘要翻译：一种读取电路，具有经由阵列位线连接到阵列存储单元的阵列分支，其内容将被读取; 通过参考位线连接到提供参考电流的电流发生器级的参考支路; 连接到阵列支路和参考支路的电流/电压转换器级，并且在阵列节点和参考节点处分别提供与分别在阵列支路中流动的电流相关联的阵列电位和参考电位，在参考分支中; 连接到阵列节点的比较器级和用于比较阵列和参考电位的参考节点; 布置在所述阵列节点和所述比较器台之间并且可选择地可操作地采样和保持所述阵列电位的采样和保持级; 以及用于关闭阵列分支的关闭阶段。

23. 发明授权

US07843255B2 Charge pump regulator and circuit structure 有权
标题翻译：电荷泵调节器和电路结构
公开(公告)号：US07843255B2
公开(公告)日：2010-11-30
申请号：US11966117
申请日：2007-12-28
申请人： Marco Poles , Marco Pasotti
发明人： Marco Poles , Marco Pasotti
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , H02M1/14
摘要： There is disclosed a regulator for a charge pump having an input signal and generating an output signal at a value greater than the input signal. The charge pump comprises at least a capacitor and at least a device for charging and discharging the capacitor; the regulator comprises means having at the input said signal exiting the charge pump and a reference signal. Said means are able to generate a supply signal for said at least a device in response to the value of the difference between the output signal of the charge pump and said reference signal.
摘要翻译：公开了一种具有输入信号并且以大于输入信号的值产生输出信号的电荷泵的调节器。电荷泵至少包括一个电容器和至少一个用于充电和放电电容器的装置; 调节器包括在输入处具有离开电荷泵的信号和参考信号的装置。所述装置能够响应于电荷泵的输出信号与所述参考信号之间的差值而产生用于所述至少一个装置的电源信号。

24. 发明申请

US20080174288A1 CHARGE PUMP REGULATOR AND CIRCUIT STRUCTURE 有权
标题翻译：充电泵调节器和电路结构
公开(公告)号：US20080174288A1
公开(公告)日：2008-07-24
申请号：US11966117
申请日：2007-12-28
申请人： Marco Poles , Marco Pasotti
发明人： Marco Poles , Marco Pasotti
IPC分类号： G05F1/10 , G05F1/00
CPC分类号： H02M3/07 , H02M1/14
摘要： There is disclosed a regulator for a charge pump having an input signal and generating an output signal at a value greater than the input signal. The charge pump comprises at least a capacitor and at least a device for charging and discharging the capacitor; the regulator comprises means having at the input said signal exiting the charge pump and a reference signal. Said means are able to generate a supply signal for said at least a device in response to the value of the difference between the output signal of the charge pump and said reference signal.
摘要翻译：公开了一种具有输入信号并且以大于输入信号的值产生输出信号的电荷泵的调节器。电荷泵至少包括一个电容器和至少一个用于充电和放电电容器的装置; 调节器包括在输入处具有离开电荷泵的信号和参考信号的装置。所述装置能够响应于电荷泵的输出信号与所述参考信号之间的差值而产生用于所述至少一个装置的电源信号。

25. 发明授权

US07110289B1 Method and system for controlling MRAM write current to reduce power consumption 有权
标题翻译：用于控制MRAM写入电流以减少功耗的方法和系统
公开(公告)号：US07110289B1
公开(公告)日：2006-09-19
申请号：US10816271
申请日：2004-03-31
申请人： Kyusik Sin , Hugh Craig Hiner , Xizeng (Stone) Shi , William D. Jensen , Hua-Ching Tong , Matthew R Gibbons , Roberto Bez , Giulio Casagrande , Paolo Cappeletti , Marco Pasotti
发明人： Kyusik Sin , Hugh Craig Hiner , Xizeng (Stone) Shi , William D. Jensen , Hua-Ching Tong , Matthew R Gibbons , Roberto Bez , Giulio Casagrande , Paolo Cappeletti , Marco Pasotti
IPC分类号： G11C11/15
CPC分类号： G11C11/15
摘要： In a method and system for reducing power consumed by a magnetic memory, magnetic memory cells are coupled to a bit line and are associated with a plurality of digit lines. A bit line current is provided in the bit line. Digit currents are provided in parallel in the digit lines at substantially the same time as the bit line current. The digit and bit line currents allow the magnetic memory cells to be written to a plurality of states in parallel.
摘要翻译：在用于减少由磁存储器消耗的功率的方法和系统中，磁存储器单元耦合到位线并与多个数字线相关联。位线中提供位线电流。与位线电流基本相同的时刻，在数字线中并联提供数字电流。数字和位线电流允许磁存储单元被并行写入多个状态。

26. 发明授权

US06581134B2 Logic partitioning of a nonvolatile memory array 有权
标题翻译：非易失性存储器阵列的逻辑分区
公开(公告)号：US06581134B2
公开(公告)日：2003-06-17
申请号：US09817804
申请日：2001-03-26
申请人： Alessandro Rocchi , Marco Bisio , Marco Pasotti , Pier Luigi Rolandi
发明人： Alessandro Rocchi , Marco Bisio , Marco Pasotti , Pier Luigi Rolandi
IPC分类号： G06F1200
CPC分类号： G06F12/0246 , G06F2212/7203 , G06F2212/7211
摘要： A FLASH memory is organized in a plurality of physical sectors which may be split into a plurality of singularly addressable logic sectors. Each logic sector may include a memory space of a predetermined size and a chain pointer assuming a neutral value or a value pointing to a second logic sector associated with a respective chain pointer at the neutral value. Each logic sector may also include a status indicator assuming at least one of a first value if the logic sector is empty, a second value if the data therein belongs to the logic sector, a third value if the data does not belong to the logic sector, and a fourth value if the data has been erased. Further, each logic sector may include a remap pointer assuming the neutral value or a value pointing directly or indirectly to the chain pointer of a third logic sector.
摘要翻译： FLASH存储器被组织在多个物理扇区中，这些扇区可以被分成多个可单独寻址的逻辑扇区。每个逻辑扇区可以包括预定大小的存储器空间和假定中性值的链指针或指向与中性值处的相应链指针相关联的第二逻辑扇区的值。如果逻辑扇区为空，则每个逻辑扇区还可以包括状态指示符，如果其中的数据属于逻辑扇区，则假设第二值为第一值;如果数据不属于逻辑扇区，则第三值，如果数据已被擦除，则为第四个值。此外，每个逻辑扇区可以包括假定中性值的重映射指针或直接或间接指向第三逻辑扇区的链指针的值。

27. 发明授权

US6091642A Method for controlled erasing memory devices, in particular analog and multi-level flash-EEPROM devices 有权
标题翻译：用于控制擦除存储器件的方法，特别是模拟和多级闪存EEPROM器件
公开(公告)号：US6091642A
公开(公告)日：2000-07-18
申请号：US234942
申请日：1999-01-21
申请人： Marco Pasotti , Roberto Canegallo , Ernestina Chioffi , Giovanni Guaitini , Frank Lhermet , Pierluigi Rolandi
发明人： Marco Pasotti , Roberto Canegallo , Ernestina Chioffi , Giovanni Guaitini , Frank Lhermet , Pierluigi Rolandi
IPC分类号： G11C16/02 , G11C11/56 , G11C16/16 , G11C16/34 , G11C27/00 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C16/04
CPC分类号： G11C16/3409 , G11C11/56 , G11C11/5621 , G11C11/5635 , G11C16/16 , G11C16/3404 , G11C16/3445 , G11C27/005
摘要： The controlled erase method includes supplying at least one erase pulse to cells of a memory array; comparing the threshold voltage of the erased cells with a low threshold value; selectively soft-programming the erased cells which have a threshold voltage lower than the low threshold value; and verifying whether the erased cells have a threshold voltage lower than a high threshold value, which is higher than the low threshold value. If at least one predetermined number of erased cells has a threshold voltage which is higher than the high threshold value, an erase pulse is applied to all the cells and the steps of comparing, selectively soft-programming and verifying are repeated.
摘要翻译：受控擦除方法包括向存储器阵列的单元提供至少一个擦除脉冲; 将擦除的单元的阈值电压与低阈值进行比较; 选择性地软编程具有低于低阈值的阈值电压的已擦除单元; 以及验证被擦除的单元是否具有低于低阈值的阈值电压。如果至少一个预定数量的擦除单元具有高于高阈值的阈值电压，则将擦除脉冲施加到所有单元，并且重复比较选择性软编程和验证的步骤。

28. 发明授权

US08693256B2 FTP memory device with single selection transistor 有权
标题翻译：具有单选晶体管的FTP存储器件
公开(公告)号：US08693256B2
公开(公告)日：2014-04-08
申请号：US12975055
申请日：2010-12-21
申请人： Marco Pasotti , Davide Lena , Fabio De Santis
发明人： Marco Pasotti , Davide Lena , Fabio De Santis
IPC分类号： G11C11/34
CPC分类号： G11C16/0433 , G11C16/0491 , G11C16/3418 , G11C2216/10
摘要： A non-volatile memory device integrated in a chip of semiconductor material. An embodiment of a memory device includes a plurality of memory cells. Each memory cell includes a first well and a second well of a first type of conductivity that are formed in an insulating region of a second type of conductivity. The memory cell further includes a first, a second, and a third region of the second type of conductivity that are formed in the first well; these regions define a selection transistor of MOS type and a storage transistor of floating gate MOS type that are coupled in series. Moreover, the memory device includes a selection gate of the selection transistor, a floating gate of the storage transistor, and a control gate of the storage transistor formed in the second well; the control gate is capacitively coupled with the floating gate.
摘要翻译：集成在半导体材料芯片中的非易失性存储器件。存储器件的实施例包括多个存储器单元。每个存储单元包括形成在第二导电类型的绝缘区域中的第一导电类型的第一阱和第二阱。存储单元还包括形成在第一阱中的第二类型导电性的第一，第二和第三区域; 这些区域限定了串联耦合的MOS型选择晶体管和浮置栅极MOS型存储晶体管。此外，存储器件包括选择晶体管的选择栅极，存储晶体管的浮置栅极和形成在第二阱中的存储晶体管的控制栅极; 控制栅极与浮动栅极电容耦合。

29. 发明授权

US08619469B2 FTP memory device with programming and erasing based on Fowler-Nordheim effect 有权
标题翻译：基于Fowler-Nordheim效应的具有编程和擦除功能的FTP存储设备
公开(公告)号：US08619469B2
公开(公告)日：2013-12-31
申请号：US12968522
申请日：2010-12-15
申请人： Marco Pasotti , Marcella Carissimi , Davide Lena
发明人： Marco Pasotti , Marcella Carissimi , Davide Lena
IPC分类号： G11C16/04
CPC分类号： G11C16/0433 , G11C2216/10
摘要： An embodiment of a non-volatile memory device integrated in a chip of semiconductor material is proposed. The memory device includes a plurality of memory cells. Each memory cell includes a first well and a second well of first type of conductivity that are formed in an insulating region of a second type of conductivity. The memory cell further includes a first, a second, a third and a fourth region of the second type of conductivity that are formed in the first well; these regions define a sequence of a first selection transistor of MOS type, a storage transistor of floating gate MOS type, and a second selection transistor of MOS type that are coupled in series. The first region is short-circuited to the first well. Moreover, the memory device includes a first gate of the first selection transistor, a second gate of the second selection transistor, and a floating gate of the storage transistor. A control gate of the storage transistor is formed in the second well; the control gate is capacitively coupled with the floating gate.
摘要翻译：提出了集成在半导体材料芯片中的非易失性存储器件的实施例。存储装置包括多个存储单元。每个存储单元包括形成在第二导电类型的绝缘区域中的第一类导电性的第一阱和第二阱。存储单元还包括形成在第一阱中的第二导电类型的第一，第二，第三和第四区域; 这些区域限定了串联耦合的MOS型第一选择晶体管，浮栅MOS型存储晶体管和MOS型第二选择晶体管的序列。第一个地区与第一个井短路。此外，存储器件包括第一选择晶体管的第一栅极，第二选择晶体管的第二栅极和存储晶体管的浮置栅极。存储晶体管的控制栅极形成在第二阱中; 控制栅极与浮动栅极电容耦合。

30. 发明授权

US07251705B2 Embeddable flash memory system for non-volatile storage of code, data and bit-streams for embedded FPGA configurations 有权
标题翻译：可嵌入式闪存系统，用于非易失性存储用于嵌入式FPGA配置的代码，数据和位流
公开(公告)号：US07251705B2
公开(公告)日：2007-07-31
申请号：US10768743
申请日：2004-01-29
申请人： Marco Pasotti , Michele Borgatti , Pier Luigi Rolandi
发明人： Marco Pasotti , Michele Borgatti , Pier Luigi Rolandi
IPC分类号： G06F12/00
CPC分类号： G11C16/30
摘要： An application-specific embeddable flash memory having three content-specific I/O ports and delivering a peak read throughput of 1.2 GB/s. The memory is combined with a special automatic programming gate voltage ramp generator circuit having a programming rate of 1 Mbyte/s for non-volatile storage of code, data, and embedded FPGA bit stream configurations. The test chip uses a NOR-type 0.18 μm flash embedded technology with 1.8V power supply, two poly, six metal and memory cell size of 0.35 μm2.
摘要翻译：具有三个特定于内容的I / O端口并具有1.2 GB / s的峰值读取吞吐量的特定于应用的嵌入式闪存。该存储器与用于代码，数据和嵌入式FPGA位流配置的非易失性存储的具有1兆字节/秒的编程速率的专用自动编程门电压斜坡发生器电路组合。测试芯片采用NOR型0.18 mum闪存嵌入式技术，具有1.8V电源，两个聚六金属和存储单元尺寸为0.35 mum 2。

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