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1. 发明授权

US08693256B2 FTP memory device with single selection transistor 有权
标题翻译：具有单选晶体管的FTP存储器件
公开(公告)号：US08693256B2
公开(公告)日：2014-04-08
申请号：US12975055
申请日：2010-12-21
申请人： Marco Pasotti , Davide Lena , Fabio De Santis
发明人： Marco Pasotti , Davide Lena , Fabio De Santis
IPC分类号： G11C11/34
CPC分类号： G11C16/0433 , G11C16/0491 , G11C16/3418 , G11C2216/10
摘要： A non-volatile memory device integrated in a chip of semiconductor material. An embodiment of a memory device includes a plurality of memory cells. Each memory cell includes a first well and a second well of a first type of conductivity that are formed in an insulating region of a second type of conductivity. The memory cell further includes a first, a second, and a third region of the second type of conductivity that are formed in the first well; these regions define a selection transistor of MOS type and a storage transistor of floating gate MOS type that are coupled in series. Moreover, the memory device includes a selection gate of the selection transistor, a floating gate of the storage transistor, and a control gate of the storage transistor formed in the second well; the control gate is capacitively coupled with the floating gate.
摘要翻译：集成在半导体材料芯片中的非易失性存储器件。存储器件的实施例包括多个存储器单元。每个存储单元包括形成在第二导电类型的绝缘区域中的第一导电类型的第一阱和第二阱。存储单元还包括形成在第一阱中的第二类型导电性的第一，第二和第三区域; 这些区域限定了串联耦合的MOS型选择晶体管和浮置栅极MOS型存储晶体管。此外，存储器件包括选择晶体管的选择栅极，存储晶体管的浮置栅极和形成在第二阱中的存储晶体管的控制栅极; 控制栅极与浮动栅极电容耦合。

2. 发明授权

US06894934B2 Non-volatile memory cell sensing circuit, particularly for low power supply voltages and high capacitive load values 有权
标题翻译：非易失性存储单元感应电路，特别适用于低电源电压和高容性负载值
公开(公告)号：US06894934B2
公开(公告)日：2005-05-17
申请号：US10728372
申请日：2003-12-04
申请人： Fabio De Santis , Marco Pasotti , Guido De Sandre
发明人： Fabio De Santis , Marco Pasotti , Guido De Sandre
IPC分类号： G11C7/06 , G11C11/56 , G11C16/28 , G11C7/00 , G11C16/06
CPC分类号： G11C7/062 , G11C7/067 , G11C11/5642 , G11C16/28
摘要： A sensing circuit for a memory cell includes a first bias current generator connected between a first voltage reference and a first inner circuit node, and a second reference current generator connected to the first voltage reference. A comparator having a first input terminal is connected to a comparison circuit node that is connected to the second reference current generator, a second input terminal is connected to a circuit node that is connected to the first inner circuit node, and an output terminal forms an output terminal of the sensing circuit. A cascode-configured bias circuit is connected between the inner circuit node and a matching circuit node. The cascode-configured bias circuit is also connected to a second voltage reference. A current/voltage conversion stage is connected to the matching circuit node, to the comparison circuit node, and to a third voltage reference.
摘要翻译：用于存储单元的感测电路包括连接在第一电压基准和第一内部电路节点之间的第一偏置电流发生器和连接到第一参考电压的第二参考电流发生器。具有第一输入端子的比较器连接到连接到第二参考电流发生器的比较电路节点，第二输入端子连接到连接到第一内部电路节点的电路节点，并且输出端子形成输出端子。在内部电路节点和匹配电路节点之间连接共源共栅偏置电路。共源共栅配置的偏置电路也连接到第二电压基准。电流/电压转换级连接到匹配电路节点，连接到比较电路节点和第三参考电压。

3. 发明授权

US08619469B2 FTP memory device with programming and erasing based on Fowler-Nordheim effect 有权
标题翻译：基于Fowler-Nordheim效应的具有编程和擦除功能的FTP存储设备
公开(公告)号：US08619469B2
公开(公告)日：2013-12-31
申请号：US12968522
申请日：2010-12-15
申请人： Marco Pasotti , Marcella Carissimi , Davide Lena
发明人： Marco Pasotti , Marcella Carissimi , Davide Lena
IPC分类号： G11C16/04
CPC分类号： G11C16/0433 , G11C2216/10
摘要： An embodiment of a non-volatile memory device integrated in a chip of semiconductor material is proposed. The memory device includes a plurality of memory cells. Each memory cell includes a first well and a second well of first type of conductivity that are formed in an insulating region of a second type of conductivity. The memory cell further includes a first, a second, a third and a fourth region of the second type of conductivity that are formed in the first well; these regions define a sequence of a first selection transistor of MOS type, a storage transistor of floating gate MOS type, and a second selection transistor of MOS type that are coupled in series. The first region is short-circuited to the first well. Moreover, the memory device includes a first gate of the first selection transistor, a second gate of the second selection transistor, and a floating gate of the storage transistor. A control gate of the storage transistor is formed in the second well; the control gate is capacitively coupled with the floating gate.
摘要翻译：提出了集成在半导体材料芯片中的非易失性存储器件的实施例。存储装置包括多个存储单元。每个存储单元包括形成在第二导电类型的绝缘区域中的第一类导电性的第一阱和第二阱。存储单元还包括形成在第一阱中的第二导电类型的第一，第二，第三和第四区域; 这些区域限定了串联耦合的MOS型第一选择晶体管，浮栅MOS型存储晶体管和MOS型第二选择晶体管的序列。第一个地区与第一个井短路。此外，存储器件包括第一选择晶体管的第一栅极，第二选择晶体管的第二栅极和存储晶体管的浮置栅极。存储晶体管的控制栅极形成在第二阱中; 控制栅极与浮动栅极电容耦合。

4. 发明授权

US08493787B2 FTP memory device programmable and erasable at cell level 有权
标题翻译： FTP存储设备在单元级可编程和可擦除
公开(公告)号：US08493787B2
公开(公告)日：2013-07-23
申请号：US12975155
申请日：2010-12-21
申请人： Marco Pasotti , Davide Lena , Giancarlo Pisoni , Fabrizio Torricelli , Zsolt M. Kovacs-Vajna
发明人： Marco Pasotti , Davide Lena , Giancarlo Pisoni , Fabrizio Torricelli , Zsolt M. Kovacs-Vajna
IPC分类号： G11C11/34
CPC分类号： G11C16/0441 , G11C16/045 , G11C2216/10
摘要： An embodiment of non-volatile memory device integrated in a chip of semiconductor material is proposed. The memory includes at least one sector of a plurality of memory cells; each sector includes a storage region of a first type of conductivity and a further storage region of a second type of conductivity. Each memory cell includes a first region and a second region of the second type of conductivity, which are formed in the storage region for defining a storage transistor of floating gate MOS type of the first type of conductivity; the memory cell likewise includes a further first region and a further second region of the first type of conductivity, which are formed in the further storage region for defining a further storage transistor of floating gate MOS type of the second type of conductivity. The memory cell also includes a common floating gate of the storage transistor and the further storage transistor. The memory device further includes programming means for programming each memory cell individually by programming the corresponding floating gate through the corresponding storage transistor, and erasing means for erasing each memory cell individually by erasing the corresponding floating gate through the corresponding further storage transistor.
摘要翻译：提出了集成在半导体材料芯片中的非易失性存储器件的实施例。存储器包括多个存储器单元的至少一个扇区; 每个扇区包括第一导电类型的存储区域和第二导电类型的另外的存储区域。每个存储单元包括形成在存储区域中的第一类型的第一导电类型的第一区域和第二区域，用于限定第一导电类型的浮栅MOS型存储晶体管; 存储单元同样包括第一导电类型的另一第一区域和另一第二区域，其形成在另外的存储区域中，用于限定第二导电类型的浮栅MOS型的另一存储晶体管。存储单元还包括存储晶体管的公共浮置栅极和另外的存储晶体管。存储装置还包括编程装置，用于通过对相应的存储晶体管对相应的浮置栅格进行编程来分别对每个存储单元进行编程;以及擦除装置，用于通过相应的另外的存储晶体管擦除相应的浮置栅，来分别擦除每个存储单元。

5. 发明授权

US08264872B2 Column decoder for non-volatile memory devices, in particular of the phase-change type 有权
标题翻译：用于非易失性存储器件的列解码器，特别是相变型
公开(公告)号：US08264872B2
公开(公告)日：2012-09-11
申请号：US12548241
申请日：2009-08-26
申请人： Guido De Sandre , Marco Pasotti
发明人： Guido De Sandre , Marco Pasotti
IPC分类号： G11C11/00 , G11C8/10 , G11C7/00
CPC分类号： G11C13/0026 , G11C13/0004
摘要： A column decoder is for a phase-change memory device provided with an array of memory cells, a reading stage for reading data contained in the memory cells, and a programming stage for programming the data. The column decoder selects and enables biasing of a bitline of the array and generates a current path between the bitline and the reading stage or, alternatively, the programming stage, respectively during a reading or a programming operation of the contents of the memory cells. In the column decoder, a first decoder circuit generates a first current path between the bitline and the reading stage, and a second decoder circuit, distinct and separate from the first decoder circuit, generates a second current path, distinct from the first current path, between the bitline and the programming stage.
摘要翻译：列解码器用于设置有存储器单元阵列的相变存储器件，用于读取存储单元中包含的数据的读取级和用于对数据进行编程的编程级。列解码器选择并启用阵列的位线的偏置，并且在存储器单元的内容的读取或编程操作期间分别产生位线和读取级之间的电流路径，或者编程阶段。在列解码器中，第一解码器电路在位线和读取级之间产生第一电流路径，并且与第一解码器电路不同且分离的第二解码器电路产生与第一电流路径不同的第二电流路径，在位线和编程阶段之间。

6. 发明授权

US07843255B2 Charge pump regulator and circuit structure 有权
标题翻译：电荷泵调节器和电路结构
公开(公告)号：US07843255B2
公开(公告)日：2010-11-30
申请号：US11966117
申请日：2007-12-28
申请人： Marco Poles , Marco Pasotti
发明人： Marco Poles , Marco Pasotti
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , H02M1/14
摘要： There is disclosed a regulator for a charge pump having an input signal and generating an output signal at a value greater than the input signal. The charge pump comprises at least a capacitor and at least a device for charging and discharging the capacitor; the regulator comprises means having at the input said signal exiting the charge pump and a reference signal. Said means are able to generate a supply signal for said at least a device in response to the value of the difference between the output signal of the charge pump and said reference signal.
摘要翻译：公开了一种具有输入信号并且以大于输入信号的值产生输出信号的电荷泵的调节器。电荷泵至少包括一个电容器和至少一个用于充电和放电电容器的装置; 调节器包括在输入处具有离开电荷泵的信号和参考信号的装置。所述装置能够响应于电荷泵的输出信号与所述参考信号之间的差值而产生用于所述至少一个装置的电源信号。

7. 发明授权

US07504862B2 Level shifter translator 有权
标题翻译：电平移位器翻译器
公开(公告)号：US07504862B2
公开(公告)日：2009-03-17
申请号：US11321732
申请日：2005-12-28
申请人： Guido De Sandre , Marco Poles , Marco Pasotti
发明人： Guido De Sandre , Marco Poles , Marco Pasotti
IPC分类号： H03K19/0175
CPC分类号： H03K19/018528 , H03K19/01707 , H03K19/01721
摘要： Level shifter translator of the type comprising at least one first transistor and one second MOS transistor belonging to respective circuit branches connected with a first common conduction terminal and connected towards a first potential reference and receiving, on the respective conduction terminals, input differential voltages, the first and the second transistor have respective circuit branches referring to a biasing circuit with current mirror, a third transistor allows to couple the second transistor to said biasing circuit, an inverter connected to an output of said the circuit with the output driving the third transistor.
摘要翻译：该类型的电平移位器转换器包括至少一个第一晶体管和一个第二MOS晶体管，属于与第一公共导通端子连接并连接到第一电位基准的相应电路分支，并且在相应的导通端子上接收输入差分电压，第一晶体管和第二晶体管具有指向具有电流镜的偏置电路的各个电路分支，第三晶体管允许将第二晶体管耦合到所述偏置电路，反相器连接到所述电路的输出端，输出驱动第三晶体管。

8. 发明授权

US07110289B1 Method and system for controlling MRAM write current to reduce power consumption 有权
标题翻译：用于控制MRAM写入电流以减少功耗的方法和系统
公开(公告)号：US07110289B1
公开(公告)日：2006-09-19
申请号：US10816271
申请日：2004-03-31
申请人： Kyusik Sin , Hugh Craig Hiner , Xizeng (Stone) Shi , William D. Jensen , Hua-Ching Tong , Matthew R Gibbons , Roberto Bez , Giulio Casagrande , Paolo Cappeletti , Marco Pasotti
发明人： Kyusik Sin , Hugh Craig Hiner , Xizeng (Stone) Shi , William D. Jensen , Hua-Ching Tong , Matthew R Gibbons , Roberto Bez , Giulio Casagrande , Paolo Cappeletti , Marco Pasotti
IPC分类号： G11C11/15
CPC分类号： G11C11/15
摘要： In a method and system for reducing power consumed by a magnetic memory, magnetic memory cells are coupled to a bit line and are associated with a plurality of digit lines. A bit line current is provided in the bit line. Digit currents are provided in parallel in the digit lines at substantially the same time as the bit line current. The digit and bit line currents allow the magnetic memory cells to be written to a plurality of states in parallel.
摘要翻译：在用于减少由磁存储器消耗的功率的方法和系统中，磁存储器单元耦合到位线并与多个数字线相关联。位线中提供位线电流。与位线电流基本相同的时刻，在数字线中并联提供数字电流。数字和位线电流允许磁存储单元被并行写入多个状态。

9. 发明授权

US06687167B2 EEPROM flash memory erasable line by line 有权
标题翻译： EEPROM闪存可逐行删除
公开(公告)号：US06687167B2
公开(公告)日：2004-02-03
申请号：US10225513
申请日：2002-08-20
申请人： Giovanni Guaitini , Marco Pasotti , Guido De Sandre , David Iezzi , Marco Poles , Pier Luigi Rolandi
发明人： Giovanni Guaitini , Marco Pasotti , Guido De Sandre , David Iezzi , Marco Poles , Pier Luigi Rolandi
IPC分类号： G11C1604
CPC分类号： G11C16/08 , G11C16/16
摘要： A non-volatile semiconductor memory device including an output connected to a row line and two supply terminals. Each elementary stage has an upper branch with a p-channel MOS transistor and a lower branch with an n-channel MOS transistor. In order to permit the memory to be erased line by line without having to use components capable of withstanding high voltages, each elementary stage has two supplementary MOS transistors, namely an n-channel transistor in the upper branch and a p-channel transistor in the lower branch. In this way it becomes possible to bias the elementary stages in such a manner the in the reading and programming phases the upper branch will function as pull-up and the lower branch as pull-down, while in the erasure phase the upper branch functions as pull-down and the lower branch as pull-up.
摘要翻译：一种非易失性半导体存储器件，包括连接到行线和两个电源端子的输出。每个基本级具有具有p沟道MOS晶体管的上部分支和具有n沟道MOS晶体管的下部分支。为了允许逐行擦除存储器，而不必使用能够承受高电压的部件，每个基本级具有两个辅助MOS晶体管，即上部支路中的n沟道晶体管和下分支。以这种方式，可以以这种方式偏置基本级，在读取和编程阶段，上部分支将用作上拉和下部分支作为下拉，而在擦除阶段，上部分支作为下拉和下部分支作为上拉。

10. 发明授权

US06687159B2 Method of programming a plurality of memory cells connected in parallel, and a programming circuit therefor 有权
标题翻译：并联连接的多个存储单元的编程方法及其编程电路
公开(公告)号：US06687159B2
公开(公告)日：2004-02-03
申请号：US10036337
申请日：2001-12-19
申请人： Marco Pasotti , Giovanni Guaitini , Guido De Sandre , David Iezzi , Marco Poles , Pierluigi Rolandi
发明人： Marco Pasotti , Giovanni Guaitini , Guido De Sandre , David Iezzi , Marco Poles , Pierluigi Rolandi
IPC分类号： G11C1604
CPC分类号： G11C16/3481 , G11C8/08 , G11C16/12
摘要： A method of programming a plurality of memory cells are connected in parallel between first and second supply references and having their gate terminals connected together and, through row decoding means, also connected to an output terminal of an operational amplifier that is adapted to generate a word voltage signal, the first voltage reference being provided by a charge pump circuit. The programming method uses a program loop that includes the cells to be programmed and the operational amplifier, the charge pump circuit thus outputting a voltage ramp whose slope is a function of the cell demand. A programming circuit adapted to implement the method is also provided.
摘要翻译：一种编程多个存储单元的方法并联连接在第一和第二供电基准之间，并且其栅极端子连接在一起，并且通过行解码装置也连接到适于产生字的运算放大器的输出端电压信号，第一参考电压由电荷泵电路提供。编程方法使用包括要编程的单元和运算放大器的程序循环，电荷泵电路因此输出其斜率是单元需求函数的电压斜坡。还提供了一种适于实现该方法的编程电路。

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