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21. 发明授权

US07996812B2 Method of minimizing early-mode violations causing minimum impact to a chip design 有权
标题翻译：最小化早期模式违规的方法，对芯片设计造成的影响最小
公开(公告)号：US07996812B2
公开(公告)日：2011-08-09
申请号：US12191435
申请日：2008-08-14
申请人： Pooja M. Kotecha , Frank J. Musante , Veena S. Pureswaran , Louise H. Trevillyan , Paul G. Villarrubia
发明人： Pooja M. Kotecha , Frank J. Musante , Veena S. Pureswaran , Louise H. Trevillyan , Paul G. Villarrubia
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A system and a method for correcting early-mode timing violations that operate across the process space of a circuit design. Optimizations are performed to replace padding that increase path delays on fast paths. At the stage in the design process where early-mode violations are addressed, placement, late-mode timing closure, routing, and detailed electrical and timing analysis are assumed to have been completed. The optimizations are designed to be effective in delaying fast paths while minimizing the impact on already-completed work on the chip, in contrast to relying only on adding pads that can have a negative impact on all of these quantities. The optimizations are classified according to their invasiveness and are followed by their deployment. The deployment is designed to minimize using delay pads, reduce design disruptions, and minimize effects on other aspects of the design.
摘要翻译：一种用于校正在电路设计的处理空间中工作的早期模式定时违反的系统和方法。执行优化来替代在快速路径上增加路径延迟的填充。在处理早期模式违规的设计过程的阶段，假设已经完成了放置，延迟模式定时关闭，路由以及详细的电气和时序分析。优化设计是有效延迟快速路径，同时最大限度地减少对已经完成的芯片上的工作的影响，而不是仅依靠添加可能对所有这些量产生负面影响的焊盘。优化根据其入侵性进行分类，其后进行部署。该部署旨在最大限度地减少使用延迟焊盘，减少设计中断，并尽量减少对设计其他方面的影响。

22. 发明申请

US20100257499A1 TECHNIQUES FOR FAST AREA-EFFICIENT INCREMENTAL PHYSICAL SYNTHESIS 审中-公开
标题翻译：用于快速增强体力合成的技术
公开(公告)号：US20100257499A1
公开(公告)日：2010-10-07
申请号：US12416960
申请日：2009-04-02
申请人： Charles J. Alpert , Zhuo Li , Chin Ngai Sze , Louise H. Trevillyan , Ying Zhou
发明人： Charles J. Alpert , Zhuo Li , Chin Ngai Sze , Louise H. Trevillyan , Ying Zhou
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A fast technique for circuit optimization in a physical synthesis flow iteratively repeats slew-driven (timerless) buffering and repowering with a changing slew target. Buffers are added as necessary with each iteration to bring the nets in line with the new slew target, but any nets having positive slack from the previous iteration are skipped, and that slack information is cached for future timing analysis. Buffer insertion is iteratively repeated with incrementally decreasing slew until a minimum slew is reached, or when none of the nets have negative slack. Iteratively repeating the timerless buffering and repowering while gradually decreasing the slew constraint in this manner results in a design structure which retains high quality of results with significantly smaller area and wire length, and with only a small computational overhead.
摘要翻译：物理合成流中电路优化的快速技术可以迭代地重复使用转换驱动（定时器）缓冲并使用更改的转换目标重新启动。根据需要，每次迭代添加缓冲区，使网格与新的转换目标一致，但是跳过与上一次迭代相反的任何网络，并且缓存信息被缓存以便将来进行时序分析。缓冲区插入被迭代重复，逐渐减小，直到达到最小的转差，或者当没有网络有负的松弛时。以这种方式迭代地重复定时器缓冲和重新赋能，同时以这种方式逐渐减小摆动约束导致设计结构，其保持高质量的结果，具有明显更小的面积和导线长度，并且仅具有小的计算开销。

23. 发明授权

US08539400B2 Routability using multiplexer structures 失效
标题翻译：使用多路复用器结构的路由性
公开(公告)号：US08539400B2
公开(公告)日：2013-09-17
申请号：US13248119
申请日：2011-09-29
申请人： Charles J. Alpert , Victor N. Kravets , Zhuo Li , Louise H. Trevillyan , Ying Zhou
发明人： Charles J. Alpert , Victor N. Kravets , Zhuo Li , Louise H. Trevillyan , Ying Zhou
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Mechanisms are provided for generating a logic design of an integrated circuit device. An initial logic design representation of the integrated circuit device is received and one or more areas of the initial logic design representation are identified where logic elements in the one or more areas can be replaced with one or more multiplexer tree structures. Logic elements in the one or more areas of the initial logic design representation are replaced with multiplexer tree structures to generate a modified logic design representation. The modified logic design representation is output to a physical synthesis system to generate a physical layout of the integrated circuit device based on the modified logic design representation.
摘要翻译：提供用于产生集成电路器件的逻辑设计的机构。接收集成电路设备的初始逻辑设计表示，并且识别初始逻辑设计表示的一个或多个区域，其中一个或多个区域中的逻辑元件可被一个或多个多路复用器树结构替代。初始逻辑设计表示的一个或多个区域中的逻辑元件被多路复用器树结构替代以生成修改的逻辑设计表示。经修改的逻辑设计表示被输出到物理合成系统，以基于经修改的逻辑设计表示来生成集成电路器件的物理布局。

24. 发明授权

US08407652B2 Task-based multi-process design synthesis 有权
标题翻译：基于任务的多进程设计综合
公开(公告)号：US08407652B2
公开(公告)日：2013-03-26
申请号：US12972879
申请日：2010-12-20
申请人： Anthony D. Drumm , Jagannathan Narasimhan , Lakshmi N. Reddy , Louise H. Trevillyan , Brian C. Wilson
发明人： Anthony D. Drumm , Jagannathan Narasimhan , Lakshmi N. Reddy , Louise H. Trevillyan , Brian C. Wilson
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A task-based multi-process design synthesis methodology relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. The child processes then notify the parent process of those objects that qualify as candidate objects, so that the parent process only has to perform the transform on the candidate objects, thereby relieving the parent process from the overhead associated with performing the transform on non-candidate objects for which the transform has been determined by the child processes as not being successful.
摘要翻译：基于任务的多进程设计合成方法依赖于多个子进程来辅助父进程对集成电路设计进行优化。来自集成电路设计的对象被分组成子集并被分配给子进程，每个子进程对分配给该子进程的子集中的每个对象执行变换，并且确定该子集中的哪些对象是候选对象变革的表现已经取得成功。然后，子进程通知那些符合候选对象的那些对象的父进程，以便父进程只需对候选对象执行转换，从而将父进程从与非候选对象执行转换相关的开销中解除子进程已将该转换确定为未成功的对象。

25. 发明授权

US08341565B2 Task-based multi-process design synthesis with reproducible transforms 有权
标题翻译：基于任务的多进程设计合成与可重现的转换
公开(公告)号：US08341565B2
公开(公告)日：2012-12-25
申请号：US12972980
申请日：2010-12-20
申请人： Anthony D. Drumm , Jagannathan Narasimhan , Lakshmi N. Reddy , Louise H. Trevillyan
发明人： Anthony D. Drumm , Jagannathan Narasimhan , Lakshmi N. Reddy , Louise H. Trevillyan
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A task-based multi-process design synthesis methodology is reproducible, and relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. Each child process also undoes the transform performed for each object such that the same initial state of the integrated circuit design is used to perform each transform. In addition, the parent process tracks the results of performing the transform by each child process, and applies successful transforms in a controlled sequence.
摘要翻译：基于任务的多进程设计合成方法是可重复的，并且依赖于多个子进程来辅助父进程对集成电路设计进行优化。来自集成电路设计的对象被分组成子集并被分配给子进程，每个子进程对分配给该子进程的子集中的每个对象执行变换，并且确定该子集中的哪些对象是候选对象变革的表现已经取得成功。每个子进程还撤消对每个对象执行的变换，使得集成电路设计的相同初始状态被用于执行每个变换。此外，父进程跟踪每个子进程执行变换的结果，并以受控序列应用成功的转换。

26. 发明申请

US20120159417A1 TASK-BASED MULTI-PROCESS DESIGN SYNTHESIS 有权
标题翻译：基于任务的多进程设计合成
公开(公告)号：US20120159417A1
公开(公告)日：2012-06-21
申请号：US12972879
申请日：2010-12-20
申请人： Anthony D. Drumm , Jagannathan Narasimhan , Lakshmi N. Reddy , Louise H. Trevillyan , Brian C. Wilson
发明人： Anthony D. Drumm , Jagannathan Narasimhan , Lakshmi N. Reddy , Louise H. Trevillyan , Brian C. Wilson
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A task-based multi-process design synthesis methodology relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. The child processes then notify the parent process of those objects that qualify as candidate objects, so that the parent process only has to perform the transform on the candidate objects, thereby relieving the parent process from the overhead associated with performing the transform on non-candidate objects for which the transform has been determined by the child processes as not being successful.
摘要翻译：基于任务的多进程设计合成方法依赖于多个子进程来辅助父进程对集成电路设计进行优化。来自集成电路设计的对象被分组成子集并被分配给子进程，每个子进程对分配给该子进程的子集中的每个对象执行变换，并且确定该子集中的哪些对象是候选对象变革的表现已经取得成功。然后，子进程通知那些符合候选对象的那些对象的父进程，以便父进程只需对候选对象执行转换，从而将父进程从与非候选对象执行转换相关的开销中解除子进程已将该转换确定为未成功的对象。

27. 发明授权

US07581201B2 System and method for sign-off timing closure of a VLSI chip 失效
标题翻译：用于签发VLSI芯片的定时关闭的系统和方法
公开(公告)号：US07581201B2
公开(公告)日：2009-08-25
申请号：US11680110
申请日：2007-02-28
申请人： Michael A. Kazda , Pooja M. Kotecha , Adam P. Matheny , Lakshmi Reddy , Louise H. Trevillyan , Paul G. Villarrubia
发明人： Michael A. Kazda , Pooja M. Kotecha , Adam P. Matheny , Lakshmi Reddy , Louise H. Trevillyan , Paul G. Villarrubia
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/84
摘要： A method for performing timing optimization of a detail routed netlist, incorporating statistical variability information, common path pessimism reduction, and capacitative coupling information, in a tightly coupled, incremental manner with minimal perturbations to the placement, routing, and asserted parasitic information. The method corrects violations in a placed and routed design of a VLSI circuit chip, where the design is represented by a netlist describing logical and physical characteristics of the design and by a corresponding timing graph, the method including the steps of: identifying violations in the design; iteratively eliminating the violations by incrementally transforming the logical and the physical characteristics of the design, incorporating in the design only legal placements and routes; and applying incremental timing to evaluate the transformations, and updating the existing timing graphs to reflect changes consisting of the legal placements and routes.
摘要翻译：一种用于以紧密耦合的递增方式对细节路由网表执行定时优化的方法，其以最小的扰动对放置，路由和断言的寄生信息进行并入，并入统计变异信息，公共路径悲观度降低和电容耦合信息。该方法校正了VLSI电路芯片的放置和路由设计中的违规，其中设计由描述设计的逻辑和物理特性的网表以及对应的时序图表示，该方法包括以下步骤：识别设计; 通过逐步改变设计的逻辑和物理特征，迭代地消除违规行为，仅在设计中纳入合法的布局和路线; 并应用增量时间来评估变革，并更新现有的时间图，以反映由法定刊登位置和路线组成的变更。

28. 发明申请

US20080155486A1 SYSTEMS AND METHODS FOR REDUCING WIRING VIAS DURING SYNTHESIS OF ELECTRONIC DESIGNS 审中-公开
标题翻译：在电子设计合成期间减少接线VIAS的系统和方法
公开(公告)号：US20080155486A1
公开(公告)日：2008-06-26
申请号：US11613754
申请日：2006-12-20
申请人： Louise H. Trevillyan
发明人： Louise H. Trevillyan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Systems and methods for reducing wire vias during synthesis of electronic designs. Exemplary embodiments include an electronic design via reduction method, including marking a plurality of nets, each net having at least two pin connections as unprocessed, determining whether there are further unprocessed nets, selecting one of the plurality of nets and marking the net as processed, sorting pairs of pins on the net by a displacement, selecting an unprocessed pin pair having the smallest displacement relative to other of the plurality of unprocessed pin pairs, selectively removing a via between the pins, determining whether there are any further unprocessed pin pairs and determining whether there are any further unprocessed nets.
摘要翻译：在电子设计合成期间减少导线通孔的系统和方法。示例性实施例包括经由还原方法的电子设计，包括标记多个网络，每个网络具有至少两个引脚连接作为未处理的网络，确定是否存在进一步的未处理网络，选择多个网络中的一个网络并且将网络标记为已处理，通过位移对网上的引脚对进行排序，选择相对于多个未处理的引脚对中的其它引脚对具有最小位移的未处理的引脚对，选择性地去除引脚之间的通孔，确定是否存在任何进一步的未处理引脚对并确定是否有进一步的未加工网。

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