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21. 发明申请

US20050059238A1 Cooling system for a semiconductor device and method of fabricating same 有权
标题翻译：一种用于半导体器件的冷却系统及其制造方法
公开(公告)号：US20050059238A1
公开(公告)日：2005-03-17
申请号：US10661299
申请日：2003-09-12
申请人： Howard Chen , Louis Hsu , Joseph Shepard
发明人： Howard Chen , Louis Hsu , Joseph Shepard
IPC分类号： H01L21/44 , H01L21/48 , H01L23/367
CPC分类号： H01L23/473 , H01L21/4871 , H01L23/3677 , H01L25/0655 , H01L2224/05001 , H01L2224/05008 , H01L2224/05548 , H01L2224/16225 , H01L2924/00014 , H01L2924/01019 , H01L2924/01079 , H01L2924/10158 , H01L2924/15311 , H01L2224/05599 , H01L2224/05099
摘要： A cooling system for a semiconductor substrate incudes a plurality of trenches formed from a backside of the semiconductor substrate, and thermally conductive material deposited in the plurality of trenches. A method of forming cooling elements in a semiconductor substrate, includes coating a backside of the semiconductor substrate with a first mask layer, forming a plurality of trench patterns in the first mask layer, etching the semiconductor substrate to form a plurality of trenches along the plurality of trench patterns, and depositing thermally conductive material in the plurality of trenches. Trenches constructed from the backside of a wafer improve efficiency of heat transfer from a front-side to the backside of an integrated-circuit chip. The fabrication of trenches from the backside of the wafer allows for increases in the depth and number of trenches, and provides a means to attach passive and active cooling devices directly to the backside of a wafer.
摘要翻译：用于半导体衬底的冷却系统包括由半导体衬底的背面形成的多个沟槽和沉积在多个沟槽中的导热材料。一种在半导体衬底中形成冷却元件的方法，包括用第一掩模层涂覆半导体衬底的背面，在第一掩模层中形成多个沟槽图案，蚀刻半导体衬底以形成沿着多个的多个沟槽的沟槽图案，并且在多个沟槽中沉积导热材料。从晶片背面构成的沟槽提高了从集成电路芯片的正面到背面的传热效率。从晶片的背面制造沟槽允许沟槽的深度和数量的增加，并且提供了将被动和主动的冷却装置直接附接到晶片的背面的手段。

22. 发明申请

US20050040536A1 Apparatus and method to reduce signal cross-talk 失效
标题翻译：降低信号串扰的装置和方法
公开(公告)号：US20050040536A1
公开(公告)日：2005-02-24
申请号：US10644372
申请日：2003-08-20
申请人： Patrick Buffet , Charles Chiu , Jon Garlett , Louis Hsu , Brian Schuh
发明人： Patrick Buffet , Charles Chiu , Jon Garlett , Louis Hsu , Brian Schuh
IPC分类号： H01L23/12 , H01L23/64 , H01L21/44 , H01L21/48 , H01L21/50 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/642 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H01L2924/15174 , H01L2924/15311 , H01L2924/3025 , H01L2224/05599
摘要： A semiconductor chip package with reduced cross-talk between adjacent signals in a layer of a carrier is disclosed. A first pair of conductors for carrying a first signal is provided in a layer of the carrier. A second pair of conductors for carrying a second signal is provided adjacent to the first pair of conductors in the layer, where the first and second pairs of conductors are configured such that cross-talk between the first and second pairs of conductors is substantially minimized, without increasing the size of the package. The height of the first pair of conductors is shorter than the second pair of conductors. Alternatively, the first and second pairs of conductors are configured so that they evenly affect each other. The chip package thus reduces the cross-talk without compromising the density of the interconnections in the package or resulting in an increase in the size of the package.
摘要翻译：公开了一种在载体层中的相邻信号之间的串扰减小的半导体芯片封装。用于承载第一信号的第一对导体提供在载体的层中。用于承载第二信号的第二对导体被提供为邻近层中的第一对导体，其中第一和第二对导体被配置为使得第一和第二对导体之间的串扰基本上最小化，而不增加包装的尺寸。第一对导体的高度比第二对导体短。或者，第一和第二对导体被配置成使得它们彼此均匀地影响。芯片封装因此减少串扰，而不会影响封装中互连的密度，或导致封装尺寸的增加。

23. 发明授权

US06777286B2 Compact SRAM cell incorporating refractory metal-silicon-nitrogen resistive elements and method for fabricating 失效
$Compact SRAM cell incorporating refractory metal-silicon-nitrogen resistive elements and method for fabricating$
标题翻译：含有难熔金属 - 硅 - 氮电阻元件的紧凑SRAM单元及其制造方法
公开(公告)号：US06777286B2
公开(公告)日：2004-08-17
申请号：US10616243
申请日：2003-07-08
申请人： Lawrence Clevenger , Louis Hsu , Li-Kong Wang
发明人： Lawrence Clevenger , Louis Hsu , Li-Kong Wang
IPC分类号： H01L218234
CPC分类号： H01L27/11 , H01L27/1112 , Y10S257/903 , Y10S257/904
摘要： A compact SRAM cell that incorporates refractory metal-silicon-nitrogen resistive elements as its pull-up transistors is described which includes a semi-conducting substrate, a pair of NMOS transfer devices formed vertically on the sidewalls of an etched substrate by a metal conductor providing electrical communication between an n+ region in the substrate and a bitline on top, a pair of pull-down nMOS devices on the substrate connected to ground interconnects, and a pair of vertical high-resistive elements formed of a refractory metal-silicon-nitrogen and function as a load for connecting to Vdd. The invention further describes a method for fabricating such compact SRAM cell.
摘要翻译：描述了一种紧凑的SRAM单元，其包含难熔金属硅 - 氮电阻元件作为其上拉晶体管，其包括半导体衬底，一对NMOS传输器件，其通过金属导体在蚀刻衬底的侧壁上垂直形成，提供衬底中n +区和顶部位线之间的电气通信，连接到接地互连的衬底上的一对下拉nMOS器件以及由难熔金属硅形成的一对垂直高电阻元件 - 并且作为连接到Vdd的负载。本发明还描述了一种用于制造这种紧凑的SRAM单元的方法。

24. 发明授权

US06601205B1 Method to descramble the data mapping in memory circuits 有权
标题翻译：在存储器电路中解扰数据映射的方法
公开(公告)号：US06601205B1
公开(公告)日：2003-07-29
申请号：US09675953
申请日：2000-09-29
申请人： Gunther Lehmann , Gerd Frankowsky , Louis Hsu , Armin Reith
发明人： Gunther Lehmann , Gerd Frankowsky , Louis Hsu , Armin Reith
IPC分类号： G01R3128
CPC分类号： G01R31/318378 , G01R31/3183 , G01R31/31926 , G11C29/10 , G11C29/56
摘要： An automatic method for the generation of a logical hardware test pattern in memory circuits is based on a given physical pattern. The method includes backwards transformation from a given set of logical data patterns. Since the method is automatic, no knowledge of data scrambling inside the memory circuit is required.
摘要翻译：用于在存储器电路中产生逻辑硬件测试图案的自动方法基于给定的物理模式。该方法包括从给定的一组逻辑数据模式的向后变换。由于该方法是自动的，所以不需要存储电路内的数据加扰知识。

25. 发明授权

US06353248B1 Optimized decoupling capacitor using lithographic dummy filler 有权
标题翻译：使用光刻虚拟填料的优化去耦电容器
公开(公告)号：US06353248B1
公开(公告)日：2002-03-05
申请号：US09562220
申请日：2000-04-28
申请人： Armin M Reith , Louis Hsu , Henning Haffner , Gunther Lehmann
发明人： Armin M Reith , Louis Hsu , Henning Haffner , Gunther Lehmann
IPC分类号： H01L2976
CPC分类号： H01L28/40 , H01L27/10861 , H01L27/10894 , H01L27/10897
摘要： A method to optimize the size and filling of decoupling capacitors for very large scale integrated circuits (VLSI) using existing lithographic fillers. The method combines the automatic or manual generation of lithographic fill patterns with the forming of the capacitors. According to the method, when the chip layout is about to be finished, all remaining empty space on the chip gets identified by a layout tool. Then, the closest power-supply nets get extracted. All power supplies and their combinations are sorted in a connection table which determines the appropriate types of capacitances once the power-supply nets closest to the empty spaces extracted from the layout. The empty spaces are then assigned appropriate decoupling capacitances. Decoupling capacitors generated by the method are suitable for VLSI power supplies for noise reduction.
摘要翻译：使用现有的平版印刷填料，优化大型集成电路（VLSI）的去耦电容的尺寸和填充的方法。该方法将自动或手动生成光刻填充图案与电容器的形成相结合。根据该方法，当芯片布局即将完成时，芯片上的所有剩余空间都由布局工具识别。然后，最近的电源网络被提取。所有电源及其组合在连接表中排序，一旦电源网最接近从布局提取的空白空间中，则确定适当类型的电容。然后空的空间被分配适当的去耦电容。通过该方法产生的去耦电容适用于降低噪声的VLSI电源。

26. 发明授权

US06232154B1 Optimized decoupling capacitor using lithographic dummy filler 有权
标题翻译：使用光刻虚拟填料的优化去耦电容器
公开(公告)号：US06232154B1
公开(公告)日：2001-05-15
申请号：US09442890
申请日：1999-11-18
申请人： Armin M. Reith , Louis Hsu , Henning Haffner , Gunther Lehmann
发明人： Armin M. Reith , Louis Hsu , Henning Haffner , Gunther Lehmann
IPC分类号： H01L2182
CPC分类号： H01L28/40 , H01L27/10861 , H01L27/10894 , H01L27/10897
摘要： A method to optimize the size and filling of decoupling capacitors for very large scale integrated circuits (VLSI) using existing lithographic fillers. The method combines the automatic or manual generation of lithographic fill patterns with the forming of the capacitors. According to the method, when the chip layout is about to be finished, all remaining empty space on the chip gets identified by a layout tool. Then, the closest power-supply nets get extracted. All power supplies and their combinations are sorted in a connection table which determines the appropriate types of capacitances once the power-supply nets closest to the empty spaces extracted from the layout. The empty spaces are then assigned appropriate decoupling capacitances. Decoupling capacitors generated by the method are suitable for VLSI power supplies for noise reduction.
摘要翻译：使用现有的平版印刷填料，优化大型集成电路（VLSI）的去耦电容的尺寸和填充的方法。该方法将自动或手动生成光刻填充图案与电容器的形成相结合。根据该方法，当芯片布局即将完成时，芯片上剩余的空余空间由布局工具识别。然后，最近的电源网络被提取。所有电源及其组合在连接表中排序，一旦电源网最接近从布局提取的空白空间中，则确定适当类型的电容。然后空的空间被分配适当的去耦电容。通过该方法产生的去耦电容适用于降低噪声的VLSI电源。

27. 发明授权

US07657995B2 Method of fabricating a microelectromechanical system (MEMS) switch 失效
标题翻译：制造微机电系统（MEMS）开关的方法
公开(公告)号：US07657995B2
公开(公告)日：2010-02-09
申请号：US11776835
申请日：2007-07-12
申请人： Louis Hsu , Timothy Dalton , Lawrence Clevenger , Carl Radens , Kwong Hon Wong , Chih-Chao Yang
发明人： Louis Hsu , Timothy Dalton , Lawrence Clevenger , Carl Radens , Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01H11/00 , H01H65/00
CPC分类号： H01H59/0009 , H01H1/20 , H01H2001/0084 , H01H2001/0089 , Y10T29/49105 , Y10T29/49128 , Y10T29/49155 , Y10T29/49204 , Y10T29/49208
摘要： A method of fabricating a MEMS switch that is fully integratable in a semiconductor fabrication line. The method consists of forming two posts, each end thereof terminating in a cap; a rigid movable conductive plate having a surface terminating in a ring in each of two opposing edges, the rings being loosely connected to guiding posts; forming upper and lower electrode pairs and upper and lower interconnect wiring lines connected and disconnected by the rigid movable conductive plate. The conductive plate moves up, shorting two upper interconnect wirings lines. Conversely, the conductive plate moves down when the voltage is applied to the lower electrode pair, while the upper electrode pair is grounded, shorting the two lower interconnect wiring lines and opening the upper wiring lines.
摘要翻译：一种制造可在半导体制造生产线中完全集成的MEMS开关的方法。该方法包括形成两个柱，其每端终止于盖中; 刚性可移动导电板，其表面终止于两个相对边缘中的每一个中的环中，所述环松散地连接到引导柱; 形成上下电极对以及由刚性可移动导电板连接和断开的上下互连布线。导电板向上移动，使两条上部互连线路短路。相反，当电压施加到下电极对时，导电板向下移动，而上电极对接地，使两个下互连布线短路并打开上布线。

28. 发明申请

US20090312046A1 INTELLIGENT WIRELESS POWER CHARGING SYSTEM 有权
标题翻译：智能无线充电系统
公开(公告)号：US20090312046A1
公开(公告)日：2009-12-17
申请号：US12137185
申请日：2008-06-11
申请人： Lawrence Clevenger , Timothy Dalton , Louis Hsu , Carl Radens
发明人： Lawrence Clevenger , Timothy Dalton , Louis Hsu , Carl Radens
IPC分类号： H04B7/00 , H04M1/00
CPC分类号： H02J50/20 , H02J7/025 , H02J17/00
摘要： A system and methodology for intelligent power management of wirelessly networked devices. The system provides for reliable wireless communication via a wireless power charging method and, a method to maintain power capacity of batteries in a wireless device. The batteries are charged via an RF harvesting unit embedded inside the wireless device. An intelligent wireless power charging system further comprises at least two batteries and at least two RF adaptor devices coupled to an AC power line. The first adaptor is set for data communication while the second adaptor is used to transmit the power. In addition, when a first battery is in use during active mode, the second battery is subjected to wireless charging.
摘要翻译：一种用于无线网络设备智能电源管理的系统和方法。该系统通过无线电力充电方法提供可靠的无线通信，以及在无线设备中维持电池的电力容量的方法。电池通过嵌入在无线设备内部的射频收集单元进行充电。智能无线电力充电系统还包括耦合到AC电力线的至少两个电池和至少两个RF适配器装置。第一个适配器设置为数据通信，而第二个适配器用于传输电源。此外，当在活动模式期间使用第一电池时，对第二电池进行无线充电。

29. 发明授权

US07545161B2 Method and apparatus to measure threshold shifting of a MOSFET device and voltage difference between nodes 失效
标题翻译：测量MOSFET器件的阈值偏移和节点之间的电压差的方法和装置
公开(公告)号：US07545161B2
公开(公告)日：2009-06-09
申请号：US11832796
申请日：2007-08-02
申请人： Louis Hsu , Jong-Ru Guo , Ping-Chuan Wang , Zhijian Yang
发明人： Louis Hsu , Jong-Ru Guo , Ping-Chuan Wang , Zhijian Yang
IPC分类号： G01R31/02
CPC分类号： G01R31/2621
摘要： An on-chip circuit to quantitatively measure threshold voltage shifts of a MOSFET. The circuit includes a programmable Vt reference sensor; a programmable Vt monitoring sensor; and a comparator for receiving inputs from the reference and monitoring sensors providing an output flag signal. The shifting of the MOSFET device voltage threshold monitors process variations, geometry sensitivity, plasma damage, stress, and hot carriers and other device damages. The same circuit also measures voltage differences between any two nodes in an integrated circuit chip or wafer.
摘要翻译：用于定量测量MOSFET的阈值电压偏移的片上电路。该电路包括可编程Vt参考传感器; 可编程Vt监控传感器; 以及比较器，用于从提供输出标志信号的参考和监视传感器接收输入。 MOSFET器件电压阈值的偏移可以监视工艺变化，几何感应，等离子体损伤，应力和热载体以及其他器件损坏。相同的电路还测量集成电路芯片或晶片中的任何两个节点之间的电压差。

30. 发明申请

US20080079172A1 METHOD FOR FABRICATING AND BEOL INTERCONNECT STRUCTURES WITH SIMULTANEOUS FORMATION OF HIGH-K AND LOW-K DIELECTRIC REGIONS 有权
标题翻译：同时形成高K和低K介电区域的制造和波形互连结构的方法
公开(公告)号：US20080079172A1
公开(公告)日：2008-04-03
申请号：US11939671
申请日：2007-11-14
申请人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
发明人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
IPC分类号： H01L23/52
CPC分类号： H01L23/5329 , H01L21/7682 , H01L21/76849 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , Y10S438/942 , H01L2924/00
摘要： A method for fabricating and back-end-of-line (BEOL) metalization structures includes simultaneous high-k and low-k dielectric regions. An interconnect structure includes a first inter-level dielectric (ILD) layer and a second ILD layer with the first ILD layer underlying the second ILD layer. A plurality of columnar air gaps is formed in the first ILD. The columnar air gap structure is created using a two-phase photoresist material for providing different etching selectivity during subsequent processing.
摘要翻译：一种用于制造和后端（BEOL）金属化结构的方法包括同时存在的高k和低k电介质区域。互连结构包括第一层间电介质（ILD）层和具有位于第二ILD层下面的第一ILD层的第二ILD层。在第一ILD中形成多个柱状气隙。使用两相光致抗蚀剂材料制造柱状气隙结构，用于在随后的处理期间提供不同的蚀刻选择性。

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