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21. 发明授权

US07304380B2 Integrated circuit cooling and insulating device and method 有权
标题翻译：集成电路冷却和绝缘装置及方法
公开(公告)号：US07304380B2
公开(公告)日：2007-12-04
申请号：US11482308
申请日：2006-07-07
申请人： Paul A. Farrar , Leonard Forbes , Kie Y. Ahn , Joseph E. Geusic , Arup Bhattacharyya , Alan R. Reinberg
发明人： Paul A. Farrar , Leonard Forbes , Kie Y. Ahn , Joseph E. Geusic , Arup Bhattacharyya , Alan R. Reinberg
IPC分类号： H01L23/34
CPC分类号： H01L23/427 , G01R31/2817 , H01L2924/0002 , H01L2924/00
摘要： A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge structures is provided. A method and device using a boiling liquid to cool circuit structures is provided. Further provided is a method of controlling chip temperature. This allows circuit and device designers an opportunity to design more efficient structures. Some properties that exhibit less variation when temperature ranges are controlled include electromigration, conductivity, operating speed, and reliability.
摘要翻译：提供一种用于冷却集成电路的方法和装置。提供了使用气体来冷却诸如多个空气桥结构之类的电路结构的方法和装置。提供了一种使用沸腾液体来冷却电路结构的方法和装置。还提供了一种控制芯片温度的方法。这允许电路和设备设计者有机会设计更有效的结构。在温度范围被控制时表现出较小变化的一些性质包括电迁移，电导率，操作速度和可靠性。

22. 发明授权

US07242049B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US07242049B2
公开(公告)日：2007-07-10
申请号：US10461593
申请日：2003-06-11
申请人： Leonard Forbes , Joseph E. Geusic
发明人： Leonard Forbes , Joseph E. Geusic
IPC分类号： H10L29/788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L27/10805 , H01L27/10873
摘要： A floating gate transistor has a reduced barrier energy at an interface with an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the floating gate is reduced. The data stored on the floating gate is dynamically refreshed. The floating gate transistor provides a dense and planar dynamic electrically alterable and programmable read only memory (DEAPROM) cell adapted for uses such as for a dynamic random access memory (DRAM) or a dynamically refreshed flash EEPROM memory. The floating gate transistor provides a high gain memory cell and low voltage operation.
摘要翻译：浮栅晶体管在与相邻栅极绝缘体的界面处具有降低的势垒能，允许在较低电压下跨越栅极绝缘体的更快的电荷转移。数据作为电荷存储在浮动栅极上。浮动栅极上的数据电荷保留时间减少。存储在浮动门上的数据被动态刷新。浮栅晶体管提供了适用于诸如用于动态随机存取存储器（DRAM）或动态刷新的快闪EEPROM存储器的密集且平面的动态电可更改和可编程只读存储器（DEAPROM）单元。浮栅晶体管提供高增益存储单元和低电压工作。

23. 发明授权

US06709978B2 Method for forming integrated circuits using high aspect ratio vias through a semiconductor wafer 有权
标题翻译：使用通过半导体晶片的高纵横比通孔形成集成电路的方法
公开(公告)号：US06709978B2
公开(公告)日：2004-03-23
申请号：US09800373
申请日：2001-03-06
申请人： Joseph E. Geusic , Kie Y. Ahn , Leonard Forbes
发明人： Joseph E. Geusic , Kie Y. Ahn , Leonard Forbes
IPC分类号： H01L2144
CPC分类号： H01L23/48 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated circuit and method for forming the same. The integrated circuit includes a semiconductor wafer with first and second surfaces. A functional circuit is formed on the first surface of the semiconductor wafer. Further, a metallization layer is formed outwardly from the first surface of the semiconductor wafer. The integrated circuit also includes at least one high aspect ratio via that extends through the layer of semiconductor material. This via provides a connection between a lead and the functional circuit.
摘要翻译：一种集成电路及其形成方法。集成电路包括具有第一和第二表面的半导体晶片。在半导体晶片的第一表面上形成功能电路。此外，从半导体晶片的第一表面向外形成金属化层。集成电路还包括延伸穿过半导体材料层的至少一个高纵横比通孔。该通孔提供引线和功能电路之间的连接。

24. 发明授权

US06526191B1 Integrated circuits using optical fiber interconnects formed through a semiconductor wafer and methods for forming same 有权
标题翻译：使用通过半导体晶片形成的光纤互连的集成电路及其形成方法
公开(公告)号：US06526191B1
公开(公告)日：2003-02-25
申请号：US09642960
申请日：2000-08-21
申请人： Joseph E. Geusic , Kie Y. Ahn , Leonard Forbes
发明人： Joseph E. Geusic , Kie Y. Ahn , Leonard Forbes
IPC分类号： G02B612
CPC分类号： G02B6/43 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit with a number of optical fibers that are formed in high aspect ratio holes. The high aspect ratio holes extend through a semiconductor wafer. The optical fibers include a cladding layer and a core formed in the high aspect ratio hole. These optical fibers are used to transmit signals between functional circuits on the semiconductor wafer and functional circuits on the back of the wafer or beneath the wafer.
摘要翻译：具有形成在高纵横比孔中的多根光纤的集成电路。高纵横比孔延伸穿过半导体晶片。光纤包括形成在高纵横比孔中的包覆层和芯。这些光纤用于在半导体晶片上的功能电路和晶片背面或晶片之下的功能电路之间传输信号。

25. 发明授权

US06476441B2 Method and structure for textured surfaces in floating gate tunneling oxide devices 有权
标题翻译：浮栅隧道氧化器件中纹理表面的方法和结构
公开(公告)号：US06476441B2
公开(公告)日：2002-11-05
申请号：US09873701
申请日：2001-06-04
申请人： Joseph E. Geusic , Leonard Forbes
发明人： Joseph E. Geusic , Leonard Forbes
IPC分类号： H01L29788
CPC分类号： H01L21/28273 , H01L29/511 , H01L29/7883
摘要： A method and structure for textured surfaces in non volatile floating gate tunneling oxide (FLOTOX) devices, e.g. FLOTOX transistors, are provided. The present invention capitalizes on using “self-structured masks” and a controlled etch to form nanometer scale microtip arrays in the textured surfaces. The microtips in the array of microtips have a more uniform size and shape and higher density (˜1012/cm2) at the substrate/tunnel oxide (Si/SiO2) interface than in current generation FLOTOX transistors. This higher density is four orders of magnitude greater than that which has been in use with FLOTOX transistor technology. In result, the new method and structure produce significantly larger tunneling currents for a given voltage than attained in prior work. The new method and structure are advantageously suited for the much higher density, non volatile FLOTOX transistors desired for use in flash memories and in electronically erasable and programmable read only memories (EEPROMs). These FLOTOX transistors are candidates for replacing the low power operation transistors found in DRAMs.
摘要翻译：非挥发性浮栅隧道氧化物（FLOTOX）器件中的纹理表面的方法和结构，例如。 FLOTOX晶体管。本发明利用“自组织掩模”和受控蚀刻在纹理化表面中形成纳米级微尖头阵列。微尖端阵列中的微尖端在衬底/隧道氧化物（Si / SiO 2）界面处具有比当前一代FLOTOX晶体管更大的尺寸和形状以及更高的密度（〜1012 / cm2）。这种更高的密度比使用FLOTOX晶体管技术的密度高四个数量级。结果，对于给定的电压，新的方法和结构产生明显较大的隧道电流，这在以前的工作中获得。新的方法和结构有利地适用于期望用于闪存和电可擦除和可编程只读存储器（EEPROM）的更高密度，非易失性FLOTOX晶体管。这些FLOTOX晶体管是替代在DRAM中发现的低功率运算晶体管的候选者。

26. 发明授权

US06351411B2 Memory using insulator traps 有权
标题翻译：内存使用绝缘子陷阱
公开(公告)号：US06351411B2
公开(公告)日：2002-02-26
申请号：US09879453
申请日：2001-06-12
申请人： Leonard Forbes , Joseph E. Geusic
发明人： Leonard Forbes , Joseph E. Geusic
IPC分类号： G11C1134
CPC分类号： G11C11/5671 , B82Y10/00 , G11C16/0458 , G11C2216/08 , H01L29/7887 , H01L29/7888 , H01L29/792 , H01L29/7923
摘要： A memory cell provides point defect trap sites in an insulator for storing data charges. Single electrons are stored on respective point defect trap sites and a resulting parameter, such as transistor drain current, is detected. By adjusting the density of the point defect trap sites, more uniform step changes in drain current are obtained as single electrons are stored on or removed from respective trap sites. By also adjusting the trapping energy of the point defect trap sites, the memory cell provides either volatile data storage, similar to a dynamic random access memory (DRAM), or nonvolatile data storage, similar to an electrically erasable and programmable read only memory (EEPROM). The memory cell is used for storing binary or multi-state data.
摘要翻译：存储单元在绝缘体中提供用于存储数据电荷的点缺陷陷阱位置。单个电子存储在相应的点缺陷陷阱位置，并且检测到所得到的参数，例如晶体管漏极电流。通过调整点缺陷陷阱位置的密度，可以获得漏极电流的更均匀的阶跃变化，因为单个电子存储在相应的陷阱位置上或从各陷阱位置移除。通过调整点缺陷陷阱位点的捕获能量，存储单元提供类似于动态随机存取存储器（DRAM）的易失性数据存储器，或类似于电可擦除和可编程只读存储器（EEPROM）的非易失性数据存储器）。存储单元用于存储二进制或多状态数据。

27. 发明授权

US06232643B1 Memory using insulator traps 失效
公开(公告)号：US06232643B1
公开(公告)日：2001-05-15
申请号：US08969099
申请日：1997-11-13
申请人： Leonard Forbes , Joseph E. Geusic
发明人： Leonard Forbes , Joseph E. Geusic
IPC分类号： H01L29792
CPC分类号： G11C11/5671 , B82Y10/00 , G11C16/0458 , G11C2216/08 , H01L29/7887 , H01L29/7888 , H01L29/792 , H01L29/7923
摘要： A memory cell provides point defect trap sites in an insulator for storing data charges. Single electrons are stored on respective point defect trap sites and a resulting parameter, such as transistor drain current, is detected. By adjusting the density of the point defect trap sites, more uniform step changes in drain current are obtained as single electrons are stored on or removed from respective trap sites. By also adjusting the trapping energy of the point defect trap sites, the memory cell provides either volatile data storage, similar to a dynamic random access memory (DRAM), or nonvolatile data storage, similar to an electrically erasable and programmable read only memory (EEPROM). The memory cell is used for storing binary or multi-state data.

28. 发明授权

US6150188A Integrated circuits using optical fiber interconnects formed through a semiconductor wafer and methods for forming same 失效
公开(公告)号：US6150188A
公开(公告)日：2000-11-21
申请号：US31975
申请日：1998-02-26
申请人： Joseph E. Geusic , Kie Y. Ahn , Leonard Forbes
发明人： Joseph E. Geusic , Kie Y. Ahn , Leonard Forbes
IPC分类号： G02B6/43 , H01L23/48 , H01L21/00
CPC分类号： G02B6/43 , H01L23/481 , H01L2924/0002
摘要： An integrated circuit with a number of optical fibers that are formed in high aspect ratio holes. The high aspect ratio holes extend through a semiconductor wafer. The optical fibers include a cladding layer and a core formed in the high aspect ratio hole. These optical fibers are used to transmit signals between functional circuits on the semiconductor wafer and functional circuits on the back of the wafer or beneath the wafer.

29. 发明授权

US6140181A Memory using insulator traps 有权
公开(公告)号：US6140181A
公开(公告)日：2000-10-31
申请号：US394109
申请日：1999-09-10
申请人： Leonard Forbes , Joseph E. Geusic
发明人： Leonard Forbes , Joseph E. Geusic
IPC分类号： G11C11/56 , G11C16/04 , H01L29/788 , H01L29/792 , H01L21/336
CPC分类号： G11C11/5671 , B82Y10/00 , G11C16/0458 , H01L29/7887 , H01L29/7888 , G11C2216/08 , H01L29/792 , H01L29/7923
摘要： A memory cell provides point defect trap sites in an insulator for storing data charges. Single electrons are stored on respective point defect trap sites and a resulting parameter, such as transistor drain current, is detected. By adjusting the density of the point defect trap sites, more uniform step changes in drain current are obtained as single electrons are stored on or removed from respective trap sites. By also adjusting the trapping energy of the point defect trap sites, the memory cell provides either volatile data storage, similar to a dynamic random access memory (DRAM), or nonvolatile data storage, similar to an electrically erasable and programmable read only memory (EEPROM). The memory cell is used for storing binary or multi-state data.

30. 发明授权

US6090636A Integrated circuits using optical waveguide interconnects formed through a semiconductor wafer and methods for forming same 失效
公开(公告)号：US6090636A
公开(公告)日：2000-07-18
申请号：US31961
申请日：1998-02-26
申请人： Joseph E. Geusic , Kie Y. Ahn , Leonard Forbes
发明人： Joseph E. Geusic , Kie Y. Ahn , Leonard Forbes
IPC分类号： G02B6/032 , G02B6/136 , G02B6/42 , G02B6/43 , H01L21/302
CPC分类号： G02B6/032 , G02B6/12002 , G02B6/136 , G02B6/43 , G02B6/42
摘要： An integrated circuit with a number of optical waveguides that are formed in high aspect ratio holes. The high aspect ratio holes extend through a semiconductor wafer. The optical waveguides include a highly reflective material that is deposited so as to line an inner surface of the high aspect ratio holes which may be filled with air or a material with an index of refraction that is greater than 1. These metal confined waveguides are used to transmit signals between functional circuits on the semiconductor wafer and functional circuits on the back of the wafer or beneath the wafer.

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