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21. 发明授权

US5983256A Apparatus for performing multiply-add operations on packed data 失效
标题翻译：用于对打包数据执行加法运算的装置
公开(公告)号：US5983256A
公开(公告)日：1999-11-09
申请号：US960413
申请日：1997-10-29
申请人： Alexander Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
发明人： Alexander Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
IPC分类号： G06F7/48 , G06F7/52 , G06F7/533 , G06F7/544 , G06F9/302 , G06F15/78 , G06F17/14 , G06F17/16 , G06T1/20 , G06F7/38 , G06F7/00 , G06F15/00
CPC分类号： G06F7/60 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F7/4812 , G06F7/5324 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06T1/20 , G06F2207/3828 , G06F7/49921 , G06F7/5338
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.
摘要翻译：一种用于在处理器中包括用于对压缩数据进行乘法运算的指令的方法和装置。在一个实施例中，处理器耦合到存储器。存储器中存储有第一打包数据和第二打包数据。处理器对所述第一打包数据和所述第二打包数据中的数据元素执行操作，以响应于接收到指令而产生第三打包数据。该第三打包数据中的至少两个数据元素存储对第一和第二打包数据中的数据元素执行加法运算的结果。

22. 发明申请

US20130091190A1 PROCESSOR FOR PERFORMING MULTIPLY-ADD OPERATIONS ON PACKED DATA 失效
公开(公告)号：US20130091190A1
公开(公告)日：2013-04-11
申请号：US13633086
申请日：2012-10-01
申请人： Alexander Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf C. Witt
发明人： Alexander Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf C. Witt
IPC分类号： G06F7/60
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

23. 发明授权

US5721892A Method and apparatus for performing multiply-subtract operations on packed data 失效
标题翻译：对打包数据进行乘法减法运算的方法和装置
公开(公告)号：US5721892A
公开(公告)日：1998-02-24
申请号：US554625
申请日：1995-11-06
申请人： Alexander Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Wolf Witt , Carole Dulong , Eiichi Kowashi
发明人： Alexander Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Wolf Witt , Carole Dulong , Eiichi Kowashi
IPC分类号： G06F7/544 , G06F7/38
CPC分类号： G06F9/30036 , G06F7/5443 , G06F2207/3828
摘要： A method and apparatus for including in a processor instructions for performing multiply-subtract operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least one of the data elements in this third packed data storing the result of performing a multiply-subtract operation on data elements in the first and second packed data.
摘要翻译：一种用于在处理器中包括用于对压缩数据进行乘法减法操作的指令的方法和装置。在一个实施例中，处理器耦合到存储器。存储器中存储有第一打包数据和第二打包数据。处理器对所述第一打包数据和所述第二打包数据中的数据元素执行操作，以响应于接收到指令而产生第三打包数据。该第三打包数据中的至少一个数据元素存储对第一和第二打包数据中的数据元素进行乘法运算的结果。

24. 发明授权

US08396915B2 Processor for performing multiply-add operations on packed data 失效
公开(公告)号：US08396915B2
公开(公告)日：2013-03-12
申请号：US13603370
申请日：2012-09-04
申请人： Alexander Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf C. Witt
发明人： Alexander Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf C. Witt
IPC分类号： G06F7/38
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

25. 发明申请

US20130198254A1 PROCESSOR FOR PERFORMING MULTIPLY-ADD OPERATIONS ON PACKED DATA 有权
公开(公告)号：US20130198254A1
公开(公告)日：2013-08-01
申请号：US13801356
申请日：2013-03-13
申请人： Alexander Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf C. Witt
发明人： Alexander Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf C. Witt
IPC分类号： G06F17/10
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

26. 发明授权

US5859997A Method for performing multiply-substrate operations on packed data 失效
标题翻译：对打包数据进行乘法减法运算的方法
公开(公告)号：US5859997A
公开(公告)日：1999-01-12
申请号：US699993
申请日：1996-08-20
申请人： Alexander Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Wolf Witt , Carole Dulong , Eiichi Kowashi
发明人： Alexander Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Wolf Witt , Carole Dulong , Eiichi Kowashi
IPC分类号： G06F7/544 , G06F9/00
CPC分类号： G06F9/30036 , G06F7/5443 , G06F2207/3828
摘要： A method and apparatus for including in a processor instructions for performing multiply-subtract operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least one of the data elements in this third packed data storing the result of performing a multiply-subtract operation on data elements in the first and second packed data.
摘要翻译：一种用于在处理器中包括用于对压缩数据进行乘法减法操作的指令的方法和装置。在一个实施例中，处理器耦合到存储器。存储器中存储有第一打包数据和第二打包数据。处理器对所述第一打包数据和所述第二打包数据中的数据元素执行操作，以响应于接收到指令而产生第三打包数据。该第三打包数据中的至少一个数据元素存储对第一和第二打包数据中的数据元素进行乘法运算的结果。

27. 发明申请

US20130219151A1 PROCESSOR FOR PERFORMING MULTIPLY-ADD OPERATIONS ON PACKED DATA 失效
公开(公告)号：US20130219151A1
公开(公告)日：2013-08-22
申请号：US13801335
申请日：2013-03-13
申请人： Alexander Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf C. Witt
发明人： Alexander Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf C. Witt
IPC分类号： G06F9/30
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

28. 发明授权

US08495123B2 Processor for performing multiply-add operations on packed data 失效
标题翻译：用于对打包数据执行加法运算的处理器
公开(公告)号：US08495123B2
公开(公告)日：2013-07-23
申请号：US13633086
申请日：2012-10-01
申请人： Alexander Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf C. Witt
发明人： Alexander Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf C. Witt
IPC分类号： G06F7/38
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.
摘要翻译：一种用于在处理器中包括用于对压缩数据进行乘法运算的指令的方法和装置。在一个实施例中，处理器耦合到存储器。存储器中存储有第一打包数据和第二打包数据。处理器对所述第一打包数据和所述第二打包数据中的数据元素执行操作，以响应于接收到指令而产生第三打包数据。该第三打包数据中的至少两个数据元素存储对第一和第二打包数据中的数据元素执行加法运算的结果。

29. 发明授权

US5835392A Method for performing complex fast fourier transforms (FFT's) 失效
标题翻译：执行复杂快速傅立叶变换（FFT）的方法
公开(公告)号：US5835392A
公开(公告)日：1998-11-10
申请号：US580467
申请日：1995-12-28
申请人： Carole Dulong , Larry M. Mennemeier , Eiichi Kowashi , Alexander D. Peleg , Stephen A. Fischer
发明人： Carole Dulong , Larry M. Mennemeier , Eiichi Kowashi , Alexander D. Peleg , Stephen A. Fischer
IPC分类号： G06F17/14 , G06F15/00 , G06F7/38
CPC分类号： G06F17/142 , G06F9/3001 , G06F9/30036 , G06F9/30109 , G06F9/3013
摘要： A method in a computer system of performing a butterfly stage of a complex fast fourier transform of two input signals. First, a packed multiply add is performed on a first packed complex value generated from a first input signal and a set of trigonometric values to generate a first product. Then, a second product is generated which comprises the first product with a sign inverted. A packed add of the second product and a second complex value generated from a second input signal is performed to generate a first result, and the first product and the second complex value to generate a second result.
摘要翻译：一种执行两个输入信号的复杂快速傅里叶变换的蝶形阶段的计算机系统中的方法。首先，对从第一输入信号和一组三角值生成的第一打包复数值执行打包乘法加法，以生成第一乘积。然后，产生第二产品，其包括具有倒牌的第一产品。执行第二产品的打包添加和从第二输入信号产生的第二复数值以产生第一结果，以及第一乘积和第二复数值以产生第二结果。

30. 发明授权

US06823353B2 Method and apparatus for multiplying and accumulating complex numbers in a digital filter 失效
标题翻译：用于在数字滤波器中乘法和累加复数的方法和装置
公开(公告)号：US06823353B2
公开(公告)日：2004-11-23
申请号：US10211203
申请日：2002-08-02
申请人： Stephen A. Fischer , Larry M. Mennemeier , Alexander D. Peleg , Carole Dulong , Eiichi Kowashi
发明人： Stephen A. Fischer , Larry M. Mennemeier , Alexander D. Peleg , Carole Dulong , Eiichi Kowashi
IPC分类号： G06F752
CPC分类号： G06F17/10
摘要： The invention provides a method and apparatus for performing complex digital filters. According to one aspect of the invention, a method for performing a complex digital filter is described. The complex digital filter is performed using a set of data samples and a set of complex coefficients. In addition, the complex digital filter is performed using a inner and outer loop. The outer loop steps through a number of corresponding relationships between the set of complex coefficients and the set of data samples. The inner loop steps thorough each complex coefficient in the set of complex coefficients. Within the inner loop, the data sample corresponding to the current complex coefficient (the complex coefficient currently identified by the inner loop) is determined according to the current corresponding relationship (the corresponding relationship currently identified by the outer loop). Then, in response to receiving an instruction, eight data elements are read and used to generate a currently calculated complex number. These eight data elements were previously stored as packed data and include two representations of each of the components of the current complex coefficient and its current corresponding data sample. Each of these data elements is either the positive or negative of the component they represent. As a result of the manner in which these eight data elements are stored, the currently calculated complex number represents the product of the current complex coefficient and its current corresponding data sample. The currently calculated complex number is then added to the current output packed data.
摘要翻译：本发明提供一种用于执行复杂数字滤波器的方法和装置。根据本发明的一个方面，描述了一种用于执行复数数字滤波器的方法。使用一组数据样本和一组复系数来执行复数数字滤波器。另外，使用内循环和外循环执行复数数字滤波器。外循环遍历复系数集合和数据样本集之间的若干对应关系。内循环遍及复系数集合中的每个复系数。在内循环中，根据当前对应关系（当前由外循环确定的对应关系）确定对应于当前复系数（由内循环确定的复系数）的数据样本。然后，响应于接收到指令，读取并使用八个数据元素来生成当前计算的复数。这八个数据元素预先存储为打包数据，并且包括当前复系数及其当前相应数据样本的每个分量的两个表示。这些数据元素中的每一个都是它们表示的组件的正或负。作为存储这八个数据元素的方式的结果，当前计算的复数代表当前复系数和其当前相应数据样本的乘积。然后将当前计算的复数加到当前输出的打包数据中。

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