专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US07620749B2 Descriptor prefetch mechanism for high latency and out of order DMA device 有权
标题翻译：高延迟和无序的DMA设备的描述符预取机制
公开(公告)号：US07620749B2
公开(公告)日：2009-11-17
申请号：US11621789
申请日：2007-01-10
申请人： Giora Biran , Luis E. De la Torre , Bernard C. Drerup , Jyoti Gupta , Richard Nicholas
发明人： Giora Biran , Luis E. De la Torre , Bernard C. Drerup , Jyoti Gupta , Richard Nicholas
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A DMA device prefetches descriptors into a descriptor prefetch buffer. The size of descriptor prefetch buffer holds an appropriate number of descriptors for a given latency environment. To support a linked list of descriptors, the DMA engine prefetches descriptors based on the assumption that they are sequential in memory and discards any descriptors that are found to violate this assumption. The DMA engine seeks to keep the descriptor prefetch buffer full by requesting multiple descriptors per transaction whenever possible. The bus engine fetches these descriptors from system memory and writes them to the prefetch buffer. The DMA engine may also use an aggressive prefetch where the bus engine requests the maximum number of descriptors that the buffer will support whenever there is any space in the descriptor prefetch buffer. The DMA device discards any remaining descriptors that cannot be stored.
摘要翻译： DMA设备将描述符预取到描述符预取缓冲区中。描述符预取缓冲区的大小在给定的等待时间环境中保存适当数量的描述符。为了支持描述符的链表，DMA引擎基于它们在存储器中是连续的假设来预取描述符，并丢弃任何被发现违反这个假设的描述符。 DMA引擎寻求通过每个事务请求多个描述符尽可能地保持描述符预取缓冲区已满。总线引擎从系统内存中读取这些描述符，并将它们写入预取缓冲区。 DMA引擎还可以使用积极的预取，其中总线引擎请求缓冲区将在描述符预取缓冲器中存在任何空间时将支持的最大数量的描述符。 DMA设备丢弃任何其他不能存储的描述符。

22. 发明申请

US20080168191A1 Barrier and Interrupt Mechanism for High Latency and Out of Order DMA Device 失效
标题翻译：高延迟和高阶DMA设备的屏障和中断机制
公开(公告)号：US20080168191A1
公开(公告)日：2008-07-10
申请号：US11621776
申请日：2007-01-10
申请人： Giora Biran , Luis E. De la Torre , Bernard C. Drerup , Jyoti Gupta , Richard Nicholas
发明人： Giora Biran , Luis E. De la Torre , Bernard C. Drerup , Jyoti Gupta , Richard Nicholas
IPC分类号： G06F13/28 , G06F12/14
CPC分类号： G06F13/28
摘要： A direct memory access (DMA) device includes a barrier and interrupt mechanism that allows interrupt and mailbox operations to occur in such a way that ensures correct operation, but still allows for high performance out-of-order data moves to occur whenever possible. Certain descriptors are defined to be “barrier descriptors.” When the DMA device encounters a barrier descriptor, it ensures that all of the previous descriptors complete before the barrier descriptor completes. The DMA device further ensures that any interrupt generated by a barrier descriptor will not assert until the data move associated with the barrier descriptor completes. The DMA controller only permits interrupts to be generated by barrier descriptors. The barrier descriptor concept also allows software to embed mailbox completion messages into the scatter/gather linked list of descriptors.
摘要翻译：直接存储器访问（DMA）设备包括屏障和中断机制，允许中断和邮箱操作以确保正确操作的方式发生，但仍然允许在可能的情况下发生高性能无序数据移动。某些描述符被定义为“屏障描述符”。当DMA设备遇到屏障描述符时，它确保所有先前的描述符在屏障描述符完成之前完成。 DMA设备进一步确保在与屏障描述符关联的数据移动完成之前，屏障描述符产生的任何中断都不会断言。 DMA控制器仅允许由屏障描述符生成中断。屏障描述符概念还允许软件将邮箱完成消息嵌入到描述符的分散/收集链接列表中。

23. 发明授权

US07395380B2 Selective snooping by snoop masters to locate updated data 失效
标题翻译：通过窥探大师进行选择性窥探以查找更新的数据
公开(公告)号：US07395380B2
公开(公告)日：2008-07-01
申请号：US10393116
申请日：2003-03-20
申请人： James N. Dieffenderfer , Bernard C. Drerup , Jaya P. Ganasan , Richard G. Hofmann , Thomas A. Sartorius , Thomas P. Speier , Barry J. Wolford
发明人： James N. Dieffenderfer , Bernard C. Drerup , Jaya P. Ganasan , Richard G. Hofmann , Thomas A. Sartorius , Thomas P. Speier , Barry J. Wolford
IPC分类号： G06F12/00 , G06F3/00
CPC分类号： G06F12/0831 , Y02D10/13
摘要： A method and structure for snooping cache memories of several snooping masters connected to a bus macro, wherein each non-originating snooping master has cache memory, and wherein some, but less than all the cache memories, may have the data requested by an originating snooping master and wherein the needed data in a non-originating snooping master is marked as updated, and wherein a main memory having addresses for all data is connected to the bus macro.Only those non-originating snooping masters which may have the requested data are queried. All the non-originating snooping masters that have been queried reply. If a non-originating snooping master has the requested data marked as updated, that non-originating snooping master returns the updated data to the originating snooping master and possibly to the main memory. If none of the non-originating snooping masters has the requested data marked as updated, then the requested data is read from main memory.
摘要翻译：一种用于窥探连接到总线宏的多个窥探主机的高速缓冲存储器的方法和结构，其中每个非起始侦听主机具有高速缓冲存储器，并且其中一些但是小于所有高速缓存存储器可以具有由始发侦听器请求的数据主站，并且其中非起始侦听主控器中的所需数据被标记为更新，并且其中具有用于所有数据的地址的主存储器连接到总线宏。只有那些可能具有请求的数据的非始发侦听主机才被查询。所有被查询的非始发侦听主人都回复。如果非始发侦听主机具有被标记为更新的请求数据，则该非起始侦听主机会将更新的数据返回给始发侦听主机，并将其返回到主内存。如果非始发侦听主机中没有一个被标记为已更新的请求数据，则从主存储器读取所请求的数据。

24. 发明授权

US07065595B2 Method and apparatus for bus access allocation 失效
标题翻译：总线接入分配的方法和装置
公开(公告)号：US07065595B2
公开(公告)日：2006-06-20
申请号：US10249271
申请日：2003-03-27
申请人： Bernard C. Drerup , Jaya P. Ganasan , Richard G. Hofmann
发明人： Bernard C. Drerup , Jaya P. Ganasan , Richard G. Hofmann
IPC分类号： G06F13/362
CPC分类号： G06F13/3625
摘要： A method for granting access to a bus is disclosed where a fair arbitration is modified to account for varying conditions. Each bus master (BM) is assigned a Grant Balance Factor value (hereafter GBF) that corresponds to a desired bandwidth from the bus. Arbitration gives priority BMs with a GBF greater than zero in a stratified protocol where requesting BMs with the same highest priority are granted access first. The GBF of a BM is decremented each time an access is granted. Requesting BMs with a GBF equal to zero are fairly arbitrated when there are no requesting BMs with GBFs greater than zero wherein they receive equal access using a frozen arbiter status. The bus access time may be partitioned into bus intervals (BIs) each comprising N clock cycles. BIs and GBFs may be modified to guarantee balanced access over multiple BIs in response to error conditions or interrupts.
摘要翻译：公开了一种允许访问总线的方法，其中公平仲裁被修改以解决变化的条件。为每个总线主机（BM）分配一个与总线所需带宽对应的授权平衡因子值（以下称为GBF）。仲裁在分层协议中给予GBF大于零的优先级BM，其中首先授予具有相同最高优先权的BM。每次授予访问权限时，BM的GBF都将递减。当没有请求具有大于零的GBF的BM时，请求具有等于零的GBF的BM被相当地仲裁，其中它们使用冷冻仲裁器状态接收相等的访问。总线访问时间可以被划分为每个包括N个时钟周期的总线间隔（BI）。可以修改BI和GBF，以保证响应于错误条件或中断而在多个BI上进行平衡访问。

25. 发明授权

US5333285A System crash detect and automatic reset mechanism for processor cards 失效
标题翻译：处理器卡的系统崩溃检测和自动复位机制
公开(公告)号：US5333285A
公开(公告)日：1994-07-26
申请号：US795562
申请日：1991-11-21
申请人： Bernard C. Drerup
发明人： Bernard C. Drerup
IPC分类号： G06F1/24 , G06F11/00 , G06F11/14
CPC分类号： G06F11/1415 , G06F11/0757 , G06F11/0763
摘要： A hardware and software mechanism is provided for ensuring that a feature processor card, included with other feature cards in a host system, can be reset without interrupting software running on other feature cards. A delay is provided that starts counting each time a watchdog timer expires. If the watchdog timer is reset by an interrupt service routine, then the feature card processor is assumed to be reset. But, if the watchdog timer is not reset before the delay timer expires, then it is assumed that service routine is corrupt and that external reset of the feature card is required. Upon expiration of the watchdog, an error signal is sent, via the system bus, to the host CPU. Recovery code that is resident on the host CPU is then run and resets the CPU on the feature card. A reset signal is output from the host CPU, via the system bus, to a reset register on the feature card which then forwards the signal to the feature card CPU, thereby initiating reset of the system.
摘要翻译：提供了一种硬件和软件机制，用于确保与主机系统中的其他功能卡一起提供的功能处理器卡可以在不中断其他功能卡上运行的软件的情况下进行复位。提供延迟，每次看门狗定时器到期时都会开始计数。如果看门狗定时器由中断服务程序复位，则功能卡处理器被假定为复位。但是，如果在延迟定时器到期之前看门狗定时器未复位，则假定服务程序已损坏，并且需要外部复位功能卡。看门狗到期后，通过系统总线将错误信号发送到主机CPU。然后运行驻留在主机CPU上的恢复代码，并将功能卡上的CPU复位。复位信号从主机CPU经由系统总线输出到特征卡上的复位寄存器，然后将该信号转发到特征卡CPU，从而启动系统复位。

26. 发明授权

US07987437B2 Structure for piggybacking multiple data tenures on a single data bus grant to achieve higher bus utilization 失效
标题翻译：在单个数据总线上搭载多个数据期限的结构，以实现更高的总线利用率
公开(公告)号：US07987437B2
公开(公告)日：2011-07-26
申请号：US12112818
申请日：2008-04-30
申请人： Bernard C. Drerup , Richard Nicholas
发明人： Bernard C. Drerup , Richard Nicholas
IPC分类号： G06F17/50 , G06F13/36 , G06F13/00 , H04L12/28
CPC分类号： G06F13/364
摘要： A design structure for piggybacking multiple data tenures on a single data bus grant to achieve higher bus utilization is disclosed. In one embodiment of the design structure, a method in a computer-aided design system includes a source device sending a request for a bus grant to deliver data to a data bus connecting a source device and a destination device. The device receives the bus grant and logic within the device determines whether the bandwidth of the data bus allocated to the bus grant will be filled by the data. If the bandwidth of the data bus allocated to the bus grant will not be filled by the data, the device appends additional data to the first data and delivers the combined data to the data bus during the bus grant for the first data. When the bandwidth of the data bus allocated to the bus grant will be filled by the first data, the device delivers only the first data to the data bus during the bus grant.
摘要翻译：公开了一种用于在单个数据总线上搭载多个数据期限以实现更高总线利用率的设计结构。在设计结构的一个实施例中，计算机辅助设计系统中的一种方法包括发送对总线许可的请求的源设备，以向连接源设备和目的地设备的数据总线传送数据。设备接收总线许可，并且设备内的逻辑确定分配给总线授权的数据总线的带宽是否将被数据填充。如果分配给总线授权的数据总线的带宽不会被数据填充，则设备将附加数据附加到第一个数据，并在第一个数据的总线授权期间将组合的数据传送到数据总线。当分配给总线授权的数据总线的带宽将由第一个数据填充时，设备在总线授权期间只将第一个数据传送到数据总线。

27. 发明授权

US07523228B2 Method for performing a direct memory access block move in a direct memory access device 失效
标题翻译：用于执行直接存储器访问块的方法在直接存储器访问设备中移动
公开(公告)号：US07523228B2
公开(公告)日：2009-04-21
申请号：US11532562
申请日：2006-09-18
申请人： Giora Biran , Luis E. De la Torre , Bernard C. Drerup , Jyoti Gupta , Richard Nicholas
发明人： Giora Biran , Luis E. De la Torre , Bernard C. Drerup , Jyoti Gupta , Richard Nicholas
IPC分类号： G06F13/28 , G06F3/00
CPC分类号： G06F13/28
摘要： A direct memory access (DMA) device is structured as a loosely coupled DMA engine (DE) and a bus engine (BE). The DE breaks the programmed data block moves into separate transactions, interprets the scatter/gather descriptors, and arbitrates among channels. The DE and BE use a combined read-write (RW) command that can be queued between the DE and the BE. The bus engine (BE) has two read queues and a write queue. The first read queue is for “new reads” and the second read queue is for “old reads,” which are reads that have been retried on the bus at least once. The BE gives absolute priority to new reads, and still avoids deadlock situations.
摘要翻译：直接存储器访问（DMA）设备被构造为松散耦合的DMA引擎（DE）和总线引擎（BE）。 DE将编程数据块移动到单独的事务中，解释分散/收集描述符，并在通道之间进行仲裁。 DE和BE使用可以在DE和BE之间排队的组合读写（RW）命令。总线引擎（BE）具有两个读队列和一个写队列。第一个读取队列是用于“新读取”，第二个读取队列用于“旧读取”，这是至少在总线上重试的读取。 BE绝对优先考虑新的读取，并且仍然避免死锁的情况。

28. 发明申请

US20080126602A1 DMA Controller with Support for High Latency Devices 失效
标题翻译：支持高延迟器件的DMA控制器
公开(公告)号：US20080126602A1
公开(公告)日：2008-05-29
申请号：US11532562
申请日：2006-09-18
申请人： Giora Biran , Luis E. De la Torre , Bernard C. Drerup , Jyoti Gupta , Richard Nicholas
发明人： Giora Biran , Luis E. De la Torre , Bernard C. Drerup , Jyoti Gupta , Richard Nicholas
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A direct memory access (DMA) device is structured as a loosely coupled DMA engine (DE) and a bus engine (BE). The DE breaks the programmed data block moves into separate transactions, interprets the scatter/gather descriptors, and arbitrates among channels. The DE and BE use a combined read-write (RW) command that can be queued between the DE and the BE. The bus engine (BE) has two read queues and a write queue. The first read queue is for “new reads” and the second read queue is for “old reads,” which are reads that have been retried on the bus at least once. The BE gives absolute priority to new reads, and still avoids deadlock situations.
摘要翻译：直接存储器访问（DMA）设备被构造为松散耦合的DMA引擎（DE）和总线引擎（BE）。 DE将编程数据块移动到单独的事务中，解释分散/收集描述符，并在通道之间进行仲裁。 DE和BE使用可以在DE和BE之间排队的组合读写（RW）命令。总线引擎（BE）具有两个读队列和一个写队列。第一个读取队列是用于“新读取”，第二个读取队列用于“旧读取”，这是至少在总线上重试的读取。 BE绝对优先考虑新的读取，并且仍然避免死锁的情况。

29. 发明授权

US07089376B2 Reducing snoop response time for snoopers without copies of requested data via snoop filtering 失效
标题翻译：通过窥探过滤减少窥探者的窥探响应时间，而无需复制所请求的数据
公开(公告)号：US07089376B2
公开(公告)日：2006-08-08
申请号：US10442485
申请日：2003-05-21
申请人： James N. Dieffenderfer , Bernard C. Drerup , Jaya P. Ganasan , Richard G. Hofmann , Thomas A. Sartorius , Thomas P. Speier , Barry J. Wolford
发明人： James N. Dieffenderfer , Bernard C. Drerup , Jaya P. Ganasan , Richard G. Hofmann , Thomas A. Sartorius , Thomas P. Speier , Barry J. Wolford
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , Y02D10/13
摘要： In a system having a plurality of snooping masters coupled to a Bus Macro, a snoop filtering device and method are provided in at least one of the plurality of snooping masters. The snoop filtering device and method parse a snoop request issued by one of the plurality of snooping masters and return an Immediate Response if parsing indicates the requested data cannot possibly be contained in a responding snooping master. If parsing indicates otherwise the at least one plurality of snoop masters searches its resources and returns the requested data if marked updated.
摘要翻译：在具有耦合到总线宏的多个窥探主器件的系统中，在多个窥探主机中的至少一个中提供窥探过滤装置和方法。窥探过滤设备和方法解析多个窥探主机之一发出的窥探请求，并且如果解析指示所请求的数据不可能包含在响应侦听主机中，则返回立即响应。如果解析指示，否则至少一个多个窥探大师搜索其资源并且如果标记更新则返回所请求的数据。

30. 发明授权

US06993619B2 Single request data transfer regardless of size and alignment 失效
公开(公告)号：US06993619B2
公开(公告)日：2006-01-31
申请号：US10249302
申请日：2003-03-28
申请人： Victor E. Augsburg , James N. Dieffenderfer , Bernard C. Drerup , Richard G. Hofmann , Thomas A. Sartorius , Barry J. Wolford
发明人： Victor E. Augsburg , James N. Dieffenderfer , Bernard C. Drerup , Richard G. Hofmann , Thomas A. Sartorius , Barry J. Wolford
IPC分类号： G06F13/40 , H04L12/56
CPC分类号： G06F13/4204 , Y02D10/14 , Y02D10/151
摘要： A method, computer system and set of signals are disclosed allowing for communication of a data transfer, via a bus, between a master and a slave using a single transfer request regardless of transfer size and alignment. The invention provides three transfer qualifier signals including: a first signal including a starting byte address of the data transfer; a second signal including a size of the data transfer in data beats; and a third signal including a byte enable for each byte required during a last data beat of the data transfer. The invention is usable with single or multiple beat, aligned or unaligned data transfers. Usage of the three transfer qualifier signals provides the slave with how many data beats it will transfer at the start of the transfer, and the alignment of both the starting and ending data beats. As a result, the slave need not calculate the number of bytes it will transfer. In terms of multiple beat transfers, the number of data transfer requests are reduced, which reduces the amount of switching, bus arbitration and power consumption required. In addition, the invention allows byte enable signals to be used for subsequent data transfer requests prior to the completion of the initial data transfer, which reduces power consumption and allows for pipelining of data transfer requests.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式