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21. 发明申请

US20100012941A1 THIN FILM TRANSISTOR ARRAY PANEL FOR LIQUID CRYSTAL DISPLAY HAVING PIXEL ELECTRODE 有权
标题翻译：带有像素电极的液晶显示器的薄膜晶体管阵列
公开(公告)号：US20100012941A1
公开(公告)日：2010-01-21
申请号：US12570505
申请日：2009-09-30
申请人： Dong-Gyu Kim , Hyang-Shik Kong , Jang-Soo Kim
发明人： Dong-Gyu Kim , Hyang-Shik Kong , Jang-Soo Kim
IPC分类号： H01L27/12 , H01L21/77
CPC分类号： G02F1/136213 , G02F1/1337 , G02F1/133784 , G02F1/134336 , G02F1/136227 , G02F2201/123
摘要： A TFT array panel includes an insulating substrate, a gate line and a storage electrode line formed thereon. The gate line and the storage electrode line are covered with a gate insulating layer, and a semiconductor island is formed on the gate insulating layer. A pair of ohmic contacts are formed on the semiconductor island, and a data line and a drain electrode are formed thereon. The data line and the drain electrode are covered with a passivation layer having a contact hole exposing the drain electrode. A pixel electrode is formed on the passivation layer and connected to the drain electrode through the contact hole. The TFT array panel is covered with an alignment layer rubbed approximately in a direction from the upper left corner to the lower right corner of the TFT array panel or the pixel electrodes. The pixel electrode has approximately a rectangular shape and overlaps the gate line and the data line. The pixel electrode has an expansion located near the upper left corner of the pixel electrode to increase the width of the corresponding overlapping area between the pixel electrode and the gate line and/or the data line.
摘要翻译： TFT阵列面板包括绝缘基板，栅极线和形成在其上的存储电极线。栅极线和存储电极线被栅极绝缘层覆盖，并且在栅极绝缘层上形成半导体岛。在半导体岛上形成一对欧姆接触，在其上形成数据线和漏电极。数据线和漏电极被具有暴露漏电极的接触孔的钝化层覆盖。像素电极形成在钝化层上，并通过接触孔与漏电极连接。 TFT阵列面板被大致沿着从TFT阵列板的左上角到右下角或像素电极的方向摩擦的取向膜覆盖。像素电极具有大致矩形形状并且与栅极线和数据线重叠。像素电极具有位于像素电极的左上角附近的扩展部，以增加像素电极与栅极线和/或数据线之间的对应重叠区域的宽度。

22. 发明申请

US20080203393A1 THIN FILM TRANSISTOR ARRAY PANEL AND FABRICATION 有权
标题翻译：薄膜晶体管阵列和制造
公开(公告)号：US20080203393A1
公开(公告)日：2008-08-28
申请号：US12099718
申请日：2008-04-08
申请人： Sang-Gab KIM , Woo-Geun Lee , Shi-Yul Kim , Jin-Ho Ju , Jang-Soo Kim , Sang-Woo Whangbo , Min-Seok Oh , Hye-Young Ryu , Hong-Kee Chin
发明人： Sang-Gab KIM , Woo-Geun Lee , Shi-Yul Kim , Jin-Ho Ju , Jang-Soo Kim , Sang-Woo Whangbo , Min-Seok Oh , Hye-Young Ryu , Hong-Kee Chin
IPC分类号： H01L27/088
CPC分类号： H01L27/124 , G02F2001/13629 , H01L29/458
摘要： The present invention provides a manufacturing method of a thin film transistor array panel, which includes forming a gate line on a substrate; forming a gate insulating layer, a semiconductor layer, and an ohmic contact on the gate line; forming a first conducting film including Mo, a second conducting film including Al, and a third conducting film including Mo on the ohmic contact; forming a first photoresist pattern on the third conducting film; etching the first, second, and third conducting films, the ohmic contact, and the semiconductor layer using the first photoresist pattern as a mask; removing the first photoresist pattern by a predetermined thickness to form a second photoresist pattern; etching the first, second, and third conducting films using the second photoresist pattern as a mask to expose a portion of the ohmic contact; and etching the exposed ohmic contact using a Cl-containing gas and a F-containing gas.
摘要翻译：本发明提供一种薄膜晶体管阵列面板的制造方法，其包括在基板上形成栅极线; 在栅极线上形成栅极绝缘层，半导体层和欧姆接触; 形成包括Mo的第一导电膜，包括Al的第二导电膜和在欧姆接触上包含Mo的第三导电膜; 在所述第三导电膜上形成第一光致抗蚀剂图案; 使用第一光致抗蚀剂图案作为掩模蚀刻第一，第二和第三导电膜，欧姆接触和半导体层; 将第一光致抗蚀剂图案去除预定厚度以形成第二光致抗蚀剂图案; 使用第二光致抗蚀剂图案作为掩模蚀刻第一，第二和第三导电膜以暴露欧姆接触的一部分; 并使用含Cl气体和含F气体蚀刻暴露的欧姆接触。

23. 发明授权

US07405798B2 Liquid crystal display apparatus and method of forming the same 失效
标题翻译：液晶显示装置及其形成方法
公开(公告)号：US07405798B2
公开(公告)日：2008-07-29
申请号：US10768333
申请日：2004-01-30
申请人： Young-Hoon Yoo , Jang-Soo Kim , Hye-Young Ryu
发明人： Young-Hoon Yoo , Jang-Soo Kim , Hye-Young Ryu
IPC分类号： G02F1/1339 , G02F1/1345
CPC分类号： G02F1/1339 , G02F1/133516 , G02F1/1345
摘要： A liquid crystal display device including a first substrate, a common electrode formed over the first substrate, and a second substrate disposed opposite the first substrate. A common voltage-applying member applies a common voltage to the common electrode and maintains a cell gap between the first substrate and the second substrate. The common voltage-applying member includes an insulator and a conductor formed over the insulator.
摘要翻译：一种液晶显示装置，包括第一基板，形成在第一基板上的公共电极以及与第一基板相对设置的第二基板。公共电压施加部件向公共电极施加公共电压，并且在第一基板和第二基板之间保持单元间隙。公共电压施加构件包括绝缘体和形成在绝缘体上的导体。

24. 发明申请

US20070139597A1 DISPLAY SUBSTRATE, METHOD OF MANUFACTURING THE SAME AND DISPLAY DEVICE HAVING THE SAME 审中-公开
标题翻译：显示基板，其制造方法和具有该基板的显示装置
公开(公告)号：US20070139597A1
公开(公告)日：2007-06-21
申请号：US11559589
申请日：2006-11-14
申请人： Yi-Seop Shim , Gug-Rae Jo , Byoung-Joo Kim , Ji-Won Choi , Jang-Soo Kim , Shi-Yul Kim , Jin-Ho Ju , Chong-Chul Chai
发明人： Yi-Seop Shim , Gug-Rae Jo , Byoung-Joo Kim , Ji-Won Choi , Jang-Soo Kim , Shi-Yul Kim , Jin-Ho Ju , Chong-Chul Chai
IPC分类号： G02F1/1343 , G02F1/1335
CPC分类号： G02F1/1362 , G02F1/136227 , G02F2001/136222
摘要： A display substrate includes a thin film transistor layer, a color filter layer, a plurality of pixel electrodes, a first cover layer and an alignment layer. The thin film transistor layer includes a plurality of pixel regions. The color filter layer is formed on the thin film transistor layer. The pixel electrodes are formed on the color filter layer with at least one gap defined between adjacent pixel electrodes. The first cover layer is provided in the gap between adjacent pixel electrodes and covers a portion of the color filter layer exposed by the gap between the pixel electrodes. The alignment layer is formed on the pixel electrodes and the first cover layer. Therefore, the color filter layer is spaced apart from the alignment layer to decrease an afterimage, thereby improving an image display quality
摘要翻译：显示基板包括薄膜晶体管层，滤色器层，多个像素电极，第一覆盖层和取向层。薄膜晶体管层包括多个像素区域。滤色器层形成在薄膜晶体管层上。像素电极形成在滤色器层上，在相邻像素电极之间限定有至少一个间隙。第一覆盖层设置在相邻像素电极之间的间隙中，并且覆盖由像素电极之间的间隙暴露的滤色器层的一部分。取向层形成在像素电极和第一覆盖层上。因此，滤色器层与对准层间隔开以减少残像，从而提高图像显示质量

25. 发明申请

US20070031763A1 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20070031763A1
公开(公告)日：2007-02-08
申请号：US11430414
申请日：2006-05-09
申请人： Jeong-Min Park , Jang-Soo Kim , Hi-Kuk Lee
发明人： Jeong-Min Park , Jang-Soo Kim , Hi-Kuk Lee
IPC分类号： G03F7/26
CPC分类号： H01L27/1288 , G03F7/40 , H01L21/0273 , H01L27/1214 , H01L29/66765
摘要： A method of fabricating a semiconductor device is provided. The method includes forming at least one etch target film on a substrate, forming a first reflowable etch mask on the at least one etch target film, patterning the etch target film using the first reflowable etch mask. The method further includes reflowing the first reflowable etch mask to form a second etch mask and patterning the etch target film using the second etch mask.
摘要翻译：提供一种制造半导体器件的方法。该方法包括在衬底上形成至少一个蚀刻目标膜，在至少一个蚀刻靶膜上形成第一可回流蚀刻掩模，使用第一可回流蚀刻掩模对蚀刻目标膜进行构图。该方法还包括回流第一可回流蚀刻掩模以形成第二蚀刻掩模，并使用第二蚀刻掩模对蚀刻目标膜进行图案化。

26. 发明申请

US20060054889A1 Thin film transistor array panel 审中-公开
标题翻译：薄膜晶体管阵列面板
公开(公告)号：US20060054889A1
公开(公告)日：2006-03-16
申请号：US10942039
申请日：2004-09-16
申请人： Jang-Soo Kim , Hyang-Shik Kong , Hye-Young Ryu , Sung-Man Kim
发明人： Jang-Soo Kim , Hyang-Shik Kong , Hye-Young Ryu , Sung-Man Kim
IPC分类号： H01L29/04
CPC分类号： H01L27/124 , G02F1/136213 , G02F1/136259 , G02F2001/13629 , H01L27/1255 , H01L27/1288
摘要： A thin film transistor array panel comprising: an insulating substrate; a plurality of gate lines formed on the insulating substrate and including a plurality of gate electrodes and end portions; a plurality of storage electrode lines formed on the insulating substrate; a gate insulating layer formed on the gate lines and storage electrode lines; a semiconductor layer formed on the gate insulating layer; a ohmic contact layer formed on the semiconductor layer; a plurality of data lines formed on the gate insulating layer, intersecting the gate lines to define a display area, and having source electrodes and end portions; a plurality of drain electrodes facing the source electrodes; a passivation layer formed on the data lines and drain electrodes and having contact holes; a plurality of pixel electrodes formed on the passivation layer and connected to the drain electrodes through the contact holes; a storage line connecting bar connecting the storage electrode lines; and a redundant connecting line connecting the storage electrode lines is provided.
摘要翻译： 1.一种薄膜晶体管阵列面板，包括：绝缘基板; 多个栅极线，形成在所述绝缘基板上并且包括多个栅电极和端部; 形成在所述绝缘基板上的多个存储电极线; 形成在栅极线和存储电极线上的栅极绝缘层; 形成在所述栅极绝缘层上的半导体层; 形成在所述半导体层上的欧姆接触层; 形成在所述栅极绝缘层上的多条数据线，与所述栅极线交叉以限定显示区域，并具有源电极和端部; 面对所述源电极的多个漏电极; 形成在数据线和漏电极上并具有接触孔的钝化层; 多个像素电极，形成在钝化层上并通过接触孔连接到漏电极; 连接存储电极线的存储线连接条; 并且提供连接存储电极线的冗余连接线。

27. 发明授权

US06445004B1 Composition for a wiring, a wiring using the composition, manufacturing method thereof, a display using the wiring and a manufacturing method thereof 有权
标题翻译：配线用组合物，使用该组合物的布线及其制造方法，使用布线的显示器及其制造方法
公开(公告)号：US06445004B1
公开(公告)日：2002-09-03
申请号：US09617311
申请日：2000-07-14
申请人： Chang-Oh Jeong , Yang-Sun Kim , Myung-Koo Hur , Young-Jae Tak , Mun-Pyo Hong , Chi-Woo Kim , Jang-Soo Kim , Chun-Gi You
发明人： Chang-Oh Jeong , Yang-Sun Kim , Myung-Koo Hur , Young-Jae Tak , Mun-Pyo Hong , Chi-Woo Kim , Jang-Soo Kim , Chun-Gi You
IPC分类号： H01L2904
CPC分类号： G02F1/136286 , G02F1/136227 , G02F1/1368 , G02F2001/13629 , H01L21/28008 , H01L23/4827 , H01L29/42384 , H01L29/4908 , H01L2924/0002 , H01L2924/00
摘要： The Mo or MoW composition layer has a low resistivity of less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with an Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl(+He) or SF6+Cl2(+He) can form the edge profile of contact holes to be smoothed. Also, when an amorphous silicon layer formed under the Mo or MoW layer is etched using the Mo or MoW layer as a mask, using an etch gas system that employs a gas such as hydrogen halide and at least one gas selected from CF4, CHF3, CHClF2, CH3F, and C2F6, yields good TFT characteristics, and H2 plasma treatment can further improve the TFT characteristics.
摘要翻译： Mo或MoW组合物层具有小于15μOMEGAcm的低电阻率，并且使用Al合金附魔或Cr附魔被蚀刻成具有平滑的锥角，并且Mo或MoW层用于显示器或半导体显示器以及Al层或Cr层。由于通过调节沉积压力可以沉积Mo或MoW层以便对基底施加低应力，所以可以单独使用单个MoW层作为布线。当在钝化层或栅极绝缘层中形成接触孔时，通过使用聚合物层减少横向蚀刻，使用CF 4 + O 2的蚀刻气体系统可以防止Mo或MoW合金层的蚀刻，以及蚀刻气体 SF6 + HCl（+ He）或SF6 + Cl2（+ He）可以形成要平滑的接触孔的边缘轮廓。此外，当使用Mo或MoW层作为掩模蚀刻形成在Mo或MoW层下面的非晶硅层时，使用采用诸如卤化氢和至少一种选自CF 4，CHF 3的气体的气体的蚀刻气体系统， CHClF 2，CH 3 F和C 2 F 6，产生良好的TFT特性，并且H 2等离子体处理可以进一步提高TFT特性。

28. 发明授权

US06441401B1 Thin film transistor array panel for liquid crystal display and method for repairing the same 有权
标题翻译：用于液晶显示器的薄膜晶体管阵列面板及其修复方法
公开(公告)号：US06441401B1
公开(公告)日：2002-08-27
申请号：US09527803
申请日：2000-03-17
申请人： Cheol-Soo Jung , Young-Sun Kim , Ho-Joon Lee , Yeong-Hwan Cho , Hyeon-Hwan Kim , Bung-Hyuk Min , Woon-Yong Park , Il-Gon Kim , Jang-Soo Kim , Jin-Oh Kwag , Seog-Chae Lee
发明人： Cheol-Soo Jung , Young-Sun Kim , Ho-Joon Lee , Yeong-Hwan Cho , Hyeon-Hwan Kim , Bung-Hyuk Min , Woon-Yong Park , Il-Gon Kim , Jang-Soo Kim , Jin-Oh Kwag , Seog-Chae Lee
IPC分类号： H01L2900
CPC分类号： G02F1/136259 , G02F2001/136263 , G02F2001/136272 , H01L27/12
摘要： A gate line extending in a horizontal direction is formed on an insulating substrate, and a data line is formed perpendicular to the gate line defining a pixel of a matrix array. Pixel electrodes receiving image signals through the data line are formed in a pixel, and a thin film transistor having a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode is formed on the portion where the gate lines and the data lines intersect. A storage wire including a storage electrode line in the horizontal direction, a storage electrode connected to the storage electrode line, and at least one of the storage electrode connection portions connecting storage electrodes of neighboring pixels is formed in the same direction as the gate line. A redundant repair line overlaps and is insulated from the storage wire at one end and overlaps the storage wire or the gate wire of a neighboring pixel at the other end is formed in the same layer as the data wire. Also, a storage wire connection portion connecting the storage wires of a neighboring pixel is formed in the same layer as the pixel electrode. In this structure, if portions of the gate wire or the data wire are disconnected, the portions overlapping the disconnected wire, the storage wire, and the redundant repair line are shorted to repair an open wire defect.
摘要翻译：在绝缘基板上形成沿水平方向延伸的栅极线，并且垂直于限定矩阵阵列的像素的栅极线形成数据线。通过数据线接收图像信号的像素电极形成在像素中，并且形成具有连接到栅极线的栅电极，连接到数据线的源电极和连接到像素电极的漏电极的薄膜晶体管在栅极线和数据线相交的部分。包括在水平方向上存储电极线的存储线，连接到存储电极线的存储电极以及连接相邻像素的存储电极的至少一个存储电极连接部分沿与栅极线相同的方向形成。冗余维修线在一端重叠并与存储线绝缘，并与存储线重叠，另一端的相邻像素的栅极线形成在与数据线相同的层中。此外，连接相邻像素的存储线的存储线连接部分形成在与像素电极相同的层中。在这种结构中，如果栅极线或数据线的部分断开，与断开的线，存储线和冗余修复线重叠的部分短路以修复开路的线缺陷。

29. 发明授权

US08642367B2 Thin film transistor having improved manufacturability and method for manufacturing a display panel containing same 失效
标题翻译：具有改进的可制造性的薄膜晶体管和用于制造包含它的显示面板的方法
公开(公告)号：US08642367B2
公开(公告)日：2014-02-04
申请号：US13042348
申请日：2011-03-07
申请人： Yu-Gwang Jeong , Young-Wook Lee , Sang-Gab Kim , Woo-Geun Lee , Min-Seok Oh , Jang-Soo Kim , Kap-Soo Yoon , Shin-Il Choi , Hong-Kee Chin , Seung-Ha Choi , Seung-Hwan Shim , Sung-Hoon Yang , Ki-Hun Jeong
发明人： Yu-Gwang Jeong , Young-Wook Lee , Sang-Gab Kim , Woo-Geun Lee , Min-Seok Oh , Jang-Soo Kim , Kap-Soo Yoon , Shin-Il Choi , Hong-Kee Chin , Seung-Ha Choi , Seung-Hwan Shim , Sung-Hoon Yang , Ki-Hun Jeong
IPC分类号： H01L21/02
CPC分类号： H01L27/127 , H01L27/1214 , H01L27/1259 , H01L27/1288 , H01L29/66765
摘要： Embodiments of the present invention relate to a thin film transistor and a manufacturing method of a display panel, and include forming a gate line including a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming an intrinsic semiconductor on the gate insulating layer, forming an extrinsic semiconductor on the intrinsic semiconductor, forming a data line including a source electrode and a drain electrode on the extrinsic semiconductor, and plasma-treating a portion of the extrinsic semiconductor between the source electrode and the drain electrode to form a protection member and ohmic contacts on respective sides of the protection member. Accordingly, the process for etching the extrinsic semiconductor and forming an inorganic insulating layer for protecting the intrinsic semiconductor may be omitted such that the manufacturing process of the display panel may be simplified, manufacturing cost may be reduced, and productivity may be improved.
摘要翻译：本发明的实施例涉及薄膜晶体管和显示面板的制造方法，包括在基板上形成包括栅电极的栅极线，在栅电极上形成栅绝缘层，在栅电极上形成本征半导体栅极绝缘层，在本征半导体上形成非本征半导体，在外部半导体上形成包括源电极和漏电极的数据线，以及对源电极和漏极之间的非本征半导体的一部分进行等离子体处理，以形成保护构件和保护构件的相应侧上的欧姆接触。因此，可以省略用于蚀刻外部半导体和形成用于保护本征半导体的无机绝缘层的工艺，从而可以简化显示面板的制造工艺，可以降低制造成本，并且可以提高生产率。

30. 发明申请

US20130320347A1 THIN FILM TRANSISTOR ARRAY PANEL AND A METHOD FOR MANUFACTURING THE SAME 有权
公开(公告)号：US20130320347A1
公开(公告)日：2013-12-05
申请号：US13951543
申请日：2013-07-26
申请人： Young-Wook Lee , Jang-Soo Kim
发明人： Young-Wook Lee , Jang-Soo Kim
IPC分类号： H01L27/12
CPC分类号： H01L27/124 , G02F1/136209 , G02F1/136286 , G02F1/1365 , G02F1/1368 , G02F2001/134372 , G02F2001/136222 , G02F2001/13629 , H01L27/1248
摘要： A thin film transistor array panel includes a substrate; a plurality of gate lines that are formed on the substrate; a plurality of data lines that intersect the gate lines; a plurality of thin film transistors that are connected to the gate lines and the data lines; a plurality of color filters that are formed on upper parts of the gate lines, the data lines, and the thin film transistors; a common electrode that is formed on the color filters and that includes a transparent conductor; a passivation layer that is formed on an upper part of the common electrode; and a plurality of pixel electrodes that are formed on an upper part of the passivation layer and that are connected to a drain electrode of each of the thin film transistors.

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