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    • 22. 发明授权
    • Voice recognition control system and voice recognition control method
    • 语音识别控制系统和语音识别控制方法
    • US07801730B1
    • 2010-09-21
    • US09626309
    • 2000-07-26
    • Yoshio MiyazakiTamiya TanakaShizue MurayamaKazuhisa SeitaKenji Kaneko
    • Yoshio MiyazakiTamiya TanakaShizue MurayamaKazuhisa SeitaKenji Kaneko
    • G10L21/00
    • H04L12/40117G10L15/26
    • A voice recognition control system capable of realizing control of entire voice-recognizable electronic devices through voice recognition. This control system includes a voice input unit for inputting an operator's voice, a voice recognition unit and a controller constituting a control means which recognizes the operator's voice obtained from the voice input unit and controls input/output of an MD player having a voice recognition table where the operator's voice is stored in advance as an expected value. When an unregistered MD player has been connected first, the voice recognition unit registers the voice recognition table provided from the MD player. And upon input of the operator's voice by the voice input unit, the control means compares the operator's voice with the preregistered voice recognition table, and then the controller controls the input/output of the MD player in accordance with the result of comparing the operator's voice with the voice recognition table.
    • 一种语音识别控制系统,能够通过语音识别来实现对整个语音识别电子设备的控制。 该控制系统包括用于输入操作人员语音的语音输入单元,语音识别单元和构成控制单元的控制器,该控制单元识别从语音输入单元获得的操作员的语音,并控制具有语音识别表的MD播放器的输入/输出 其中操作者的声音被预先存储为期望值。 当首先连接未注册的MD播放器时,语音识别单元注册从MD播放器提供的语音识别表。 并且在由语音输入单元输入操作者的声音时,控制装置将操作人员的语音与预先注册的语音识别表进行比较,然后控制器根据操作者语音的比较结果来控制MD播放器的输入/输出 与语音识别表。
    • 27. 发明授权
    • Survey point indicating instrument
    • 测点指示仪
    • US06796042B1
    • 2004-09-28
    • US10641038
    • 2003-08-15
    • Kenji Kaneko
    • Kenji Kaneko
    • G01C500
    • G01C15/00G01J5/08
    • A survey point indicating instrument, for recognizing a line of sight visually, includes a collimating lens, two light sources being positioned so that optical axes of the two light sources intersect each other on an optical axis of the collimating lens at a focal point of the collimating lens; a driving circuit for controlling light emissions of the two light sources independently from each other; and a light shield plate having a slit, and positioned between the focal point and the two light sources so that light rays emitted from each of the two light sources to travel in an area between the optical axes are allowed to pass through the slit while other light rays emitted from each of the two light sources are cut off by the light shield plate to prevent the other light rays from traveling outside the area between the optical axes.
    • 用于在视觉上识别视线的测点指示仪器包括准直透镜,两个光源被定位成使得两个光源的光轴在准直透镜的光轴处彼此相交, 准直透镜 用于彼此独立地控制两个光源的光发射的驱动电路; 以及遮光板,其具有狭缝,并且位于焦点和两个光源之间,使得从两个光源中的每一个射出的光线在光轴之间的区域中行进,允许穿过狭缝,而其他 通过遮光板切断从两个光源中的每一个射出的光线,以防止其他光线在光轴之间的区域外行进。
    • 30. 发明授权
    • Multi-port memory and a data processor accessing the same
    • 多端口存储器和访问它的数据处理器
    • US06282505B1
    • 2001-08-28
    • US09125285
    • 1998-08-14
    • Makoto HanawaKenji KanekoKazumichi YamamotoKentaro Shimada
    • Makoto HanawaKenji KanekoKazumichi YamamotoKentaro Shimada
    • G11C800
    • G06F12/0846
    • In a cache memory of a super-scalar or VLIW processor to concurrently process a plurality of memory accesses, to provide a memory capable of multi-port access operation, there is provided a unit which subdivides the cache memory into a plurality of memory banks for concurrent operations thereof and which allocates memory ports independently to the respective memory banks. In a first cycle, the first and second memory ports are allocated to the first and second memory banks, respectively. If a hit occurs, the plural accesses are completed in one cycle. If a miss results, the first and second memory ports are allocated respectively to the second and first memory banks in a second cycle.
    • 在超标量或VLIW处理器的高速缓冲存储器中,以并行处理多个存储器访问,为了提供能够进行多端口访问操作的存储器,提供了一种将高速缓冲存储器细分成多个存储体的单元,用于 并行操作,并且独立地分配存储器端口到相应的存储体。 在第一周期中,分别将第一和第二存储器端口分配给第一和第二存储体。 如果发生命中,则多个访问在一个周期内完成。 如果错过结果,则第一和第二存储器端口在第二周期中分别分配给第二和第一存储体。