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21. 发明申请

US20050230714A1 Semiconductor memory device and manufacturing method thereof 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20050230714A1
公开(公告)日：2005-10-20
申请号：US11066567
申请日：2005-02-28
申请人： Hideki Komori , Hisayuki Shimada , Yu Sun , Hiroyuki Kinoshita
发明人： Hideki Komori , Hisayuki Shimada , Yu Sun , Hiroyuki Kinoshita
IPC分类号： H01L21/8234 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/336 , H01L29/80 , H01L31/112
CPC分类号： H01L27/11521 , H01L21/823425 , H01L21/823468 , H01L27/115 , H01L27/11568 , Y10S257/90
摘要： A drain (7) comprises a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped impurity region (7b) to reduce the contact resistance at the drain (7).
摘要翻译：漏极（7）包括与控制栅极（5）对准的轻掺杂浅杂质区域（7a）和与侧壁膜（8）对准并掺杂杂质的重掺杂深杂质区域（7b）其浓度高于轻掺杂浅杂质区（7a）的浓度。轻掺杂的浅杂质区域（7a）导致短沟道效应和编程效率的改善。漏极接触孔形成部分（70）设置到重掺杂杂质区域（7b）以降低漏极（7）处的接触电阻。

22. 发明授权

US06583009B1 Innovative narrow gate formation for floating gate flash technology 有权
标题翻译：用于浮栅闪存技术的创新窄门形成
公开(公告)号：US06583009B1
公开(公告)日：2003-06-24
申请号：US10178106
申请日：2002-06-24
申请人： Angela T. Hui , Kelwin Ko , Hiroyuki Kinoshita , Sameer Haddad , Yu Sun
发明人： Angela T. Hui , Kelwin Ko , Hiroyuki Kinoshita , Sameer Haddad , Yu Sun
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115 , Y10S438/952
摘要： The present invention relates to a method of forming a stacked gate flash memory cell and comprises forming a tunnel oxide layer, a first conductive layer, an interpoly dielectric layer, and a second conductive layer in succession over a semiconductor substrate. The method further comprises forming a sacrificial layer over the second conductive layer, and patterning the sacrificial layer to form a sacrificial layer feature having at least one lateral sidewall edge associated therewith. A sidewall spacer is then formed against the lateral sidewall edge of the sacrificial layer, wherein the spacer has a width associated therewith, and the patterned sacrificial layer feature is removed. Finally, the second conductive layer, the interpoly dielectric and the first conductive layer are patterned using the spacer as a hard mask, and defining the stacked gate, wherein a width of the stacked gate is a function of the spacer width.
摘要翻译：本发明涉及一种形成层叠栅极闪存单元的方法，包括在半导体衬底上连续形成隧道氧化物层，第一导电层，多晶硅间介质层和第二导电层。该方法还包括在第二导电层上形成牺牲层，以及图案化牺牲层以形成具有与其相关联的至少一个侧向侧壁边缘的牺牲层特征。然后在牺牲层的横向侧壁边缘上形成侧壁间隔物，其中间隔件具有与其相关联的宽度，并且去除图案化的牺牲层特征。最后，使用间隔物作为硬掩模来图案化第二导电层，多晶硅间电介质和第一导电层，并且限定堆叠栅极，其中堆叠栅极的宽度是间隔物宽度的函数。

23. 发明授权

US06359307B1 Method for forming self-aligned contacts and interconnection lines using dual damascene techniques 有权
标题翻译：使用双镶嵌技术形成自对准触点和互连线的方法
公开(公告)号：US06359307B1
公开(公告)日：2002-03-19
申请号：US09493436
申请日：2000-01-29
申请人： Fei Wang , Hiroyuki Kinoshita , Kashmir Sahota , Yu Sun , Wenge Yang
发明人： Fei Wang , Hiroyuki Kinoshita , Kashmir Sahota , Yu Sun , Wenge Yang
IPC分类号： H01L2976
CPC分类号： H01L21/76897 , H01L23/485 , H01L27/115 , H01L27/11521 , H01L2924/0002 , H01L2924/3011 , Y02P80/30 , H01L2924/00
摘要： The present invention further provides a method for forming self-aligned contacts using a dual damascene techniques that reduces the number of process steps and results in a reduction in cycle time, cost and yield loss. In a preferred embodiment, a method for forming a contact and a channel in a dielectric layer over a region on a semiconductor substrate is provided. The contact is self-aligned. The contact and channel are formed by (1) forming a contact opening in the dielectric layer, (2) forming a channel opening in the dielectric layer, wherein the channel opening encompasses the contact opening, (3) extending the contact opening to expose a portion of the region on the semiconductor substrate; and (4) filling the contact opening and the channel opening with a conductive material to form a contact and a channel, respectively.
摘要翻译：本发明还提供了一种使用双镶嵌技术形成自对准接触的方法，其减少了工艺步骤的数量并导致了循环时间，成本和屈服损失的降低。在优选实施例中，提供了在半导体衬底上的区域上形成电介质层中的接触和沟道的方法。联系人自行对齐。接触和通道由（1）在电介质层中形成接触开口形成，（2）在电介质层中形成通道开口，其中通道开口包围接触开口，（3）延伸接触开口以露出所述半导体衬底上的所述区域的部分; 和（4）分别用导电材料填充接触开口和通道开口以形成接触和通道。

24. 发明授权

US06271087B1 Method for forming self-aligned contacts and local interconnects using self-aligned local interconnects 有权
标题翻译：使用自对准局部互连形成自对准触点和局部互连的方法
公开(公告)号：US06271087B1
公开(公告)日：2001-08-07
申请号：US09685968
申请日：2000-10-10
申请人： Hiroyuki Kinoshita , YongZhong Hu , Yu Sun , Fei Wang
发明人： Hiroyuki Kinoshita , YongZhong Hu , Yu Sun , Fei Wang
IPC分类号： H01L21336
CPC分类号： H01L21/76897 , H01L21/31144 , H01L21/76895 , H01L2924/3011
摘要： A method of manufacturing a semiconductor device is provided in which multi-layer structures are formed on a semiconductor substrate to form core and peripheral regions. Sidewall spacers are formed around the multi-layer structures and source and drain regions are implanted adjacent the sidewall spacers and a stop layer is deposited over the semiconductor substrate after which a dielectric layer is deposited over the stop layer. A first photoresist contact mask is deposited, processed, and used to etch core contact and peripheral local interconnect openings. The first photoresist contact mask is removed. A second photoresist contact mask is deposited, processed, and used to etch the multi-layer structures to form local interconnect openings. The second photoresist contact mask is removed. A conductive material is deposited over the dielectric layer and in the core and peripheral contact openings and is chemical mechanical planarized to remove the conductive material over the dielectric layer so the conductive material is left isolated in the core contact and peripheral local interconnect openings with core contacts to the source/drain regions and peripheral local interconnect contacts to the multi-layer structures and the source/drain regions.
摘要翻译：提供一种制造半导体器件的方法，其中在半导体衬底上形成多层结构以形成芯和周边区域。在多层结构周围形成侧壁间隔物，并且将源极和漏极区域相邻于侧壁间隔物注入，并且在半导体衬底上沉积停止层，之后在停止层上沉积电介质层。第一光致抗蚀剂接触掩模被沉积，处理并用于蚀刻芯接触和外围局部互连开口。去除第一光致抗蚀剂接触掩模。沉积，处理和用于蚀刻多层结构以形成局部互连开口的第二光致抗蚀剂接触掩模。去除第二光致抗蚀剂接触掩模。导电材料沉积在电介质层上，并在芯和外围接触开口中沉积，并进行化学机械平面化以去除电介质层上的导电材料，因此导电材料在芯接触区和外围局部互连开口处与芯触点隔离到源极/漏极区域和外围局部互连触点到多层结构和源极/漏极区域。

25. 发明授权

US07078314B1 Memory device having improved periphery and core isolation 失效
标题翻译：具有改进的外围和核心隔离的存储器件
公开(公告)号：US07078314B1
公开(公告)日：2006-07-18
申请号：US10407999
申请日：2003-04-03
申请人： Unsoon Kim , Hiroyuki Kinoshita , Yu Sun
发明人： Unsoon Kim , Hiroyuki Kinoshita , Yu Sun
IPC分类号： H01L21/76
CPC分类号： H01L21/76229 , H01L27/105 , H01L27/1052
摘要： The present invention discloses a memory device having an improved periphery isolation region and core isolation region. A first trench is formed in a core region. Substrate material bordering the first trench is then oxidized to form a first liner. The first liner is then removed. A second trench is then formed in a periphery region. A second oxidation is then performed such that a second liner is formed from the substrate material bordering the first and second trenches. A dielectric trench fill having substantially uniform density is then deposited in the first and second trenches.
摘要翻译：本发明公开了一种具有改进的外围隔离区域和核心隔离区域的存储器件。第一沟槽形成在芯区域中。然后与第一沟槽接壤的衬底材料被氧化以形成第一衬里。然后将第一个衬垫取出。然后在周边区域中形成第二沟槽。然后执行第二氧化，使得第二衬垫由与第一和第二沟槽接壤的衬底材料形成。然后在第一和第二沟槽中沉积具有基本均匀密度的电介质沟槽填料。

26. 发明授权

US07632749B1 Semiconductor device having a pad metal layer and a lower metal layer that are electrically coupled, whereas apertures are formed in the lower metal layer below a center area of the pad metal layer 有权
标题翻译：具有电耦合的焊盘金属层和下金属层的半导体器件，而在焊盘金属层的中心区域下方的下金属层中形成孔
公开(公告)号：US07632749B1
公开(公告)日：2009-12-15
申请号：US10823970
申请日：2004-04-13
申请人： Hiroyuki Ogawa , Yider Wu , Nian Yang , Kuo-Tung Chang , Yu Sun
发明人： Hiroyuki Ogawa , Yider Wu , Nian Yang , Kuo-Tung Chang , Yu Sun
IPC分类号： H01L21/44
CPC分类号： H01L21/76816 , H01L24/05 , H01L2224/02166 , H01L2224/05093 , H01L2224/05095 , H01L2224/05096 , H01L2224/05554 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/14
摘要： A semiconductor device is disclosed and provided. The semiconductor device includes a pad metal layer having a perimeter area and a center area. Further, the semiconductor device has a lower metal layer having a plurality of apertures below the center area of the pad metal layer. Moreover, an interlayer dielectric is formed between the pad metal layer and the lower metal layer. In an embodiment, the semiconductor device also includes a plurality of vias formed in the interlayer dielectric. The vias electrically couple the pad metal layer and the lower metal layer. Additionally, the vias are located below the perimeter area of the pad metal layer.
摘要翻译：公开并提供了半导体器件。半导体器件包括具有周边区域和中心区域的焊盘金属层。此外，半导体器件具有在焊盘金属层的中心区域下方具有多个孔的下部金属层。此外，在焊盘金属层和下金属层之间形成层间电介质。在一个实施例中，半导体器件还包括形成在层间电介质中的多个通孔。通孔电连接焊盘金属层和下部金属层。另外，通孔位于垫金属层的周边区域的下方。

27. 发明授权

US07019366B1 Electrostatic discharge performance of a silicon structure and efficient use of area with electrostatic discharge protective device under the pad approach and adjustment of via configuration thereto to control drain junction resistance 有权
标题翻译：硅结构的静电放电性能，有效利用垫下方的静电放电保护装置的面积，调整通孔配置，以控制漏极结电阻
公开(公告)号：US07019366B1
公开(公告)日：2006-03-28
申请号：US10758173
申请日：2004-01-14
申请人： Nian Yang , Hiroyuki Ogawa , Yider Wu , Kuo-Tung Chang , Yu Sun
发明人： Nian Yang , Hiroyuki Ogawa , Yider Wu , Kuo-Tung Chang , Yu Sun
IPC分类号： H01L23/62
CPC分类号： H01L27/0251
摘要： More efficient use of silicon area is achieved by incorporating an electrostatic discharge protective (ESDP) device beneath a pad area of a semiconductor structure. The pad area includes a substrate having a first metal layer above it. A second metal layer is above the first metal layer. The ESDP device resides in the substrate below the first metal layer. A layer of dielectric separates the first and second metal layers. A via within the dielectric layer electrically couples the first and second metal layers. A via connects to the ESDP component. Subsequent metal layers can be arranged between the first and second metal layers. The Ohmic value of the resistance component of the ESDP device can be set during fabrication by fixing a number of individual via components, arranged electrically in parallel, by fixing the cross sectional area of the via components, and/or by fixing the length of the via components.
摘要翻译：通过在半导体结构的焊盘区域的下方并入静电放电保护（ESDP）器件来实现硅面积的更有效的使用。焊盘区域包括在其上方具有第一金属层的基板。第二金属层位于第一金属层之上。 ESDP设备位于第一金属层下方的基板中。电介质层分离第一和第二金属层。电介质层内的通孔电耦合第一和第二金属层。 A通道连接到ESDP组件。随后的金属层可以布置在第一和第二金属层之间。 ESDP装置的电阻部件的欧姆值可以在制造期间通过固定多个单独的通孔部件，通过固定通孔部件的横截面面积和/或固定长度通过组件。

28. 发明授权

US07151027B1 Method and device for reducing interface area of a memory device 有权
标题翻译：用于减少存储器件的接口面积的方法和装置
公开(公告)号：US07151027B1
公开(公告)日：2006-12-19
申请号：US10859369
申请日：2004-06-01
申请人： Hiroyuki Ogawa , Yider Wu , Kuo-Tung Chang , Yu Sun
发明人： Hiroyuki Ogawa , Yider Wu , Kuo-Tung Chang , Yu Sun
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11536 , H01L27/11548
摘要： A method and device for reducing interface area of a memory device. A poly-2 layer is formed above a substrate at an interface between a memory array and a periphery of the memory device. The poly-2 layer is etched proximate to the memory array. The poly-2 layer is etched proximate to the periphery such that a portion of the poly-2 layer remains at the interface.
摘要翻译：一种用于减少存储器件的接口面积的方法和装置。在存储器阵列和存储器件的外围之间的界面处，在衬底上形成多晶硅层2。聚二层蚀刻到存储器阵列附近。聚二层被蚀刻到外围附近，使得多2层的一部分保留在界面处。

29. 发明申请

US20050151265A1 Efficient use of wafer area with device under the pad approach 审中-公开
标题翻译：利用垫片方式下的设备有效利用晶圆区域
公开(公告)号：US20050151265A1
公开(公告)日：2005-07-14
申请号：US10758148
申请日：2004-01-14
申请人： Nian Yang , Hiroyuki Ogawa , Yider Wu , Kuo-Tung Chang , Yu Sun , Darlene Hamilton
发明人： Nian Yang , Hiroyuki Ogawa , Yider Wu , Kuo-Tung Chang , Yu Sun , Darlene Hamilton
IPC分类号： G06F17/50 , H01L23/485 , H01L27/02 , H01L23/48 , H01L21/44
CPC分类号： H01L27/0203 , H01L24/05 , H01L24/06 , H01L2224/02166 , H01L2224/05093 , H01L2224/05096 , H01L2224/05556 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05684 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/14 , H01L2924/19043 , H01L2924/00014
摘要： More efficient use of silicon area is achieved by incorporating an active device beneath a pad area of a semiconductor structure. The pad area includes a substrate having a first metal layer above it. A second metal layer is below the first metal layer. The active device resides in the substrate below the second metal layer. A layer of dielectric separates the first and second metal layers. A via within the dielectric layer electrically couples the first and second metal layers. A via connects to the active component. Subsequent metal layers can be arranged between the first and second metal layers.
摘要翻译：通过在半导体结构的焊盘区域的下方并入有源器件来实现硅面积的更有效的使用。焊盘区域包括在其上方具有第一金属层的基板。第二金属层位于第一金属层的下方。有源器件位于第二金属层下方的衬底中。电介质层分离第一和第二金属层。电介质层内的通孔电耦合第一和第二金属层。 A通道连接到活动组件。随后的金属层可以布置在第一和第二金属层之间。

30. 发明授权

US06936515B1 Method for fabricating a memory device having reverse LDD 有权
标题翻译：用于制造具有反向LDD的存储器件的方法
公开(公告)号：US06936515B1
公开(公告)日：2005-08-30
申请号：US10387774
申请日：2003-03-12
申请人： Hiroyuki Ogawa , Yu Sun , Angela Hui
发明人： Hiroyuki Ogawa , Yu Sun , Angela Hui
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/105
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11534 , H01L29/6656 , H01L29/6659 , H01L29/66825
摘要： A method for fabricating a semiconductor device. Specifically, a method that includes forming a source and drain region in a periphery transistor, exhibiting a channel width between the source and drain regions suitable for operation at predetermined voltages. After forming the source and drain regions, to eliminate diffusion of lightly doped drain regions resulting from a later formation of the source and drain regions, forming the lightly doped drain regions adjacent to the source and drain regions of the periphery transistor. After forming the lightly doped drain regions in the periphery transistor, the method includes forming a source region and a drain region in a core memory cell, independent of forming the source and drain regions in the periphery transistor.
摘要翻译：一种半导体器件的制造方法。具体地，涉及在周边晶体管中形成源区和漏区的方法，其表现出适于在预定电压下操作的源区和漏区之间的沟道宽度。在形成源极区和漏极区之后，为了消除稍后形成源极和漏极区所产生的轻掺杂漏极区的扩散，形成与周边晶体管的源极和漏极区相邻的轻掺杂漏极区。在周边晶体管中形成轻掺杂的漏极区之后，该方法包括在核心存储单元中形成源极区和漏极区，与形成周边晶体管中的源极和漏极区无关。

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