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21. 发明授权

US07709926B2 Device structures for active devices fabricated using a semiconductor-on-insulator substrate and design structures for a radiofrequency integrated circuit 失效
标题翻译：使用绝缘体上半导体衬底制造的有源器件的器件结构和用于射频集成电路的设计结构
公开(公告)号：US07709926B2
公开(公告)日：2010-05-04
申请号：US12108924
申请日：2008-04-24
申请人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier , Jed H. Rankin , Robert R. Robison , William R. Tonti
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier , Jed H. Rankin , Robert R. Robison , William R. Tonti
IPC分类号： H01L29/06
CPC分类号： H01L29/7436 , H01L21/76229 , H01L29/0649 , H01L29/6625 , H01L29/66265 , H01L29/7317 , H01L29/735
摘要： Device structure for active devices fabricated in a semiconductor-on-insulator (SOI) substrate and design structures for a radiofrequency integrated circuit. The device structure includes a first isolation region in the semiconductor layer that extends from a top surface of a semiconductor layer to a first depth, a second isolation region in the semiconductor layer that extends from the top surface of the semiconductor layer to a second depth greater than the first depth, and a first doped region in the semiconductor layer. The first doped region is disposed vertically between the first isolation region and an insulating layer disposed between the semiconductor layer and a handle wafer of the SOI substrate. The device structure may be included in a design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit.
摘要翻译：用于在绝缘体上半导体（SOI）衬底中制造的有源器件的器件结构和用于射频集成电路的设计结构。器件结构包括半导体层中从半导体层的顶表面延伸到第一深度的第一隔离区域，半导体层中的从半导体层的顶表面延伸到第二深度更大的第二隔离区域比第一深度，以及半导体层中的第一掺杂区域。第一掺杂区域垂直地设置在第一隔离区域和设置在SOI衬底的半导体层和处理晶片之间的绝缘层之间。装置结构可以包括在体现在用于设计，制造或测试集成电路的机器可读介质中的设计结构中。

22. 发明申请

US20100038754A1 Back-End-of-Line Resistive Semiconductor Structures 有权
标题翻译：后端电阻半导体结构
公开(公告)号：US20100038754A1
公开(公告)日：2010-02-18
申请号：US12191683
申请日：2008-08-14
申请人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, JR. , Jed H. Rankin , Robert Robison , Yun Shi , William R. Tonti
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, JR. , Jed H. Rankin , Robert Robison , Yun Shi , William R. Tonti
IPC分类号： H01L29/00
CPC分类号： H01L27/115 , H01L23/5256 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, a back-end-of-line (BEOL) resistive structure comprises a second metal line embedded in a second dielectric layer and overlying a first metal line embedded in a first dielectric layer. A doped semiconductor spacer or plug laterally abutting sidewalls of the second metal line and vertically abutting a top surface of the first metal line provides a resistive link between the first and second metal lines. In another embodiment, another BEOL resistive structure comprises a first metal line and a second metal line are embedded in a dielectric layer. A doped semiconductor spacer or plug laterally abutting the sidewalls of the first and second metal lines provides a resistive link between the first and second metal lines.
摘要翻译：在一个实施例中，后端行（BEOL）电阻结构包括嵌入在第二电介质层中的第二金属线，并且覆盖嵌入在第一介电层中的第一金属线。横向邻接第二金属线的侧壁并垂直邻接第一金属线的顶表面的掺杂半导体间隔物或插塞提供第一和第二金属线之间的电阻连接。在另一个实施例中，另一个BEOL电阻结构包括第一金属线，第二金属线嵌入电介质层。横向邻接第一和第二金属线的侧壁的掺杂半导体间隔件或插塞提供第一和第二金属线之间的电阻连接。

23. 发明授权

US07649243B2 Semiconductor structures incorporating multiple crystallographic planes and methods for fabrication thereof 有权
标题翻译：结合多个晶面的半导体结构及其制造方法
公开(公告)号：US07649243B2
公开(公告)日：2010-01-19
申请号：US11556833
申请日：2006-11-06
申请人： Brent A. Anderson , Edward J. Nowak , Jed H. Rankin
发明人： Brent A. Anderson , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L29/04
CPC分类号： H01L29/045 , H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/785
摘要： A semiconductor structure includes a semiconductor mesa located upon an isolating substrate. The semiconductor mesa includes a first end that includes a first doped region separated from a second end that includes a second doped region by an isolating region interposed therebetween. The first doped region and the second doped region are of different polarity. The semiconductor structure also includes a channel stop dielectric layer located upon a horizontal surface of the semiconductor mesa over the second doped region. The semiconductor structure also includes a first device located using a sidewall and a top surface of the first end as a channel region, and a second device located using the sidewall and not the top surface of the second end as a channel. A related method derives from the foregoing semiconductor structure. Also included is a semiconductor circuit that includes the semiconductor structure.
摘要翻译：半导体结构包括位于隔离衬底上的半导体台面。半导体台面包括第一端，该第一端包括通过插入其间的隔离区域与第二掺杂区域分离的第一掺杂区域。第一掺杂区域和第二掺杂区域具有不同的极性。半导体结构还包括位于第二掺杂区域上的半导体台面的水平表面上的沟道阻挡介电层。半导体结构还包括使用第一端的侧壁和顶表面作为沟道区的第一器件，以及使用侧壁而不是第二端的顶表面作为沟道定位的第二器件。相关方法源于上述半导体结构。还包括包括半导体结构的半导体电路。

24. 发明申请

US20090280607A1 METHODS OF FABRICATING A DEVICE STRUCTURE FOR USE AS A MEMORY CELL IN A NON-VOLATILE RANDOM ACCESS MEMORY 失效
标题翻译：在非易失性随机存取存储器中用作存储器单元的器件结构的制作方法
公开(公告)号：US20090280607A1
公开(公告)日：2009-11-12
申请号：US12117950
申请日：2008-05-09
申请人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, JR. , Jed H. Rankin , Yun Shi , William R. Tonti
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, JR. , Jed H. Rankin , Yun Shi , William R. Tonti
IPC分类号： H01L21/8238
CPC分类号： H01L29/7881 , H01L27/1203 , H01L29/66825
摘要： Methods for fabricating a device structure for use as a memory cell in a non-volatile random access memory. The method includes forming first and second semiconductor bodies on the insulating layer that have a separated, juxtaposed relationship, doping the first semiconductor body to form a source and a drain, and partially removing the second semiconductor body to define a floating gate electrode adjacent to the channel of the first semiconductor body. The method further includes forming a first dielectric layer between the channel of the first semiconductor body and the floating gate electrode, forming a second dielectric layer on a top surface of the floating gate electrode, and forming a control gate electrode on the second dielectric layer that cooperates with the floating gate electrode to control carrier flow in the channel in the first semiconductor body.
摘要翻译：制造用作非易失性随机存取存储器中的存储单元的器件结构的方法。该方法包括在绝缘层上形成具有分开且并置的关系的第一和第二半导体本体，掺杂第一半导体本体以形成源极和漏极，以及部分地移除第二半导体本体以限定邻近第一半导体体的通道。该方法还包括在第一半导体本体的沟道与浮栅之间形成第一电介质层，在浮置栅电极的顶表面上形成第二电介质层，在第二电介质层上形成控制栅电极，与浮栅电极配合，以控制第一半导体体的沟道中的载流子流动。

25. 发明申请

US20090278185A1 DEVICE STRUCTURES FOR A MEMORY CELL OF A NON-VOLATILE RANDOM ACCESS MEMORY AND DESIGN STRUCTURES FOR A NON-VOLATILE RANDOM ACCESS MEMORY 失效
标题翻译：非易失性随机访问存储器的存储单元的设备结构和非易失性随机存取存储器的设计结构
公开(公告)号：US20090278185A1
公开(公告)日：2009-11-12
申请号：US12118241
申请日：2008-05-09
申请人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, JR. , Jed H. Rankin , Yun Shi , William R. Tonti
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, JR. , Jed H. Rankin , Yun Shi , William R. Tonti
IPC分类号： H01L29/00 , G06F9/455
CPC分类号： H01L29/7881 , H01L21/28273 , H01L29/42324
摘要： Device and design structures for memory cells in a non-volatile random access memory (NVRAM). The device structure includes a semiconductor body in direct contact with the insulating layer, a control gate electrode, and a floating gate electrode in direct contact with the insulating layer. The semiconductor body includes a source, a drain, and a channel between the source and the drain. The floating gate electrode is juxtaposed with the channel of the semiconductor body and is disposed between the control gate electrode and the insulating layer. A first dielectric layer is disposed between the channel of the semiconductor body and the floating gate electrode. A second dielectric layer is disposed between the control gate electrode and the floating gate electrode.
摘要翻译：非易失性随机存取存储器（NVRAM）中存储单元的器件和设计结构。器件结构包括与绝缘层直接接触的半导体本体，控制栅电极和与绝缘层直接接触的浮栅电极。半导体本体包括源极，漏极以及源极和漏极之间的沟道。浮置栅电极与半导体本体的沟道并置并且设置在控制栅电极和绝缘层之间。第一电介质层设置在半导体本体的沟道和浮栅之间。第二介电层设置在控制栅电极和浮栅电极之间。

26. 发明申请

US20090269903A1 METHODS FOR FABRICATING ACTIVE DEVICES ON A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE UTILIZING MULTIPLE DEPTH SHALLOW TRENCH ISOLATIONS 失效
标题翻译：在使用多个深度深层分离分离的半导体绝缘体基板上制作活性器件的方法
公开(公告)号：US20090269903A1
公开(公告)日：2009-10-29
申请号：US12108851
申请日：2008-04-24
申请人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, JR. , Jed H. Rankin , Robert R. Robison , William R. Tonti
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, JR. , Jed H. Rankin , Robert R. Robison , William R. Tonti
IPC分类号： H01L21/762
CPC分类号： H01L21/7624
摘要： Methods for fabricating a device structure in a semiconductor-on-insulator substrate. The method includes forming a first isolation region in the substrate device layer that extends from a top surface of the device layer to a first depth and forming a second isolation region in the semiconductor layer that extends from the top surface of the semiconductor layer to a second depth greater than the first depth. The method further includes forming a doped region of the device structure in the semiconductor layer that is located vertically between the first isolation region and the insulating layer.
摘要翻译：在绝缘体上半导体衬底中制造器件结构的方法。该方法包括在衬底器件层中形成第一隔离区，该第一隔离区从器件层的顶表面延伸到第一深度，并且在半导体层中形成第二隔离区，该半导体层从半导体层的顶表面延伸到第二隔离区深度大于第一深度。该方法还包括在垂直位于第一隔离区域和绝缘层之间的半导体层中形成器件结构的掺杂区域。

27. 发明申请

US20090134463A1 SEMICONDUCTOR STRUCTURE AND SYSTEM FOR FABRICATING AN INTEGRATED CIRCUIT CHIP 有权
标题翻译：用于制造集成电路芯片的半导体结构和系统
公开(公告)号：US20090134463A1
公开(公告)日：2009-05-28
申请号：US12348344
申请日：2009-01-05
申请人： Wagdi W. Abadeer , Jeffrey S. Brown , David M. Fried , Robert J. Gauthier, JR. , Edward J. Nowak , Jed H. Rankin , William R. Tonti
发明人： Wagdi W. Abadeer , Jeffrey S. Brown , David M. Fried , Robert J. Gauthier, JR. , Edward J. Nowak , Jed H. Rankin , William R. Tonti
IPC分类号： H01L29/78
CPC分类号： H01L29/786 , H01L21/845 , H01L27/1211 , H01L29/4908 , H01L29/78615
摘要： A semiconductor structure and a system for fabricating an integrated circuit chip. The semiconductor structure includes: a buried oxide layer on a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure includes a first hard mask on a semiconductor fin, wherein the semiconductor fin is disposed between the first hard mask and a surface of the buried oxide layer; and a thick mesa structure on the buried oxide layer, and wherein the thick mesa structure includes a semiconductor mesa. The system for fabricating an integrated circuit chip enables: providing a buried oxide layer on and in direct mechanical contact with a semiconductor wafer; and concurrently forming at least one fin-type field effect transistor and at least one thick-body device on the buried oxide layer.
摘要翻译：一种半导体结构和用于制造集成电路芯片的系统。半导体结构包括：半导体晶片上的掩埋氧化物层; 在所述掩埋氧化物层上的薄翅片结构，其中所述薄翅片结构包括半导体鳍片上的第一硬掩模，其中所述半导体鳍片设置在所述第一硬掩模和所述掩埋氧化物层的表面之间; 以及在所述掩埋氧化物层上的厚的台面结构，并且其中所述厚的台面结构包括半导体台面。用于制造集成电路芯片的系统能够：提供与半导体晶片直接机械接触的掩埋氧化物层; 并且在掩埋氧化物层上同时形成至少一个鳍式场效应晶体管和至少一个厚体器件。

28. 发明授权

US07494748B2 Method for correction of defects in lithography masks 失效
标题翻译：光刻掩模中缺陷校正方法
公开(公告)号：US07494748B2
公开(公告)日：2009-02-24
申请号：US10904308
申请日：2004-11-03
申请人： James W. Adkisson , Eric M. Coker , Christopher K. Magg , Jed H. Rankin , Anthony K. Stamper
发明人： James W. Adkisson , Eric M. Coker , Christopher K. Magg , Jed H. Rankin , Anthony K. Stamper
IPC分类号： G03F1/00
CPC分类号： G03F1/72 , G03F1/70
摘要： A method for correction of defects in lithography masks includes determining the existence of mask defects on an original mask, and identifying a stitchable zone around each of the mask defects found on the original mask. Each of the identified stitchable zones on the original mask is blocked out such that circuitry within the stitchable zones is not printed out during exposure of the original mask. A repair mask is formed, the repair mask including corrected circuit patterns from each of the identified stitchable zones.
摘要翻译：用于校正光刻掩模中的缺陷的方法包括确定原始掩模上的掩模缺陷的存在，以及识别在原始掩模上发现的每个掩模缺陷周围的可缝合区域。原始掩模上的每个识别的可缝合区域被阻挡，使得在原始掩模曝光期间不能打印出可缝合区域内的电路。形成修复掩模，修复掩模包括来自每个识别的可缝合区域的校正电路图案。

29. 发明申请

US20080284021A1 Method for FEOL and BEOL Wiring 失效
标题翻译： FEOL和BEOL接线方法
公开(公告)号：US20080284021A1
公开(公告)日：2008-11-20
申请号：US11749898
申请日：2007-05-17
申请人： Brent A. Anderson , John J. Ellis-Monaghan , Edward J. Nowak , Jed H. Rankin
发明人： Brent A. Anderson , John J. Ellis-Monaghan , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L21/44 , H01L23/48
CPC分类号： H01L21/76885 , H01L21/76843 , H01L21/76844 , H01L21/76867 , H01L21/76895 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a conductive structure of sub-lithographic dimension suitable for FEOL and BEOL semiconductor fabrication applications. The method includes forming a topographic feature of silicon-containing material on a substrate; forming a dielectric cap on the topographic feature; applying a mask structure to expose a pattern on a sidewall of the topographic feature, the exposed pattern corresponding to a conductive structure to be formed; depositing a metal at the exposed portions of the sidewall and forming one or more metal silicide conductive structures at the exposed sidewall portions; removing the dielectric cap layer; and removing the silicon-containing topographic feature. The result is the formation of one or more metal silicide conductor structures formed for a single lithographically defined feature. In example embodiments, the formed metal silicide conductive structures have a high aspect ratio, e.g., ranging from 1:1 to 20:1 (height to width dimension).
摘要翻译：一种用于形成适用于FEOL和BEOL半导体制造应用的亚光刻尺寸的导电结构的方法。该方法包括在衬底上形成含硅材料的形貌特征; 在地形特征上形成介电帽; 施加掩模结构以暴露所述地形特征的侧壁上的图案，所述暴露图案对应于要形成的导电结构; 在所述侧壁的暴露部分处沉积金属并在所述暴露的侧壁部分处形成一个或多个金属硅化物导电结构; 去除所述电介质盖层; 并去除含硅的地形特征。结果是形成一个或多个金属硅化物导体结构，其形成用于单个光刻定义的特征。在示例性实施例中，形成的金属硅化物导电结构具有高纵横比，例如从1：1至20：1（高度与宽度尺寸）。

30. 发明申请

US20080121949A1 SEMICONDUCTOR STRUCTURES INCORPORATING MULTIPLE CRYSTALLOGRAPHIC PLANES AND METHODS FOR FABRICATION THEREOF 有权
标题翻译：包含多个水晶平面的半导体结构及其制造方法
公开(公告)号：US20080121949A1
公开(公告)日：2008-05-29
申请号：US11556833
申请日：2006-11-06
申请人： Brent A. Anderson , Edward J. Nowak , Jed H. Rankin
发明人： Brent A. Anderson , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/045 , H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/785
摘要： A semiconductor structure includes a semiconductor mesa located upon an isolating substrate. The semiconductor mesa includes a first end that includes a first doped region separated from a second end that includes a second doped region by an isolating region interposed therebetween. The first doped region and the second doped region are of different polarity. The semiconductor structure also includes a channel stop dielectric layer located upon a horizontal surface of the semiconductor mesa over the second doped region. The semiconductor structure also includes a first device located using a sidewall and a top surface of the first end as a channel region, and a second device located using the sidewall and not the top surface of the second end as a channel. A related method derives from the foregoing semiconductor structure. Also included is a semiconductor circuit that includes the semiconductor structure.
摘要翻译：半导体结构包括位于隔离衬底上的半导体台面。半导体台面包括第一端，该第一端包括从包括第二掺杂区的第二端与第二掺杂区隔开的第一掺杂区。第一掺杂区域和第二掺杂区域具有不同的极性。半导体结构还包括位于第二掺杂区域上的半导体台面的水平表面上的沟道阻挡介电层。半导体结构还包括使用第一端的侧壁和顶表面作为沟道区的第一器件，以及使用侧壁而不是第二端的顶表面作为沟道定位的第二器件。相关方法源于上述半导体结构。还包括包括半导体结构的半导体电路。

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