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21. 发明申请

US20060190744A1 METHOD OF SWITCHING VOLTAGE ISLANDS IN INTEGRATED CIRCUITS 有权
标题翻译：在电路中切换电压岛的方法
公开(公告)号：US20060190744A1
公开(公告)日：2006-08-24
申请号：US10906476
申请日：2005-02-22
申请人： Rafael Blanco , John Cohn , Kenneth Goodnow , Douglas Stout , Sebastian Ventrone
发明人： Rafael Blanco , John Cohn , Kenneth Goodnow , Douglas Stout , Sebastian Ventrone
IPC分类号： G06F1/26
CPC分类号： G06F1/3287 , G06F1/26 , G06F1/3203 , Y02D10/171
摘要： An integrated circuit has a power grid and a set of independently switchable voltage islands, together with a system and method for measuring the voltage and history of the voltage on the power grid to determine the correct time to allow a large capacitive load (such as a voltage island) to be switched on to or off the power grid.
摘要翻译：集成电路具有电网和一组可独立切换的电压岛，以及用于测量电网电压和历史的系统和方法，以确定允许大容性负载（例如，电压岛）被接通或断开电网。

22. 发明申请

US20060189294A1 Wireless communication system within a system on a chip 有权
标题翻译：芯片内系统内的无线通信系统
公开(公告)号：US20060189294A1
公开(公告)日：2006-08-24
申请号：US11410829
申请日：2006-04-24
申请人： Kenneth Goodnow , Riyon Harding , Charles Masenas , Jason Norman , Sebastian Ventrone
发明人： Kenneth Goodnow , Riyon Harding , Charles Masenas , Jason Norman , Sebastian Ventrone
IPC分类号： H04B1/28
CPC分类号： H04B1/38
摘要： A communication system for transmitting data between cores embedded in an integrated circuit on a silicon chip. Communication system includes transmitter circuitry for wirelessly transmitting data between cores and receiver circuitry for wirelessly receiving the transmission of data from other cores. Both transmitter circuitry and receiver circuitry may include of a phase-locked loop circuit having a voltage-controlled oscillator. Each core may transmit and receive data on a unique frequency with respect to other cores embedded in an integrated circuit on a silicon chip or transmit and receive data on the same frequency as other cores embedded in an integrated circuit on a silicon chip. Groups of cores may share transmitter and receiver circuitry.
摘要翻译：一种用于在嵌入在硅芯片上的集成电路中的核之间传输数据的通信系统。通信系统包括用于在核心和接收机电路之间无线地传输数据的发射机电路，用于无线地接收来自其他核的数据传输。发射机电路和接收机电路都可以包括具有压控振荡器的锁相环电路。每个核心可以相对于嵌入在硅芯片上的集成电路中的其它核心以独特的频率发送和接收数据，或者以与嵌入在硅芯片上的集成电路中的其它芯片相同的频率发送和接收数据。核心组可以共享发射机和接收机电路。

23. 发明申请

US20050071575A1 SEMICONDUCTOR DEVICE COMPRISING A PLURALITY OF MEMORY STRUCTURES 失效
标题翻译：包含大量存储器结构的半导体器件
公开(公告)号：US20050071575A1
公开(公告)日：2005-03-31
申请号：US10605366
申请日：2003-09-25
申请人： Kenneth Goodnow , Francis Kampf , Jason Norman , Sebastian Ventrone
发明人： Kenneth Goodnow , Francis Kampf , Jason Norman , Sebastian Ventrone
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F12/0284
摘要： A structure and associated method of transfer data on a semiconductor device, comprising: a plurality of systems within the semiconductor device. Each system comprises at least one processing device and a local memory structure. Each processing device is electrically coupled to each local memory structure within each system. Each local memory structure is electrically coupled to each of the other said local memory structures. Each local memory structure is adapted to share address space with each of the processing devices. Each processing device is adapted to transmit data and instructions to each local memory structure.
摘要翻译：一种半导体器件上传输数据的结构和相关方法，包括：半导体器件内的多个系统。每个系统包括至少一个处理设备和本地存储器结构。每个处理设备电耦合到每个系统内的每个本地存储器结构。每个本地存储器结构电耦合到每个其他所述本地存储器结构。每个本地存储器结构适于与每个处理设备共享地址空间。每个处理设备适于将数据和指令传送到每个本地存储器结构。

24. 发明申请

US20050041448A1 POWER DOWN PROCESSING ISLANDS 失效
标题翻译：断电处理岛
公开(公告)号：US20050041448A1
公开(公告)日：2005-02-24
申请号：US10604328
申请日：2003-07-11
申请人： Rafael Blanco , John Cohn , Kenneth Goodnow , Douglas Stout , Sebastian Ventrone
发明人： Rafael Blanco , John Cohn , Kenneth Goodnow , Douglas Stout , Sebastian Ventrone
IPC分类号： G11C19/08 , H01L20060101
CPC分类号： G06F1/3203 , G06F1/3287 , G11C5/144 , G11C5/147 , G11C2207/2227 , Y02D10/171
摘要： A structure and associated method of processing data on a semi-conductor device comprising an input island, a processing island, and an output island formed on the semiconductor device. The input island is adapted to accept a specified amount of data and enable a means for providing a first specified voltage for powering the processing island after accepting the specified amount of data. The processing island is adapted to receive and process the specified amount of data from the input island upon powering the processing island by the first specified voltage. The output island is adapted to be powered by a second specified voltage. The processing island is further adapted to transmit the processed data to the output island upon said powering by the second specified voltage. The first specified voltage is adapted to be disabled thereby removing power from processing island upon completion of transmission of the processed data to the output island.
摘要翻译：一种在半导体器件上处理数据的结构和相关方法，包括形成在半导体器件上的输入岛，处理岛和输出岛。输入岛适于接收指定数量的数据，并且能够在接受指定数量的数据之后启用用于提供用于为处理岛供电的第一指定电压的装置。处理岛适于在对处理岛供电第一指定电压时从输入岛接收和处理指定量的数据。输出岛适于由第二规定电压供电。处理岛还适于在所述第二规定电压的供电时将经处理的数据发送到输出岛。第一指定电压适于被禁用，从而在完成将处理的数据传输到输出岛时从处理岛去除功率。

25. 发明申请

US20070200744A1 INTRINSIC RC POWER DISTRIBUTION FOR NOISE FILTERING OF ANALOG SUPPLIES 有权
标题翻译：用于噪声滤波的模拟电源的内部RC功率分配
公开(公告)号：US20070200744A1
公开(公告)日：2007-08-30
申请号：US11276451
申请日：2006-02-28
申请人： Anthony Bonaccio , Hayden Cranford , Joseph Iadanza , Sebastian Ventrone , Stephen Wyatt
发明人： Anthony Bonaccio , Hayden Cranford , Joseph Iadanza , Sebastian Ventrone , Stephen Wyatt
IPC分类号： H03M1/66
CPC分类号： G05F1/46
摘要： Analog supply for an analog circuit and process for supplying an analog signal to an analog circuit. The analog supply includes a noise filter having a variable resistor, and a control device coupled to adjust the variable resistor. The control device is structured and arranged to set the resistance of the variable resistor to maximize noise filtering and optimize performance of the analog circuit.
摘要翻译：用于模拟电路的模拟电源和用于向模拟电路提供模拟信号的过程。模拟电源包括具有可变电阻器的噪声滤波器和耦合以调节可变电阻器的控制装置。控制装置被构造和布置成设置可变电阻器的电阻以最大化噪声滤波并优化模拟电路的性能。

26. 发明申请

US20060190908A1 Coding of FPGA and standard cell logic in a tiling structure 审中-公开
标题翻译： FPGA和标准单元逻辑在平铺结构中的编码
公开(公告)号：US20060190908A1
公开(公告)日：2006-08-24
申请号：US11375891
申请日：2006-03-15
申请人： Stanislav Bajuk , Jack Smith , Sebastian Ventrone
发明人： Stanislav Bajuk , Jack Smith , Sebastian Ventrone
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5068
摘要： A method and system for storing and modifying register transfer language (RTL) described logic types. Upon a declaration of a signal interconnect, a language extension of a register transfer language is defined for the signal interconnect based on the signal interconnect”s type. The language extensions allow different signal interconnect types, such as those used with field programmable gate arrays (FPGA) and standard cells, to be stored in a same file array hierarchy. This storage facilitates changing logic types, thus ultimately resulting in an integrated circuit (IC) that is either smaller (using more standard cells) or more flexible (using more FPGA cells). The transition from one RTL type to another is performed within the physical design cycle, in which wiring, timing and placement of components (information) is performed before masking out the final chip design.
摘要翻译：一种存储和修改寄存器传输语言（RTL）的方法和系统，描述逻辑类型。在声明信号互连时，基于信号互连的类型为信号互连定义了寄存器传输语言的语言扩展。语言扩展允许不同的信号互连类型，例如与现场可编程门阵列（例如， FPGA）和标准单元存储在相同的文件阵列层次结构中，这种存储有助于改变逻辑类型，从而最终导致集成电路（IC）更小（使用更多的标准单元）或更灵活（使用更多的FPGA 在物理设计周期内执行从一个RTL类型到另一个RTL类型的转换，其中在屏蔽最终芯片设计之前执行组件（信息）的布线，定时和布局。

27. 发明申请

US20060022753A1 METHOD AND APPARATUS FOR CONTROLLING COMMON-MODE OUTPUT VOLTAGE IN FULLY DIFFERENTIAL AMPLIFIERS 有权
标题翻译：用于控制全差分放大器中的共模输出电压的方法和装置
公开(公告)号：US20060022753A1
公开(公告)日：2006-02-02
申请号：US10710745
申请日：2004-07-30
申请人： Anthony Bonaccio , Hayden Cranford, Jr. , Michael Sorna , Sebastian Ventrone
发明人： Anthony Bonaccio , Hayden Cranford, Jr. , Michael Sorna , Sebastian Ventrone
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F3/4565 , H03F3/45659 , H03F2200/78 , H03F2203/45418 , H03F2203/45424 , H03F2203/45521
摘要： A method for controlling the common-mode output voltage in a fully differential amplifier includes comparing a sensed common-mode output voltage of the fully differential amplifier to a reference voltage, and generating an error signal representing the difference between the sensed common-mode output voltage and the reference voltage. The error signal is utilized to control the body voltage of one or more FET devices included within the fully differential amplifier until the sensed common-mode output voltage is in agreement with said reference voltage.
摘要翻译：一种用于控制全差分放大器中的共模输出电压的方法包括将全差分放大器的感测共模输出电压与参考电压进行比较，并产生一个误差信号，该误差信号表示检测到的共模输出电压和参考电压。误差信号用于控制包括在全差分放大器内的一个或多个FET器件的体电压，直到检测到的共模输出电压与所述参考电压一致。

28. 发明申请

US20050076170A1 Data acknowledgment using impedance mismatching 失效
标题翻译：使用阻抗失配的数据确认
公开(公告)号：US20050076170A1
公开(公告)日：2005-04-07
申请号：US10680756
申请日：2003-10-07
申请人： Michael Boudreaux , Adam Courchesne , Jason Norman , Mark Styduhar , Sebastian Ventrone
发明人： Michael Boudreaux , Adam Courchesne , Jason Norman , Mark Styduhar , Sebastian Ventrone
IPC分类号： G06F12/00
CPC分类号： G06F13/4269
摘要： A structure and associated method to control a flow of data on a semiconductor device. A transmitter, receiver and transmission line are formed within the semiconductor device. The transmitter, receiver, and transmission line are adapted to control data transfer between a first core and a second core within the semiconductor device. The transmitter is adapted to send a signal over the transmission line to the receiver adapted to receive the signal. The receiver is further adapted to create an impedance mismatch to indicate that the second core is unable to transfer the data. The transmitter is adapted to detect the impedance mismatch.
摘要翻译：一种用于控制半导体器件上的数据流的结构和相关方法。在半导体器件内形成发射器，接收器和传输线。发射器，接收器和传输线适于控制半导体器件内的第一芯和第二芯之间的数据传输。发射机适于通过传输线路将信号发送到适于接收信号的接收机。接收机还适于产生阻抗失配以指示第二核心不能传送数据。发射机适用于检测阻抗失配。

29. 发明授权

US08549330B2 Dynamic energy management 有权
标题翻译：动态能源管理
公开(公告)号：US08549330B2
公开(公告)日：2013-10-01
申请号：US12641578
申请日：2009-12-18
申请人： Paul Niekrewicz , Pascal A. Nsame , Aydin Suren , Sebastian Ventrone
发明人： Paul Niekrewicz , Pascal A. Nsame , Aydin Suren , Sebastian Ventrone
IPC分类号： G06F1/00
CPC分类号： G06F1/26 , G06F1/324 , G06F1/329 , G06F1/3296 , G06F9/30079 , G06F9/30083 , G06F9/3009 , Y02D10/126 , Y02D10/172 , Y02D10/24
摘要： A computer system with reliable dynamic energy management includes a thread synchronized energy configurator, the thread synchronized energy configurator extending an instruction decoder of the computer system and the thread synchronized energy configurator is disposed to append an energy configuration field including energy configuration bits to pipeline control bits of instructions in the instruction decoder, a thread synchronized dynamic frequency shifter (DFS), the thread synchronized DFS disposed to set control signals indicative of a frequency shift both per thread and per pipeline, and a thread synchronized general purpose register (GPR) super scaler, wherein the GPR super scaler is disposed to optimize thread operation based upon the set control signals.
摘要翻译：具有可靠的动态能量管理的计算机系统包括螺纹同步的能量配置器，延伸计算机系统的指令解码器的线程同步能量配置器和线程同步的能量配置器被设置为将包括能量配置位的能量配置字段附加到流水线控制位指令解码器中的指令，线程同步动态移频器（DFS），线程同步DFS被设置为设置指示每线程和每个线路的频移的控制信号，以及线程同步通用寄存器（GPR）超级缩放器其中，GPR超级定标器被设置为基于所设置的控制信号来优化线程操作。

30. 发明申请

US20110154064A1 Dynamic Energy Managment 有权
标题翻译：动态能源管理
公开(公告)号：US20110154064A1
公开(公告)日：2011-06-23
申请号：US12641578
申请日：2009-12-18
申请人： Paul Niekrewicz , Pascal A. Nsame , Aydin Suren , Sebastian Ventrone
发明人： Paul Niekrewicz , Pascal A. Nsame , Aydin Suren , Sebastian Ventrone
IPC分类号： G06F1/00
CPC分类号： G06F1/26 , G06F1/324 , G06F1/329 , G06F1/3296 , G06F9/30079 , G06F9/30083 , G06F9/3009 , Y02D10/126 , Y02D10/172 , Y02D10/24
摘要： A computer system with reliable dynamic energy management includes a thread synchronized energy configurator, the thread synchronized energy configurator extending an instruction decoder of the computer system and the thread synchronized energy configurator is disposed to append an energy configuration field including energy configuration bits to pipeline control bits of instructions in the instruction decoder, a thread synchronized dynamic frequency shifter (DFS), the thread synchronized DFS disposed to set control signals indicative of a frequency shift both per thread and per pipeline, and a thread synchronized general purpose register (GPR) super scaler, wherein the GPR super scaler is disposed to optimize thread operation based upon the set control signals.
摘要翻译：具有可靠的动态能量管理的计算机系统包括螺纹同步的能量配置器，延伸计算机系统的指令解码器的线程同步能量配置器和线程同步的能量配置器被设置为将包括能量配置位的能量配置字段附加到流水线控制位指令解码器中的指令，线程同步动态移频器（DFS），线程同步DFS被设置为设置指示每线程和每个线路的频移的控制信号，以及线程同步通用寄存器（GPR）超级缩放器其中，GPR超级定标器被设置为基于所设置的控制信号来优化线程操作。

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