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21. 发明授权

US07737665B2 Multi-threshold charging of a rechargeable battery 有权
标题翻译：可充电电池的多阈值充电
公开(公告)号：US07737665B2
公开(公告)日：2010-06-15
申请号：US11916717
申请日：2006-06-12
申请人： Anthony J. Grewe , Parag Parikh
发明人： Anthony J. Grewe , Parag Parikh
IPC分类号： H02J7/04 , H02J7/16
CPC分类号： H02J7/0029 , H02J7/0068 , H02J7/0091
摘要： In a preferred embodiment, a battery charging system in the form of an integrated circuit (IC), incorporated in a consumer electronic device, has a charging controller, a charging current generator, a junction temperature sensor, and a device current monitor. The junction temperature sensor provides to the charging controller a measured junction temperature of the IC. The charging current generator utilizes fractional synthesis, which involves regulating the duty cycles of multiple current sources, to achieve increased current resolution. The charging controller regulates the charging current provided by the charging current generator based on the relation of the measured junction temperature to three or more threshold temperatures. The device current monitor provides to the charging controller information about the current utilization of the consumer electronic device, thus allowing the charging controller to determine the device non-charging current and give priority for available current to user applications running on the consumer electronic device.
摘要翻译：在优选实施例中，结合在消费电子设备中的集成电路（IC）形式的电池充电系统具有充电控制器，充电电流发生器，结温传感器和器件电流监视器。结温传感器向充电控制器提供了IC的测量结温。充电电流发生器利用分数合成，其涉及调节多个电流源的占空比，以实现增加的电流分辨率。充电控制器基于测量的结温与三个或更多阈值温度的关系来调节由充电电流发生器提供的充电电流。设备电流监视器向充电控制器提供关于消费电子设备的当前利用率的信息，从而允许充电控制器确定设备非充电电流并且为可用电流优先考虑在消费者电子设备上运行的用户应用。

22. 发明授权

US07434082B2 Multi-stage clock selector 失效
标题翻译：多级时钟选择器
公开(公告)号：US07434082B2
公开(公告)日：2008-10-07
申请号：US11240290
申请日：2005-09-30
申请人： Parag Parikh
发明人： Parag Parikh
IPC分类号： G06F1/04
CPC分类号： H03K5/13
摘要： A clock selector for selecting a set of candidate clock signals from among a plurality of input clock signals. The phase selector includes control logic adapted to generate a plurality of control signals and a plurality of muxes controlled by the control signals and arranged in two or more stages having at least a first stage and a last stage. The input to the first stage is the plurality of input clock signals. At least one stage is adapted to (i) receive a plurality of clock signals, (ii) drop at least the first or the last clock signal of the received plurality of clock signals, and (iii) output a reduced plurality of clock signals. The output of the last stage is the set of candidate clock signals.
摘要翻译：一种时钟选择器，用于从多个输入时钟信号中选择一组候选时钟信号。相位选择器包括适于产生多个控制信号的控制逻辑和由控制信号控制的多个多路复用器，并且布置成具有至少第一级和最后级的两级或更多级。第一级的输入是多个输入时钟信号。至少一个级适于（i）接收多个时钟信号，（ii）至少丢弃所接收的多个时钟信号的第一或最后一个时钟信号，以及（iii）输出减少的多个时钟信号。最后一级的输出是候选时钟信号的集合。

23. 发明授权

US07352837B2 Digital phase-locked loop 有权
标题翻译：数字锁相环
公开(公告)号：US07352837B2
公开(公告)日：2008-04-01
申请号：US10856447
申请日：2004-05-28
申请人： Dale H. Nelson , Parag Parikh
发明人： Dale H. Nelson , Parag Parikh
IPC分类号： H03D3/24
CPC分类号： H03L7/089 , H03L7/0995 , H03L7/0997 , H03L7/18 , H03L2207/50
摘要： A phase-locked loop includes a variable frequency generator, a comparator and a counter. The variable frequency generator is configurable for generating an output signal having a frequency which varies based at least in part on at least first and second control signals presented thereto. The comparator is configurable for receiving a first signal and a second signal, the first signal being an input signal presented to the phase-locked loop and the second signal being representative of the output signal from the variable frequency generator. The comparator generates a difference signal representative of a difference between a phase and/or a frequency of the first and second signals, the difference signal comprising the first control signal. The counter is configurable for generating an output count based at least in part on the difference signal from the comparator. The output count is a digital representation of the difference signal, the output count comprising the second control signal. The frequency of the output signal from the variable frequency generator is determined as a function of the difference signal and the output count.
摘要翻译：锁相环包括可变频率发生器，比较器和计数器。可变频率发生器可配置用于产生具有至少部分地基于呈现给其的至少第一和第二控制信号而变化的频率的输出信号。比较器可配置为接收第一信号和第二信号，第一信号是呈现给锁相环的输入信号，第二信号代表来自可变频率发生器的输出信号。比较器产生表示第一和第二信号的相位和/或频率之间的差的差分信号，差分信号包括第一控制信号。计数器可配置用于至少部分地基于来自比较器的差分信号来产生输出计数。输出计数是差分信号的数字表示，输出计数包括第二控制信号。来自可变频率发生器的输出信号的频率被确定为差分信号和输出计数的函数。

24. 发明申请

US20080013663A1 Signal buffering and retiming circuit for multiple memories 有权
标题翻译：用于多个存储器的信号缓冲和重新定时电路
公开(公告)号：US20080013663A1
公开(公告)日：2008-01-17
申请号：US11601998
申请日：2006-11-20
申请人： William P. Cornelius , Tony S. El-Kik , Stephen A. Masnica , Parag Parikh , Anthony W. Seaman
发明人： William P. Cornelius , Tony S. El-Kik , Stephen A. Masnica , Parag Parikh , Anthony W. Seaman
IPC分类号： H04L7/00
CPC分类号： G11C7/22 , G11C7/222
摘要： A signal buffering and retiming (SBR) circuit for a plurality of memory devices. A PLL-based clock generator generates a set of phase-shifted clock signals from a received host clock signal. Each of a plurality of phase selectors independently selects a subset of contiguous clock signals from the set of phase-shifted clock signals. Each subset of contiguous clock signals is applied to a different set of one or more verniers, each vernier independently selecting one of the contiguous clock signals as its retiming clock signal for use in generating either (1) an output clock signal or a retimed bit of address or control data for one or more of the memory devices or (2) a feedback clock signal for the PLL-based clock generator. The SBR circuit can be designed to satisfy relatively stringent signal timing requirements related to skew and delay.
摘要翻译：一种用于多个存储器件的信号缓冲和重定时（SBR）电路。基于PLL的时钟发生器从接收到的主机时钟信号产生一组相移时钟信号。多个相位选择器中的每一个独立地从该组相移时钟信号中选择连续时钟信号的子集。连续时钟信号的每个子集被施加到一个或多个游标的不同集合，每个游标器独立地选择连续时钟信号之一作为其重新定时时钟信号，用于产生（1）输出时钟信号或重新定时位一个或多个存储器件的地址或控制数据或（2）用于基于PLL的时钟发生器的反馈时钟信号。 SBR电路可以设计成满足与偏斜和延迟相关的相对严格的信号定时要求。

25. 发明授权

US07061331B2 Clock generation circuits providing slewing of clock frequency 有权
标题翻译：时钟发生电路提供时钟频率的回转
公开(公告)号：US07061331B2
公开(公告)日：2006-06-13
申请号：US10770046
申请日：2004-02-02
申请人： Parag Parikh
发明人： Parag Parikh
IPC分类号： H03L7/00
CPC分类号： H03L7/18 , H03L7/0996
摘要： Techniques are described for slewing a clock frequency of a clock signal from an initial clock frequency to a final clock frequency. An oscillator provides a number of phase outputs. A current frequency divider value is set to an initial frequency divider value, the initial frequency divider value corresponding to the initial clock frequency. A period of a feedback signal is modified through a number of periods from an initial period to a final period, utilizing one or more of the phase outputs. The current frequency divider value is changed when the period of the feedback signal reaches the final period. The modify and change operations are performed until the current frequency divider value reaches a final frequency divider value, where the final frequency divider value corresponds to the final clock frequency.
摘要翻译：描述了将时钟信号的时钟频率从初始时钟频率转换到最终时钟频率的技术。振荡器提供多个相位输出。当前分频器值被设置为初始分频器值，初始分频器值对应于初始时钟频率。通过使用一个或多个相位输出，从初始周期到最后周期的多个周期来修改反馈信号的周期。当反馈信号的周期达到最后期间时，当前的分频器值被改变。执行修改和改变操作，直到当前分频器值达到最终分频器值，其中最终分频器值对应于最终时钟频率。

26. 发明申请

US20050265505A1 Digital phase-locked loop 有权
标题翻译：数字锁相环
公开(公告)号：US20050265505A1
公开(公告)日：2005-12-01
申请号：US10856447
申请日：2004-05-28
申请人： Dale Nelson , Parag Parikh
发明人： Dale Nelson , Parag Parikh
IPC分类号： H03D3/24 , H03L7/089 , H03L7/099 , H03L7/18
CPC分类号： H03L7/089 , H03L7/0995 , H03L7/0997 , H03L7/18 , H03L2207/50
摘要： A phase-locked loop includes a variable frequency generator, a comparator and a counter. The variable frequency generator is configurable for generating an output signal having a frequency which varies based at least in part on at least first and second control signals presented thereto. The comparator is configurable for receiving a first signal and a second signal, the first signal being an input signal presented to the phase-locked loop and the second signal being representative of the output signal from the variable frequency generator. The comparator generates a difference signal representative of a difference between a phase and/or a frequency of the first and second signals, the difference signal comprising the first control signal. The counter is configurable for generating an output count based at least in part on the difference signal from the comparator. The output count is a digital representation of the difference signal, the output count comprising the second control signal. The frequency of the output signal from the variable frequency generator is determined as a function of the difference signal and the output count.
摘要翻译：锁相环包括可变频率发生器，比较器和计数器。可变频率发生器可配置用于产生具有至少部分地基于呈现给其的至少第一和第二控制信号而变化的频率的输出信号。比较器可配置为接收第一信号和第二信号，第一信号是呈现给锁相环的输入信号，第二信号代表来自可变频率发生器的输出信号。比较器产生表示第一和第二信号的相位和/或频率之间的差的差分信号，差分信号包括第一控制信号。计数器可配置用于至少部分地基于来自比较器的差分信号来产生输出计数。输出计数是差分信号的数字表示，输出计数包括第二控制信号。来自可变频率发生器的输出信号的频率被确定为差分信号和输出计数的函数。

27. 发明申请

US20050242851A1 Signal generator with selectable mode control 失效
标题翻译：具有可选模式控制的信号发生器
公开(公告)号：US20050242851A1
公开(公告)日：2005-11-03
申请号：US10834730
申请日：2004-04-29
申请人： Richard Booth , Roger Minear , Parag Parikh
发明人： Richard Booth , Roger Minear , Parag Parikh
IPC分类号： H03B19/00 , H03L7/06 , H03L7/081 , H03L7/099 , H03L7/197
CPC分类号： H03L7/0996 , H03L7/081 , H03L7/197
摘要： A signal generator circuit includes a controller adapted to generate a divide value in accordance with at least a first control signal, and a divider adapted to divide an output signal of the signal generator circuit by the divisor value. The controller is selectively operable in at least one of a plurality of modes in accordance with at least a second control signal. The controller is configured to calculate each of one or more new divide values so as to vary a frequency of the output signal in accordance with at least one of the first and second control signals. The controller is configured to switch between operational modes and/or switch between divide values, the switching between operational modes and/or divide values being performed in such a manner so as to substantially eliminate discontinuities in the frequency of the output signal.
摘要翻译：信号发生器电路包括适于根据至少第一控制信号产生分频值的控制器和适于将信号发生器电路的输出信号除以除数值的分频器。控制器可根据至少第二控制信号以多种模式中的至少一种选择性地操作。控制器被配置为计算一个或多个新的除法值中的每一个，以便根据第一和第二控制信号中的至少一个来改变输出信号的频率。控制器被配置为在操作模式之间切换和/或在分频值之间切换，操作模式之间的切换和/或以这样的方式进行分频，以便基本上消除输出信号频率的不连续性。

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