会员体验
专利管家（专利管理）
工作空间（专利管理）
风险监控（情报监控）
数据分析（专利分析）
侵权分析（诉讼无效）
联系我们
交流群
官方交流：
QQ群： 891211   
微信请扫码    >>>
现在联系顾问~
下载
著录项
PDF全文
热词
    • 22. 发明授权
      US4818716A Semiconductor device and manufacturing method thereof 失效
    • Semiconductor device and manufacturing method thereof
    • 半导体器件及其制造方法
    • US4818716A
    • 1989-04-04
    • US111690
    • 1987-10-22
    • Kousuke Okuyama , Ken Uchida , Kouichi Kusuyama , Satoshi Meguro , Hisao Katto , Kazuhiro Komori
    • Kousuke Okuyama , Ken Uchida , Kouichi Kusuyama , Satoshi Meguro , Hisao Katto , Kazuhiro Komori
    • H01L27/112 , H01L21/8246 , H01L21/265 , B01J17/00
    • H01L27/1126
    • Disclosed are memory cells of a vertical-type read only memory (ROM) having a plurality of MISFETs connected in series. The MISFETs include gate electrodes formed with multiple conductive layers, in which some of the MISFETs are set to the depletion type and at least some of the remaining MISFETs are set to the enhancement type, so as to write information in the memory cells. The information write operation is conducted through at least two steps. Namely, in the first information write step, gate electrodes are used as a mask to implant an impurity; and in the second step, an impurity is implanted through the gate electrodes into the surface of the semiconductor substrate. These steps enable a semiconductor memory device, such as a vertical-type mask ROM having memory cells with a reduced series resistance and being suitable for a high degree of integration, to be produced.Furthermore, there is disclosed a memory structure of a semiconductor memory device suitable for a higher degree of integration through an arrangement of gate electrodes of multiple layers.
    • 公开了具有串联连接的多个MISFET的垂直型只读存储器（ROM）的存储单元。 MISFET包括形成有多个导电层的栅电极，其中一些MISFET被设置为耗尽型，并且至少一些剩余的MISFET被设置为增强型，以便将信息写入存储单元。 信息写入操作通过至少两个步骤进行。 也就是说，在第一信息写入步骤中，使用栅电极作为掩模来注入杂质; 并且在第二步骤中，通过栅电极将杂质注入到半导体衬底的表面中。 这些步骤使得能够生产半导体存储器件，例如具有降低的串联电阻并且适于高度集成的存储单元的垂直型掩模ROM。 此外，公开了一种半导体存储器件的存储结构，其适用于通过多层栅电极的布置而具有更高的集成度。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 23. 发明授权
      US08039887B2 Non-volatile semiconductor storage device and method for manufacturing the same 有权
    • Non-volatile semiconductor storage device and method for manufacturing the same
    • 非易失性半导体存储装置及其制造方法
    • US08039887B2
    • 2011-10-18
    • US12773967
    • 2010-05-05
    • Masumi Saitoh , Ken Uchida
    • Masumi Saitoh , Ken Uchida
    • H01L29/788
    • H01L29/42324 , H01L21/28273 , H01L29/165 , H01L29/7881
    • A non-volatile semiconductor storage device includes: a semiconductor substrate; a source region and a drain region formed in the semiconductor substrate so as to be separated from each other; a first insulating film formed between the source region and the drain region, on the semiconductor substrate; a floating electrode formed on the first insulating film and including a semiconductor conductive material layer having extension strain; a second insulating film formed on the floating electrode; and a control electrode formed on the second insulating film. The extension strain of the floating electrode becomes gradually small as the location advances from the second insulating film toward the first insulating film, and the floating electrode has extension strain of 0.01% or more at an interface between the floating electrode and the second insulating film, and has extension strain less than 0.01% at an interface between the floating electrode and the first insulating film.
    • 非易失性半导体存储器件包括：半导体衬底; 源极区域和漏极区域，形成在半导体衬底中以便彼此分离; 在所述半导体衬底上形成在所述源极区域和所述漏极区域之间的第一绝缘膜; 形成在所述第一绝缘膜上并具有延伸应变的半导体导电材料层的浮动电极; 形成在浮置电极上的第二绝缘膜; 以及形成在所述第二绝缘膜上的控制电极。 浮动电极的延伸应变随着位置从第二绝缘膜向第一绝缘膜前进而逐渐变小，浮动电极在浮动电极和第二绝缘膜之间的界面具有0.01％以上的延伸应变， 并且在浮动电极和第一绝缘膜之间的界面处具有小于0.01％的延伸应变。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 24. 发明授权
      US07057302B2 Static random access memory 失效
    • Static random access memory
    • 静态随机存取存储器
    • US07057302B2
    • 2006-06-06
    • US10909399
    • 2004-08-03
    • Kazuya Matsuzawa , Ken Uchida , Takahiro Nakauchi
    • Kazuya Matsuzawa , Ken Uchida , Takahiro Nakauchi
    • H01L27/11
    • H01L27/11 , H01L27/1104 , H01L27/1463 , Y10S257/903
    • A static random access memory has first and second complementary field-effect transistors. The first complementary field-effect transistor includes a semiconductor substrate, a first field-effect transistor of electron conduction type which has a first drain region constituting a Schottky junction and a gate electrode, and a first field-effect transistor of positive hole conduction type which shares the first drain region and has a shared gate electrode. The second complementary field-effect transistor includes a second field-effect transistor of electron conduction type which has a second drain region and a gate electrode, a second field-effect transistor of positive hole conduction type which shares the second drain region and has a shared gate electrode. The gate electrode shared by the first and second complementary field-effect transistors is connected to the common drain region of the mutually opposing complementary field-effect transistors, and the static random access memory has superior resistance to software errors.
    • 一种静态随机存取存储器具有第一和第二互补型场效应晶体管。 第一互补场效应晶体管包括：半导体衬底，电子传导类型的第一场效应晶体管，其具有构成肖特基结和栅电极的第一漏极区，和正空穴传导类型的第一场效应晶体管，其 共享第一漏极区，设有一个共用栅电极。 所述第二互补型场效应晶体管包括电子传导类型的第二场效应晶体管，其具有第二漏区和栅电极，正空穴传导类型的这股第二漏区，并具有一共享的第二场效应晶体管 栅电极。 由第一和第二互补场效应晶体管共享栅电极被连接到彼此相对的互补型场效应晶体管的公共漏极区和静态随机存取存储器具有软件错误优异。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 25. 发明授权
      US06252272B1 Semiconductor device, and method of fabricating the same 失效
    • Semiconductor device, and method of fabricating the same
    • 半导体装置及其制造方法
    • US06252272B1
    • 2001-06-26
    • US09267607
    • 1999-03-15
    • Hiroshi Watanabe , Hitoshi Itoh , Ken Uchida
    • Hiroshi Watanabe , Hitoshi Itoh , Ken Uchida
    • H01L29788
    • H01L27/11521 , H01L27/115 , H01L27/11524 , H01L29/42324 , H01L29/7883
    • A surface portion of a semiconductor substrate 41 is serrated at intervals equal to a minimum processing size to form impurity diffusion layers in peaks. These impurity diffusion layers are isolated from each other by valleys. At a valley where a gate is formed, the gate and impurity diffusion layers and in peaks on the two sides of the gate form a MOS transistor. A valley in which no gate is formed functions as an element isolation region. Since a MOS transistor or an element isolation region is formed in one valley, the element area is reduced. A surface of a p-type semiconductor substrate is serrated to form n+-type impurity regions in peaks and floating gates having an upper spired portion in valleys via a silicon oxide film. Control gates are formed on the floating gates via a tunnel oxide film. The lower portion of the control gate has a shape corresponding to the valley and opposes the upper portion of the floating gate by self-alignment. Data is written or erased by using a tunnel current flowing of electrons through the tunnel oxide film between the floating gate and control gate having the above-mentioned shapes and positional relationship. This achieves micropatterning and reduces the maximum operating voltage at the same time.
    • 半导体衬底41的表面部分以等于最小处理尺寸的间隔被锯齿，以在峰上形成杂质扩散层。 这些杂质扩散层通过谷彼此隔离。 在形成栅极的谷中，栅极和杂质扩散层以及栅极两侧的峰形成MOS晶体管。 没有栅极的谷形成元件隔离区域。 由于在一个谷中形成MOS晶体管或元件隔离区域，所以元件面积减小。p型半导体衬底的表面被锯齿形以形成峰顶中的n +型杂质区域和具有上部尖端部分的浮动栅极 谷经硅氧化膜。 控制栅极通过隧道氧化膜形成在浮动栅极上。 控制栅极的下部具有与谷相对应的形状，并且通过自对准与浮栅的上部相对。 通过使用电子流通过具有上述形状和位置关系的浮动栅极和控制栅极之间的隧道氧化物膜的隧道电流来写入或擦除数据。 这实现了微图案化，同时降低了最大工作电压。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
每页展示10个专利
每页展示10个专利
每页展示20个专利
每页展示50个专利
每页展示100个专利

IPRDB

最新中国发明专利 最新美国发明专利 技术领域 专利库 专利分类库 国际专利分类库

热门服务

会员版试用 API 数据接口 找代理 知嘟嘟专利交易 排行榜 大学排行榜 专利百科

关于我们

平台介绍 战略合作 网站地图

友情链接

知嘟嘟专利交易 国家知识产权局 中国商标网

联系方式


©2019-2023 上海吉码数字技术有限公司 版权所有，并保留所有权利 沪ICP备20016256号-6 沪公网安备31011702005475号