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21. 发明授权

US06633072B2 Fabrication method for semiconductor integrated circuit devices and semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件和半导体集成电路器件的制造方法
公开(公告)号：US06633072B2
公开(公告)日：2003-10-14
申请号：US09811589
申请日：2001-03-20
申请人： Kazuo Yamazaki , Shinji Kuniyoshi , Kousuke Kusakari , Takenobu Ikeda , Masahiro Tadokoro
发明人： Kazuo Yamazaki , Shinji Kuniyoshi , Kousuke Kusakari , Takenobu Ikeda , Masahiro Tadokoro
IPC分类号： H01L2978
CPC分类号： H01L21/02071 , H01L21/2807 , H01L21/28123 , H01L21/32137 , H01L21/823842 , H01L21/82385
摘要： To improve the shape of a gate electrode having SiGe, after patterning a gate electrode 15G having an SiGe layer 15b by a dry etching process, a plasma processing (postprocessing) is carried out in an atmosphere of an Ar/CHF3 gas. Thereby, the gate electrode 15G can be formed without causing side etching at two side faces (SiGe layer 15b) of the gate electrode 15G.
摘要翻译：为了改善具有SiGe的栅电极的形状，在图案化具有SiGe层 15 的栅电极之后， PDAT> b ，在Ar / CHF <3>气体气氛中进行等离子体处理（后处理）。因此，可以形成栅极 15 G，而不会在两个侧面（SiGe层 15 b ）栅极电极 15 G。

22. 发明授权

US06506674B2 Method of manufacturing a semiconductor integrated circuit device 有权
公开(公告)号：US06506674B2
公开(公告)日：2003-01-14
申请号：US09964628
申请日：2001-09-28
申请人： Takenobu Ikeda , Masahiro Tadokoro , Masaru Izawa , Takashi Yunogami
发明人： Takenobu Ikeda , Masahiro Tadokoro , Masaru Izawa , Takashi Yunogami
IPC分类号： H01L214763
CPC分类号： H01L21/76897 , H01L21/31116 , H01L21/76802 , H01L21/76814
摘要： A hole is formed on an insulating film made of silicon oxide by selectively plasma-etching the insulating film with an etching gas containing C5F8, O2, and Ar firstly under a condition in which the deposition property of a polymer layer is weak and secondly under a condition in which that of the polymer layer is strong.

23. 发明授权

US06479392B2 Fabrication method for semiconductor integrated circuit devices and semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件和半导体集成电路器件的制造方法
公开(公告)号：US06479392B2
公开(公告)日：2002-11-12
申请号：US09810577
申请日：2001-03-19
申请人： Kazuo Yamazaki , Shinji Kuniyoshi , Kousuke Kusakari , Takenobu Ikeda , Masahiro Tadokoro
发明人： Kazuo Yamazaki , Shinji Kuniyoshi , Kousuke Kusakari , Takenobu Ikeda , Masahiro Tadokoro
IPC分类号： H01L2976
CPC分类号： H01L21/02071 , H01L21/2807 , H01L21/28123 , H01L21/32137 , H01L21/823842 , H01L21/82385
摘要： To improve the shape of a gate electrode having SiGe, after patterning a gate electrode 15G having an SiGe layer 15b by a dry etching process, a plasma processing (postprocessing) is carried out in an atmosphere of an Ar/CHF3 gas. Thereby, the gate electrode 15G can be formed without causing side etching at two side faces (SiGe layer 15b) of the gate electrode 15G.
摘要翻译：为了改善具有SiGe的栅电极的形状，在通过干蚀刻工艺对具有SiGe层15b的栅电极15G进行图案化之后，在Ar / CHF 3气体的气氛中进行等离子体处理（后处理）。由此，可以在栅电极15G的两个侧面（SiGe层15b）不形成侧蚀而形成栅电极15G。

24. 发明授权

US07985678B2 Method of manufacturing a semiconductor integrated circuit device 有权
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US07985678B2
公开(公告)日：2011-07-26
申请号：US12896933
申请日：2010-10-04
申请人： Hiraku Chakihara , Mitsuhiro Noguchi , Masahiro Tadokoro , Naonori Wada , Akio Nishida
发明人： Hiraku Chakihara , Mitsuhiro Noguchi , Masahiro Tadokoro , Naonori Wada , Akio Nishida
IPC分类号： H01L21/44
CPC分类号： H01L27/1104 , H01L27/11
摘要： In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest distance between the second or third trench and the fourth trench is smaller than the resolution limit for the exposure light, the distance between each of the five trenches arranged in one identical memory cell can be reduced to be smaller than resolution limit for the exposure light.
摘要翻译：在形成五个埋入中间导电层的沟槽中，用于连接转移MISFET和驱动MISFET与其上形成的垂直MISFET，其中第二和第三沟槽以及第一，第四和第五沟槽分别通过使用第一和第二光刻胶膜作为掩模。由于即使在第一沟槽和第二或第三沟槽之间的最短距离以及第二沟槽和第三沟槽与第四沟槽之间的最短距离小于分辨率极限的情况下，也可以以高精度形成所有沟槽对于曝光光，布置在一个相同存储单元中的五个沟槽中的每一个之间的距离可以减小到小于曝光光的分辨率极限。

25. 发明授权

US07833905B2 Method of manufacturing a semiconductor integrated circuit device 失效
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US07833905B2
公开(公告)日：2010-11-16
申请号：US12435446
申请日：2009-05-05
申请人： Hiraku Chakihara , Mitsuhiro Noguchi , Masahiro Tadokoro , Naonori Wada , Akio Nishida
发明人： Hiraku Chakihara , Mitsuhiro Noguchi , Masahiro Tadokoro , Naonori Wada , Akio Nishida
IPC分类号： H01L21/44
CPC分类号： H01L27/1104 , H01L27/11
摘要： In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest distance between the second or third trench and the fourth trench is smaller than the resolution limit for the exposure light, the distance between each of the five trenches arranged in one identical memory cell can be reduced to be smaller than resolution limit for the exposure light.
摘要翻译：在形成五个埋入中间导电层的沟槽中，用于连接转移MISFET和驱动MISFET与其上形成的垂直MISFET，其中第二和第三沟槽以及第一，第四和第五沟槽分别通过使用第一和第二光刻胶膜作为掩模。由于即使在第一沟槽和第二或第三沟槽之间的最短距离以及第二沟槽和第三沟槽与第四沟槽之间的最短距离小于分辨率极限的情况下，也可以以高精度形成所有沟槽对于曝光光，布置在一个相同存储单元中的五个沟槽中的每一个之间的距离可以减小到小于曝光光的分辨率极限。

26. 发明授权

US07692168B2 Device and method for outputting charged particle beam 有权
标题翻译：用于输出带电粒子束的装置和方法
公开(公告)号：US07692168B2
公开(公告)日：2010-04-06
申请号：US11774085
申请日：2007-07-06
申请人： Kunio Moriyama , Noriaki Ouchi , Masahiro Tadokoro , Hisataka Fujimaki
发明人： Kunio Moriyama , Noriaki Ouchi , Masahiro Tadokoro , Hisataka Fujimaki
IPC分类号： A61N5/10
CPC分类号： H05H7/12 , A61N5/1048 , A61N2005/1087
摘要： The present invention improves the accuracy of therapy by checking in real time whether an spread-out Bragg peak (SOBP) width agrees with a desired width during irradiation with a beam. The device for outputting a charged particle beam includes a charged particle beam generator 1 including a synchrotron 4; a range modulation device such as a range modulation wheel (RMW) 28 which forms a Bragg peak of an ion beam extracted from this charged particle beam generator 1; an irradiation device 16 which is located in the direction of ion beam propagation of this RMW device 28 and includes a dose monitor 31 for detecting a dose of the ion beam; and an SOBP width calculation device 73 which calculates ion beam Bragg peak formed by the RMW device 28 based on a detection value of the dose monitor 31.
摘要翻译：本发明通过实时检查展开的布拉格峰（SOBP）宽度是否与用束照射期间的期望宽度一致而提高了治疗的准确性。用于输出带电粒子束的装置包括：包括同步加速器4的带电粒子束发生器1; 范围调制装置，例如形成从该带电粒子束发生器1提取的离子束的布拉格峰的范围调制轮（RMW）28; 照射装置16，其位于该RMW装置28的离子束传播方向上，并包括用于检测离子束剂量的剂量监测器31; 以及SOBP宽度计算装置73，其基于剂量监视器31的检测值计算由RMW装置28形成的离子束布拉格峰。

27. 发明授权

US07485477B2 Thin plate manufacturing method and thin plate manufacturing apparatus 失效
标题翻译：薄板制造方法和薄板制造装置
公开(公告)号：US07485477B2
公开(公告)日：2009-02-03
申请号：US11544680
申请日：2006-10-10
申请人： Shuji Goma , Hirozumi Gokaku , Kozaburo Yano , Masahiro Tadokoro , Yasuhiro Nakai
发明人： Shuji Goma , Hirozumi Gokaku , Kozaburo Yano , Masahiro Tadokoro , Yasuhiro Nakai
IPC分类号： H01L21/00
CPC分类号： C30B19/00 , C30B29/06
摘要： In order to obtain a thin plate manufacturing method capable of extremely increasing manufacturing efficiency by enlarging the production scale and remarkably reducing the manufacturing cost per unit area and an apparatus for manufacturing this thin plate, a method and an apparatus performing introduction of a substrate into a main chamber and discharge of the substrate from the main chamber through at least one subsidiary chamber (3, 4) adjacent to the main chamber (1) are employed when manufacturing a silicon thin plate by dipping a surface layer part of the substrate into a silicon melt (7) in a crucible (2) arranged in the main chamber (1) for bonding silicon (5) to the surface of the substrate.
摘要翻译：为了获得能够通过扩大生产规模并显着降低每单位面积的制造成本而极大地提高制造效率的薄板制造方法以及制造该薄板的装置的方法和装置，当通过将基板的表面层部分浸入到硅中来制造硅薄板时，主室通过邻近主室（1）的至少一个辅助室（3,4）从主室排出基板。在布置在主室（1）中的用于将硅（5）粘合到基板表面的坩埚（2）中熔化（7）。

28. 发明授权

US06838388B2 Fabrication method of semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US06838388B2
公开(公告)日：2005-01-04
申请号：US09893577
申请日：2001-06-29
申请人： Masahiro Tadokoro , Masahiro Shioya , Masayuki Kojima , Takenobu Ikeda
发明人： Masahiro Tadokoro , Masahiro Shioya , Masayuki Kojima , Takenobu Ikeda
IPC分类号： H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L27/108
CPC分类号： H01L21/76897 , H01L21/31116 , H01L21/31144 , H01L27/10855 , H01L27/10888
摘要： A fabrication method of a semiconductor integrated circuit device comprises, in an SAC process or HARC process, subjecting a semiconductor substrate to plasma etching to make contact holes in an oxide film made of a silicon oxide film formed on the semiconductor substrate. For improving the ease-in-etching property of the silicon oxide film and selectivity to a nitride film, a residence time of an etching gas within a chamber is so set as to be in a range where selectivity to an insulating film made of silicon nitride is improved by using etching conditions of a low pressure and a large flow rate of the etching gas of C5H8/O2/Ar.

29. 发明授权

US4375885A Reverberatory furnace 失效
标题翻译：反射炉
公开(公告)号：US4375885A
公开(公告)日：1983-03-08
申请号：US212882
申请日：1980-12-04
申请人： Shigeyuki Shigihara , Masahiro Tadokoro
发明人： Shigeyuki Shigihara , Masahiro Tadokoro
IPC分类号： C21C5/52 , F27B1/21 , F27B3/04 , F27B3/18 , F27D3/00 , F27D3/10 , F27D3/14 , H05B6/34 , C21C5/04
CPC分类号： F27B1/21 , C21C5/5247 , F27B3/045 , F27B3/18 , H05B6/34 , F27D2003/0054 , F27D3/10 , F27D3/14 , Y02P10/253
摘要： A reverberatory furnace includes a reverberatory furnace body for melting metal and holding molten metal, having an opening well, an electromagnetic trough for transporting hot molten metal from the reverberatory furnace body upwardly and slantly, having an inductor for generating a travelling magnetic field, and a guide trough for guiding the hot molten metal from the electromagnetic trough to the opening well. The hot molten metal is circulated through the reverberatory furnace.
摘要翻译：反射炉包括用于熔化金属并保持熔融金属的反射炉体，具有开口孔，用于从反射炉体向上且倾斜地输送热熔融金属的电磁槽，具有用于产生行进磁场的电感器，以及引导槽，用于将热熔融金属从电磁槽引导到开口井。热熔融金属循环通过反射炉。

30. 发明授权

US08684151B2 Raw material loading apparatus and pipe unit for raw material loading apparatus 失效
标题翻译：原料装载装置和原料装载装置的管道装置
公开(公告)号：US08684151B2
公开(公告)日：2014-04-01
申请号：US13420297
申请日：2012-03-14
申请人： Masahiro Tadokoro , Takaya Nakamura
发明人： Masahiro Tadokoro , Takaya Nakamura
IPC分类号： B65G11/14
CPC分类号： B65G11/146 , C30B15/02 , C30B29/06
摘要： A loading apparatus for loading raw material into a processing apparatus includes an accommodation section accommodating the raw material, upstream and downstream paths through which the raw material is fed in an airtight state into the processing apparatus, a feeding mechanism that feeds in an airtight state the raw material from the accommodation section to the upstream path, a joint section that separates and joins the upstream and downstream paths, and a closing section, positioned in the second path, that can be opened and closed to maintain the processing apparatus and a portion of the downstream path located downstream of the closing section in an airtight state when the joint section separates the upstream and downstream paths. The downstream path is extendable and contractible to move its downstream end with respect to the joint section while the upstream and downstream paths remain joined.
摘要翻译：用于将原材料装入处理装置的装载装置包括容纳原料的容纳部分，将原料以气密状态供给到处理装置中的上游和下游通路;进气机构，其在气密状态下进给从容纳部到上游路径的原料，分离并连接上下游路径的接合部，以及位于第二路径中的能够打开和关闭以保持处理装置的部分和所述下游路径在所述接合部分离所述上游路径和所述下游路径时位于所述关闭区段的下游，处于气密状态。下游路径是可延伸和收缩的，以相对于接头部分移动其下游端，同时上游和下游路径保持连接。

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