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22. 发明申请

US20160310077A1 DEVICES, SYSTEMS AND METHODS FOR USING AND MONITORING MEDICAL DEVICES 审中-公开
标题翻译：用于使用和监测医疗装置的装置，系统和方法
公开(公告)号：US20160310077A1
公开(公告)日：2016-10-27
申请号：US15078604
申请日：2016-03-23
申请人： William L. Hunter , Douglas R. Holberg , Jeffrey M. Gross
发明人： William L. Hunter , Douglas R. Holberg , Jeffrey M. Gross
IPC分类号： A61B5/00 , A61B5/021 , A61B5/029 , A61B5/026 , A61B5/03 , A61N1/36 , A61N1/37 , A61N1/39 , A61F2/16 , A61F2/00 , A61F2/07 , A61F2/32 , A61F2/38 , A61F5/01 , A61F5/055 , A61B17/74 , A61F2/24 , A61C8/00 , A61B5/01
CPC分类号： A61B5/0031 , A61B5/00 , A61B5/0024 , A61B5/01 , A61B5/02014 , A61B5/021 , A61B5/02108 , A61B5/026 , A61B5/029 , A61B5/036 , A61B5/4851 , A61B5/6812 , A61B5/6853 , A61B5/686 , A61B5/6862 , A61B5/7275 , A61B17/74 , A61B2560/0219 , A61B2562/0219 , A61B2562/0247 , A61B2562/043 , A61B2562/063 , A61C8/00 , A61F2/0059 , A61F2/07 , A61F2/16 , A61F2/2412 , A61F2/32 , A61F2/3859 , A61F2/3877 , A61F2/389 , A61F5/0123 , A61F5/055 , A61N1/3702 , A61N1/3956 , G16H40/60 , G16H40/63
摘要： Medical devices are provided, comprising a medical device and a sensor.
摘要翻译：提供医疗设备，包括医疗设备和传感器。

23. 发明授权

US07421251B2 Precise frequency generation for low duty cycle transceivers using a single crystal oscillator 有权
标题翻译：使用单晶振荡器的低占空比收发器的精确频率产生
公开(公告)号：US07421251B2
公开(公告)日：2008-09-02
申请号：US11095229
申请日：2005-03-31
申请人： Alan L. Westwick , Douglas R. Holberg
发明人： Alan L. Westwick , Douglas R. Holberg
IPC分类号： H04B1/40
CPC分类号： H03L7/00 , H03L1/00
摘要： An apparatus and method for calibrating a non-crystal oscillator in a transceiver unit using a crystal-oscillator includes the step of establishing a time base based upon oscillations of the crystal oscillator. A comparison of the number of oscillations for the non-crystal oscillator and the crystal oscillator is made during a known time period is made. An adjustment is determined based upon the established time base and the compared number of oscillations. The transceiving of the transceiver unit is then controlled based upon this adjustment.
摘要翻译：使用晶体振荡器校准收发器单元中的非晶体振荡器的装置和方法包括基于晶体振荡器的振荡建立时基的步骤。在已知时间段内进行非晶振荡器和晶体振荡器的振荡次数的比较。基于确定的时基和比较的振荡次数来确定调整。然后基于该调整来控制收发器单元的收发。

24. 发明授权

US07286176B2 CCD imager analog processor systems and methods 有权
标题翻译： CCD成像器模拟处理器系统和方法
公开(公告)号：US07286176B2
公开(公告)日：2007-10-23
申请号：US10820577
申请日：2004-04-08
申请人： Douglas R. Holberg , Sandra M. Johnson , Nadi R. Itani , Argos R. Cue
发明人： Douglas R. Holberg , Sandra M. Johnson , Nadi R. Itani , Argos R. Cue
IPC分类号： H04N5/222 , H04N5/228 , H03M1/12 , H03M1/38
CPC分类号： H04N5/23241 , H04N5/23293 , H04N5/335
摘要： A processing system for a charge coupled device (CCD) or CMOS imaging system includes a multi-mode, multiple current level, correlated double sample and variable gain (CDS/VGA) circuit for receiving data from a CCD system, subject to horizontal and vertical timing signals for the system which are locally generated by the processing system itself. The processing system particularly includes programmable timing circuitry for controlling the detection of pixel intensity values from elements of a two-dimensional pixel array, with a programmable low-frequency master vertical timing circuit driving a high-frequency horizontal timing circuit, wherein the vertical and horizontal timing signals are independently locally provided to the array from the analog processor actually sampling the array. The architecture of the processing system further includes a correlated double sampler, a black level clamp, and an A/D conversion module. The processing system includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA) having amplifiers of selectable current level to enable reduced data resolution, an analog-to-digital converter (ADC) having a selectable bit-width output and coupled to said VGA circuit, and a gain circuit coupled to said ADC. The single chip analog front end produces digitized CCD data in a bit formats corresponding to selected current level and data resolution. The VGA amplifier includes circuitry to enable selected data resolution levels respectively for still image capture and separate video display on another viewing screen.
摘要翻译：用于电荷耦合器件（CCD）或CMOS成像系统的处理系统包括多模，多电流电平，相关双样本和可变增益（CDS / VGA）电路，用于从CCD系统接收数据，受水平和垂直由处理系统本身本地生成的系统的定时信号。处理系统特别地包括可编程定时电路，用于通过驱动高频水平定时电路的可编程低频主垂直定时电路来控制来自二维像素阵列的元件的像素强度值的检测，其中垂直和水平定时信号从模拟处理器独立地本地提供给阵列，实际上对阵列进行采样。处理系统的架构还包括相关双采样器，黑电平钳位器和A / D转换模块。该处理系统包括用于产生成像器信号的相机系统，用于从成像器接收数据的相关双样本（CDS）电路，具有可选电流电平的放大器的可变增益放大器（VGA），以实现减少的数据分辨率; 具有可选位宽输出并耦合到所述VGA电路的数模转换器（ADC），以及耦合到所述ADC的增益电路。单芯片模拟前端以对应于所选电流和数据分辨率的位格式生成数字化CCD数据。 VGA放大器包括分别为静止图像拍摄和在另一个观看屏幕上分离的视频显示启用所选数据分辨率级别的电路。

25. 发明授权

US07164311B2 Method and apparatus for tuning GMC filter 有权
标题翻译： GMC滤波器调谐方法及装置
公开(公告)号：US07164311B2
公开(公告)日：2007-01-16
申请号：US10954887
申请日：2004-09-30
申请人： Golam R. Chowdhury , Douglas R. Holberg
发明人： Golam R. Chowdhury , Douglas R. Holberg
IPC分类号： H03K5/00
CPC分类号： H03H11/04 , H03B5/14 , H03F1/342 , H03F3/45183 , H03F2203/45318 , H03F2203/45366 , H03L7/0995
摘要： A system and method for providing a tunable GMC filter is disclosed wherein a transconducted element having an attenuator in a feedback loop therewith is allowed to oscillate at a first oscillation frequency. An input to the filter enables tuning of the oscillation frequency to a pre-determined frequency.
摘要翻译：公开了一种用于提供可调GMC滤波器的系统和方法，其中具有与其反馈回路中的衰减器的跨导元件被允许以第一振荡频率振荡。滤波器的输入使振荡频率调谐到预定频率。

26. 发明授权

US06720999B1 CCD imager analog processor systems and methods 有权
标题翻译： CCD成像器模拟处理器系统和方法
公开(公告)号：US06720999B1
公开(公告)日：2004-04-13
申请号：US09283112
申请日：1999-03-31
申请人： Douglas R. Holberg , Sandra M. Johnson , Nadi R. Itani , Argos R. Cue
发明人： Douglas R. Holberg , Sandra M. Johnson , Nadi R. Itani , Argos R. Cue
IPC分类号： H04N5228
CPC分类号： H04N5/23241 , H04N5/23293 , H04N5/335
摘要： A processing system for a charge coupled device (CCD) or CMOS imaging system includes a multi-mode, multiple current level, correlated double sample and variable gain (CDS/VGA) circuit for receiving data from a CCD system, subject to horizontal and vertical timing signals for the system which are locally generated by the processing system itself. The processing system particularly includes programmable timing circuitry for controlling the detection of pixel intensity values from elements of a two-dimensional pixel array, with a programable low-frequency master vertical timing circuit driving a high-frequency horizontal timing circuit, wherein the vertical and horizontal timing signals are independently locally provided to the array from the analog processor actually sampling the array. The architecture of the processing system further includes a correlated double sampler, a black level clamp, and an A/D conversion module. The processing system includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA) having amplifiers of selectable current level to enable reduced data resolution, an analog-to-digital converter (ADC) having a selectable bit-width output and coupled to said VGA circuit, and a gain circuit coupled to said ADC. The single chip analog front end produces digitized CCD data in a bit formats corresponding to selected current level and data resolution. The VGA amplifier includes circuitry to enable selected data resolution levels respectively for still image capture and separate video display on another viewing screen.
摘要翻译：用于电荷耦合器件（CCD）或CMOS成像系统的处理系统包括多模，多电流电平，相关双样本和可变增益（CDS / VGA）电路，用于从CCD系统接收数据，受水平和垂直由处理系统本身本地生成的系统的定时信号。处理系统特别地包括可编程定时电路，用于通过驱动高频水平定时电路的可编程低频主垂直定时电路来控制来自二维像素阵列的元件的像素强度值的检测，其中垂直和水平定时信号从模拟处理器独立地本地提供给阵列，实际上对阵列进行采样。处理系统的架构还包括相关双采样器，黑电平钳位器和A / D转换模块。该处理系统包括用于产生成像器信号的相机系统，用于从成像器接收数据的相关双样本（CDS）电路，具有可选电流电平的放大器的可变增益放大器（VGA），以实现减少的数据分辨率; 具有可选位宽输出并耦合到所述VGA电路的数模转换器（ADC），以及耦合到所述ADC的增益电路。单芯片模拟前端以对应于所选电流和数据分辨率的位格式生成数字化CCD数据。 VGA放大器包括分别为静止图像拍摄和在另一个观看屏幕上分离的视频显示启用所选数据分辨率级别的电路。

27. 发明授权

US4390754A Tone generator circuit 失效
标题翻译：音频发生器电路
公开(公告)号：US4390754A
公开(公告)日：1983-06-28
申请号：US265983
申请日：1980-06-30
申请人： Douglas R. Holberg
发明人： Douglas R. Holberg
IPC分类号： H04M1/50
CPC分类号： H04M1/505
摘要： A dual-tone multi-frequency (DTMF) tone generator circuit (10) produces selected frequency row and column tones which are combined to generate a DTMF signal. Key board scan circuits (42,44) scan a conventional push-button telephone key board to produce row and column input signals. Row and column fundamental rate signals are generated by fundamental counters (48,76) from a reference signal derived from an external crystal (12). Row and column integration rate signals are generated by integrator counters (50,78) also derived from the reference signal. Specialized row and column clock control signals (SLOPE RATE, SLOPE SIGN, AUTO ZERO) are produced by clock generators (58,82). Row and column integrators (64,92) integrate reference signals to produce discrete voltage steps at the rate of the row and column integration rate signals to produce row and column signals made up of a plurality of segments for each cycle of the signal. Each signal segment comprises a plurality of similar voltage steps having amplitude and polarity determined by the specialized row and column clock signals (SLOPE RATE, SLOPE SIGN). The row and column signals are combined in a summer (68) to produce the DTMF signal.
摘要翻译： PCT No.PCT / US80 / 00817 Sec。 371日期1980年6月30日第 102（e）1980年6月30日PCT申请1980年6月30日PCT公布。第WO82 / 00231号公报日期：1982年1月21日。双音多频（DTMF）乐音发生器电路（10）产生组合以产生DTMF信号的所选频率行和列音调。键盘扫描电路（42,44）扫描传统的按钮电话键盘以产生行和列输入信号。行和列基本速率信号由来自外部晶体（12）的参考信号的基本计数器（48,76）产生。行和列积分率信号由也从参考信号导出的积分器计数器（50,78）产生。专门的行和列时钟控制信号（SLOPE RATE，SLOPE SIGN，AUTO ZERO）由时钟发生器（58,82）生成。行和列积分器（64,92）集成参考信号以以行和列积分率信号的速率产生离散电压步长，以产生由信号的每个周期的多个段组成的行和列信号。每个信号段包括具有由专门的行和列时钟信号（SLOPE RATE，SLOPE SIGN）确定的振幅和极性的多个相似的电压阶跃。行和列信号在夏季（68）中组合以产生DTMF信号。

28. 发明授权

US07719595B1 Preview mode low resolution output system and method 有权
标题翻译：预览模式低分辨率输出系统和方法
公开(公告)号：US07719595B1
公开(公告)日：2010-05-18
申请号：US11980173
申请日：2007-10-30
申请人： Sandra M. Johnson , Douglas R. Holberg , Nadi R. Itani
发明人： Sandra M. Johnson , Douglas R. Holberg , Nadi R. Itani
IPC分类号： H04N5/222 , H04N5/228 , H03M1/12 , H03M1/38
CPC分类号： H03M1/002 , H03M1/007 , H03M1/12 , H04N5/232 , H04N5/23245
摘要： A processing system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA) having amplifiers of selectable current level to enable reduced data resolution in a preview display, a low power mode analog-to-digital converter (ADC) having a selectable narrow bit-width output and coupled to said VGA circuit, and a gain circuit coupled to said ADC. The single chip low-power analog front end produces digitized CCD data in either 13-bit, 12-bit or 10-bit formats at a first current level and 9-bit, 8-bit, or 6-bit formats at a second current level. The VGA amplifier includes symmetrical subcircuits which are independently actuable to enable full or reduced data resolution levels respectively for still image capture operation and video previewing on a separate preview screen.
摘要翻译：用于电荷耦合器件（CCD）或CMOS成像系统的处理系统包括用于从成像器接收数据的相关双样本（CDS）电路，具有可选电流电平的放大器的可变增益放大器（VGA），以使数据分辨率降低预览显示器，具有可选择的窄位宽输出并耦合到所述VGA电路的低功率模式模数转换器（ADC）以及耦合到所述ADC的增益电路。单芯片低功耗模拟前端以第一电流电平以13位，12位或10位格式生成数字化CCD数据，并以第二个电流产生9位，8位或6位格式水平。 VGA放大器包括对称的子电路，它们独立地可启动，以分别在单独的预览屏幕上实现静态图像捕获操作和视频预览的全部或者简化的数据分辨率级别。

29. 发明授权

US07502883B2 USB integrated module 失效
标题翻译： USB集成模块
公开(公告)号：US07502883B2
公开(公告)日：2009-03-10
申请号：US10625580
申请日：2003-07-23
申请人： Daniel Kenneth Lunecki , Douglas R. Holberg
发明人： Daniel Kenneth Lunecki , Douglas R. Holberg
IPC分类号： G06F13/14
CPC分类号： H01R13/665 , H01R31/06
摘要： USB integrated module. A modularized serial data module is disclosed for interfacing with a serial data line operating in accordance with a first serial data protocol that transmits/receives data and also provides power to the modularized serial data module. The module includes a connector housing for providing a physical interface with the serial data line. A processor housing is disposed adjacent the connector housing and operable to interface therewith. A processor is disposed within the processor housing and operable to be powered by the serial data line through the connector housing and is also operable to interface with the data portion of the serial data line through the connector housing. The processor is operable to provide processing of information based upon data received from the serial data line through the connector housing or processing of information for transmission to the serial data line through the connector housing.
摘要翻译： USB集成模块。公开了一种模块化串行数据模块，用于与根据发送/接收数据的第一串行数据协议操作的串行数据线进行接口，并且还向模块化的串行数据模块提供电力。该模块包括用于提供与串行数据线的物理接口的连接器壳体。处理器壳体邻近连接器壳体设置并且可操作以与其连接。处理器设置在处理器壳体内并且可操作以通过连接器壳体由串行数据线供电，并且还可操作以通过连接器壳体与串行数据线的数据部分进行接口。处理器可操作以基于通过连接器壳体从串行数据线接收的数据或处理用于通过连接器壳体传输到串行数据线的信息来提供信息的处理。

30. 发明授权

US07314173B2 Optical reader with ultraviolet wavelength capability 有权
标题翻译：具有紫外线波长能力的光学读卡器
公开(公告)号：US07314173B2
公开(公告)日：2008-01-01
申请号：US10884377
申请日：2004-07-02
申请人： Jeffry Jovan Philyaw , Douglas R. Holberg
发明人： Jeffry Jovan Philyaw , Douglas R. Holberg
IPC分类号： G06K7/14
CPC分类号： H04L29/12009 , G06F17/30722 , G06F17/30876 , G06F17/30879 , G06K7/10762 , G06K7/10831 , G06K7/10881 , G06Q20/208 , G06Q30/02 , G06Q30/0257 , H04L29/06 , H04L29/12047 , H04L29/12594 , H04L61/15 , H04L61/301 , H04L67/02 , H04L69/329 , H04N21/4622 , H04N21/4782 , H04N21/812
摘要： An optical reader is provided for reading a bar code having ultraviolet-wavelength-responsive properties. The optical reader includes an ultraviolet light source, a photodetector, an optical system and a decoder. The ultraviolet light source generates ultraviolet light having a wavelength shorter than visible light and longer than X-rays for illuminating a target region. The photodetector generates output electrical signals indicative of light incident thereon having a wavelength within a predetermined range of wavelengths. The optical system includes a projection portion and a collection portion. The projection portion directs the ultraviolet light along a projection path extending from the ultraviolet light source to the target region. The collection portion collects the light from a bar code when the bar code occupies the target region and directs the collected light along a collection path extending from the target region to the photodetector. The decoder receives the output electrical signals of the photodetector and produces, in response thereto, electrical signals indicative of information encoded in the bar code.
摘要翻译：提供了用于读取具有紫外线 - 波长响应特性的条形码的光学读取器。光学读取器包括紫外光源，光电检测器，光学系统和解码器。紫外光源产生波长短于可见光的紫外光，并且比用于照射目标区域的X射线长。光电检测器产生指示入射到其上的具有波长在预定波长范围内的光的输出电信号。光学系统包括突出部分和收集部分。突出部沿着从紫外线光源延伸到目标区域的投影路径引导紫外线。当条形码占据目标区域时，收集部分收集来自条形码的光，并将收集的光沿着从目标区域延伸到光电检测器的收集路径引导。解码器接收光电检测器的输出电信号，并响应于此产生指示在条形码中编码的信息的电信号。

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