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1. 发明授权

US07286176B2 CCD imager analog processor systems and methods 有权
标题翻译： CCD成像器模拟处理器系统和方法
公开(公告)号：US07286176B2
公开(公告)日：2007-10-23
申请号：US10820577
申请日：2004-04-08
申请人： Douglas R. Holberg , Sandra M. Johnson , Nadi R. Itani , Argos R. Cue
发明人： Douglas R. Holberg , Sandra M. Johnson , Nadi R. Itani , Argos R. Cue
IPC分类号： H04N5/222 , H04N5/228 , H03M1/12 , H03M1/38
CPC分类号： H04N5/23241 , H04N5/23293 , H04N5/335
摘要： A processing system for a charge coupled device (CCD) or CMOS imaging system includes a multi-mode, multiple current level, correlated double sample and variable gain (CDS/VGA) circuit for receiving data from a CCD system, subject to horizontal and vertical timing signals for the system which are locally generated by the processing system itself. The processing system particularly includes programmable timing circuitry for controlling the detection of pixel intensity values from elements of a two-dimensional pixel array, with a programmable low-frequency master vertical timing circuit driving a high-frequency horizontal timing circuit, wherein the vertical and horizontal timing signals are independently locally provided to the array from the analog processor actually sampling the array. The architecture of the processing system further includes a correlated double sampler, a black level clamp, and an A/D conversion module. The processing system includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA) having amplifiers of selectable current level to enable reduced data resolution, an analog-to-digital converter (ADC) having a selectable bit-width output and coupled to said VGA circuit, and a gain circuit coupled to said ADC. The single chip analog front end produces digitized CCD data in a bit formats corresponding to selected current level and data resolution. The VGA amplifier includes circuitry to enable selected data resolution levels respectively for still image capture and separate video display on another viewing screen.
摘要翻译：用于电荷耦合器件（CCD）或CMOS成像系统的处理系统包括多模，多电流电平，相关双样本和可变增益（CDS / VGA）电路，用于从CCD系统接收数据，受水平和垂直由处理系统本身本地生成的系统的定时信号。处理系统特别地包括可编程定时电路，用于通过驱动高频水平定时电路的可编程低频主垂直定时电路来控制来自二维像素阵列的元件的像素强度值的检测，其中垂直和水平定时信号从模拟处理器独立地本地提供给阵列，实际上对阵列进行采样。处理系统的架构还包括相关双采样器，黑电平钳位器和A / D转换模块。该处理系统包括用于产生成像器信号的相机系统，用于从成像器接收数据的相关双样本（CDS）电路，具有可选电流电平的放大器的可变增益放大器（VGA），以实现减少的数据分辨率; 具有可选位宽输出并耦合到所述VGA电路的数模转换器（ADC），以及耦合到所述ADC的增益电路。单芯片模拟前端以对应于所选电流和数据分辨率的位格式生成数字化CCD数据。 VGA放大器包括分别为静止图像拍摄和在另一个观看屏幕上分离的视频显示启用所选数据分辨率级别的电路。

2. 发明授权

US06720999B1 CCD imager analog processor systems and methods 有权
标题翻译： CCD成像器模拟处理器系统和方法
公开(公告)号：US06720999B1
公开(公告)日：2004-04-13
申请号：US09283112
申请日：1999-03-31
申请人： Douglas R. Holberg , Sandra M. Johnson , Nadi R. Itani , Argos R. Cue
发明人： Douglas R. Holberg , Sandra M. Johnson , Nadi R. Itani , Argos R. Cue
IPC分类号： H04N5228
CPC分类号： H04N5/23241 , H04N5/23293 , H04N5/335
摘要： A processing system for a charge coupled device (CCD) or CMOS imaging system includes a multi-mode, multiple current level, correlated double sample and variable gain (CDS/VGA) circuit for receiving data from a CCD system, subject to horizontal and vertical timing signals for the system which are locally generated by the processing system itself. The processing system particularly includes programmable timing circuitry for controlling the detection of pixel intensity values from elements of a two-dimensional pixel array, with a programable low-frequency master vertical timing circuit driving a high-frequency horizontal timing circuit, wherein the vertical and horizontal timing signals are independently locally provided to the array from the analog processor actually sampling the array. The architecture of the processing system further includes a correlated double sampler, a black level clamp, and an A/D conversion module. The processing system includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA) having amplifiers of selectable current level to enable reduced data resolution, an analog-to-digital converter (ADC) having a selectable bit-width output and coupled to said VGA circuit, and a gain circuit coupled to said ADC. The single chip analog front end produces digitized CCD data in a bit formats corresponding to selected current level and data resolution. The VGA amplifier includes circuitry to enable selected data resolution levels respectively for still image capture and separate video display on another viewing screen.
摘要翻译：用于电荷耦合器件（CCD）或CMOS成像系统的处理系统包括多模，多电流电平，相关双样本和可变增益（CDS / VGA）电路，用于从CCD系统接收数据，受水平和垂直由处理系统本身本地生成的系统的定时信号。处理系统特别地包括可编程定时电路，用于通过驱动高频水平定时电路的可编程低频主垂直定时电路来控制来自二维像素阵列的元件的像素强度值的检测，其中垂直和水平定时信号从模拟处理器独立地本地提供给阵列，实际上对阵列进行采样。处理系统的架构还包括相关双采样器，黑电平钳位器和A / D转换模块。该处理系统包括用于产生成像器信号的相机系统，用于从成像器接收数据的相关双样本（CDS）电路，具有可选电流电平的放大器的可变增益放大器（VGA），以实现减少的数据分辨率; 具有可选位宽输出并耦合到所述VGA电路的数模转换器（ADC），以及耦合到所述ADC的增益电路。单芯片模拟前端以对应于所选电流和数据分辨率的位格式生成数字化CCD数据。 VGA放大器包括分别为静止图像拍摄和在另一个观看屏幕上分离的视频显示启用所选数据分辨率级别的电路。

3. 发明授权

US07304679B1 Preview mode low resolution output system and method 有权
标题翻译：预览模式低分辨率输出系统和方法
公开(公告)号：US07304679B1
公开(公告)日：2007-12-04
申请号：US10742170
申请日：2003-12-19
申请人： Sandra M. Johnson , Douglas R. Holberg , Nadi R. Itani
发明人： Sandra M. Johnson , Douglas R. Holberg , Nadi R. Itani
IPC分类号： H04N5/222 , H04N5/235 , H04N5/20 , H03M1/12
CPC分类号： H03M1/002 , H03M1/007 , H03M1/12 , H04N5/232 , H04N5/23245
摘要： A processing system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA) having amplifiers of selectable current level to enable reduced data resolution in a preview display, a low power mode analog-to-digital converter (ADC) having a selectable narrow bit-width output and coupled to said VGA circuit, and a gain circuit coupled to said ADC. The single chip low-power analog front end produces digitized CCD data in either 13-bit, 12-bit or 10-bit formats at a first current level and 9-bit, 8-bit, or 6-bit formats at a second current level. The VGA amplifier includes symmetrical subcircuits which are independently actuable to enable full or reduced data resolution levels respectively for still image capture operation and video previewing on a separate preview screen.
摘要翻译：用于电荷耦合器件（CCD）或CMOS成像系统的处理系统包括用于从成像器接收数据的相关双样本（CDS）电路，具有可选电流电平的放大器的可变增益放大器（VGA），以使数据分辨率降低预览显示器，具有可选择的窄位宽输出并耦合到所述VGA电路的低功率模式模数转换器（ADC）以及耦合到所述ADC的增益电路。单芯片低功耗模拟前端以第一电流电平以13位，12位或10位格式生成数字化CCD数据，并以第二个电流产生9位，8位或6位格式水平。 VGA放大器包括对称的子电路，它们独立地可启动，以分别在单独的预览屏幕上实现静态图像捕获操作和视频预览的全部或者简化的数据分辨率级别。

4. 发明授权

US07719595B1 Preview mode low resolution output system and method 有权
标题翻译：预览模式低分辨率输出系统和方法
公开(公告)号：US07719595B1
公开(公告)日：2010-05-18
申请号：US11980173
申请日：2007-10-30
申请人： Sandra M. Johnson , Douglas R. Holberg , Nadi R. Itani
发明人： Sandra M. Johnson , Douglas R. Holberg , Nadi R. Itani
IPC分类号： H04N5/222 , H04N5/228 , H03M1/12 , H03M1/38
CPC分类号： H03M1/002 , H03M1/007 , H03M1/12 , H04N5/232 , H04N5/23245
摘要： A processing system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA) having amplifiers of selectable current level to enable reduced data resolution in a preview display, a low power mode analog-to-digital converter (ADC) having a selectable narrow bit-width output and coupled to said VGA circuit, and a gain circuit coupled to said ADC. The single chip low-power analog front end produces digitized CCD data in either 13-bit, 12-bit or 10-bit formats at a first current level and 9-bit, 8-bit, or 6-bit formats at a second current level. The VGA amplifier includes symmetrical subcircuits which are independently actuable to enable full or reduced data resolution levels respectively for still image capture operation and video previewing on a separate preview screen.
摘要翻译：用于电荷耦合器件（CCD）或CMOS成像系统的处理系统包括用于从成像器接收数据的相关双样本（CDS）电路，具有可选电流电平的放大器的可变增益放大器（VGA），以使数据分辨率降低预览显示器，具有可选择的窄位宽输出并耦合到所述VGA电路的低功率模式模数转换器（ADC）以及耦合到所述ADC的增益电路。单芯片低功耗模拟前端以第一电流电平以13位，12位或10位格式生成数字化CCD数据，并以第二个电流产生9位，8位或6位格式水平。 VGA放大器包括对称的子电路，它们独立地可启动，以分别在单独的预览屏幕上实现静态图像捕获操作和视频预览的全部或者简化的数据分辨率级别。

5. 发明授权

US06686957B1 Preview mode low resolution output system and method 有权
标题翻译：预览模式低分辨率输出系统和方法
公开(公告)号：US06686957B1
公开(公告)日：2004-02-03
申请号：US09282524
申请日：1999-03-31
申请人： Sandra M. Johnson , Douglas R. Holberg , Nadi R. Itani
发明人： Sandra M. Johnson , Douglas R. Holberg , Nadi R. Itani
IPC分类号： H04N5228
CPC分类号： H03M1/002 , H03M1/007 , H03M1/12 , H04N5/232 , H04N5/23245
摘要： A processing system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA) having amplifiers of selectable current level to enable reduced data resolution in a preview display, a low power mode analog-to-digital converter (ADC) having a selectable narrow bit-width output and coupled to said VGA circuit, and a gain circuit coupled to said ADC. The single chip low-power analog front end produces digitized CCD data in either 13-bit, 12-bit or 10-bit formats at a first current level and 9-bit, 8-bit, or 6-bit formats at a second current level. The VGA amplifier includes symmetrical subcircuits which are independently actuable to enable full or reduced data resolution levels respectively for still image capture operation and video previewing on a separate preview screen.
摘要翻译：用于电荷耦合器件（CCD）或CMOS成像系统的处理系统包括用于从成像器接收数据的相关双样本（CDS）电路，具有可选电流电平的放大器的可变增益放大器（VGA），以使数据分辨率降低预览显示器，具有可选择的窄位宽输出并耦合到所述VGA电路的低功率模式模数转换器（ADC），以及耦合到所述ADC的增益电路。单芯片低功耗模拟前端以第一电流电平以13位，12位或10位格式生成数字化CCD数据，并以第二个电流产生9位，8位或6位格式水平。 VGA放大器包括对称的子电路，它们独立地可启动，以分别在单独的预览屏幕上实现静态图像捕获操作和视频预览的全部或者简化的数据分辨率级别。

6. 发明授权

US06252536B1 Dynamic range extender apparatus, system, and method for digital image receiver system 有权
标题翻译：用于数字图像接收系统的动态范围扩展装置，系统和方法
公开(公告)号：US06252536B1
公开(公告)日：2001-06-26
申请号：US09283779
申请日：1999-03-31
申请人： Sandra M. Johnson , Nadi R. Itani
发明人： Sandra M. Johnson , Nadi R. Itani
IPC分类号： H03M112
CPC分类号： H04N5/361 , H03M1/18 , H03M1/187
摘要： A dynamic range enhancement system (DRES) receives input signals from an imager device connected to a correlated double sampling (CDS) circuit for receiving the video signal from the CCD imaging device. The dynamic range enhancement system includes a variable gain amplifier (VGA), and a limited bit-width analog-to-digital converter (ADC) which digitizes the analog signal received from the VGA. The output of the ADC is provided to an initial bit range position of a wider bit-width shifter connected to the output of the ADC. The DRES system includes a 2-bit ADC for extending the dynamic range of the imager device, which enhances the dynamic range of a 10 bit ADC to 13 bits.
摘要翻译：动态范围增强系统（DRES）从连接到相关双采样（CDS）电路的成像器装置接收输入信号，用于从CCD成像装置接收视频信号。动态范围增强系统包括可变增益放大器（VGA）和有限位宽模数转换器（ADC），数字化从VGA接收的模拟信号。 ADC的输出被提供给连接到ADC的输出的较宽位移移位器的初始位范围位置。 DRES系统包括一个2位ADC，用于扩展成像器件的动态范围，从而将10位ADC的动态范围增加到13位。

7. 发明授权

US06617934B1 Phase locked loop circuits, systems, and methods 有权
标题翻译：锁相环电路，系统和方法
公开(公告)号：US06617934B1
公开(公告)日：2003-09-09
申请号：US09283098
申请日：1999-03-31
申请人： Douglas R. Holberg , Sandra M. Johnson
发明人： Douglas R. Holberg , Sandra M. Johnson
IPC分类号： H03B524
CPC分类号： H03K3/0322 , H03L7/0995
摘要： A phase locked loop in an imaging system is used to generate signals on one of eight equal phase steps within a clock period. The phase locked loop outputs eight clock phases, or four clock phases and their complements, each running at the pixel rate, eliminating the need for higher speed circuitry. According to one embodiment, the phase locked loop employs an oscillator with three inverting stages and one non-inverting stage. The output of each stage is shifted in phase 45 degrees from the previous one, in terms of pixel clock rate. Differential stages are employed so that the delay of the inverting and non-inverting stage are the same. According to the present invention, the output of the last stage is swapped onto the input of the first stage, making it non-inverting without path delay, permitting oscillation with each stage's output remaining at 45 degrees of the previous stage's phase.
摘要翻译：成像系统中的锁相环用于在时钟周期内的八个相位相位步骤之一上产生信号。锁相环输出8个时钟相位或4个时钟相位及其补码，每个时钟相位以像素速率运行，无需更高速度电路。根据一个实施例，锁相环采用具有三个反相级和一个非反相级的振荡器。在像素时钟速率方面，每个级的输出与前一级的相位相差45度。使用差分级，使得反相和非反相级的延迟相同。根据本发明，最后一级的输出被交换到第一级的输入端上，使其不反相而没有路径延迟，允许每级的输出保持在前一级相位45度的振荡。

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