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21. 发明授权

US07573772B2 Semiconductor memory device and self-refresh method therefor 有权
标题翻译：半导体存储器件及其自刷新方法
公开(公告)号：US07573772B2
公开(公告)日：2009-08-11
申请号：US11612866
申请日：2006-12-19
申请人： Kyung-Woo Nam , Ho-Cheol Lee
发明人： Kyung-Woo Nam , Ho-Cheol Lee
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C7/1075 , G11C11/40603 , G11C11/40615 , G11C11/40618
摘要： A semiconductor memory device and a self-refresh method in which the semiconductor memory device includes a plurality of input/output ports having respective independent operation, a period of self-refresh through one of the plurality of input/output ports being subordinate to a kind of operation through another input/output port. Whereby, a refresh characteristic in a multi-port semiconductor memory device including a dual-port semiconductor memory device may be improved.
摘要翻译：一种半导体存储器件和自刷新方法，其中所述半导体存储器件包括具有各自独立操作的多个输入/输出端口，所述多个输入/输出端口中的一个输入/输出端口中的一个从属于一种类型的自刷新周期的操作通过另一个输入/输出端口。因此，可以提高包括双端口半导体存储器件的多端口半导体存储器件中的刷新特性。

22. 发明授权

US07505353B2 Multi-port semiconductor memory device having variable access paths and method 有权
标题翻译：具有可变存取路径和方法的多端口半导体存储器件
公开(公告)号：US07505353B2
公开(公告)日：2009-03-17
申请号：US11466389
申请日：2006-08-22
申请人： Nam-Jong Kim , Ho-Cheol Lee , Kyoung-Hwan Kwon , Hyong-Ryol Hwang , Hyo-Joo Ahn
发明人： Nam-Jong Kim , Ho-Cheol Lee , Kyoung-Hwan Kwon , Hyong-Ryol Hwang , Hyo-Joo Ahn
IPC分类号： G11C8/00 , G11C8/12 , G11C8/16 , G11C7/10
CPC分类号： G11C8/12 , G11C7/1075 , G11C29/1201 , G11C29/26 , G11C29/48 , G11C2029/1802
摘要： A multi-port semiconductor memory device having variable access paths and a method therefore are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports.
摘要翻译：提供具有可变存取路径的多端口半导体存储器件及其方法。半导体存储器件包括多个输入/输出端口; 分成多个存储区域的存储器阵列; 以及选择控制单元，用于可变地控制存储区域和输入/输出端口之间的访问路径，使得通过至少一个输入/输出端口访问每个存储器区域。

23. 发明申请

US20050001300A1 Semiconductor package having multiple embedded chips 有权
标题翻译：具有多个嵌入式芯片的半导体封装
公开(公告)号：US20050001300A1
公开(公告)日：2005-01-06
申请号：US10803043
申请日：2004-03-18
申请人： Ho-Cheol Lee
发明人： Ho-Cheol Lee
IPC分类号： H01L23/12 , H01L25/065 , H01L21/48 , H01L23/52
CPC分类号： H01L25/065 , H01L2224/48091 , H01L2224/48247 , H01L2224/49113 , H01L2924/00014
摘要： A semiconductor package includes multiple embedded chips, each chip including a common circuit having substantially the same common function. The common circuit in a selected one of the chips is enabled. The common circuit in one or more other ones of the chips is disabled. As a result, the enabled common circuit performs the common function for the selected chip and the one or more other chips.
摘要翻译：半导体封装包括多个嵌入式芯片，每个芯片包括具有基本上相同的共同功能的公共电路。所选择的一个芯片中的公共电路被使能。一个或多个其他芯片中的公共电路被禁用。结果，使能的公共电路执行所选择的芯片和一个或多个其他芯片的共同功能。

24. 发明授权

US5886947A Semiconductor memory device with shared data input/output line 失效
标题翻译：具有共享数据输入/输出线的半导体存储器件
公开(公告)号：US5886947A
公开(公告)日：1999-03-23
申请号：US947280
申请日：1997-10-08
申请人： Ho-Cheol Lee
发明人： Ho-Cheol Lee
IPC分类号： G11C11/417 , G11C7/00 , G11C7/10 , G11C7/22 , G11C11/407 , G11C11/409 , G11C11/413 , G11C8/00
CPC分类号： G11C7/22 , G11C7/1048
摘要： The semiconductor memory device includes a clock signal generating circuit, a precharge circuit, a write circuit, and an input/output circuit. The clock signal generating circuit generates a second clock signal having a second state of a constant interval irrespective of a period of a first clock signal. The precharge circuit precharges a data input/output line in response to a precharge signal. The write circuit transfers, during a write operation, input data signal to the data input/output line each time the second clock signal is a first state under the state that a power signal and the precharge signal are the first state. The input/output circuit transfers data transmitted to the data input/output line to a cell.
摘要翻译：半导体存储器件包括时钟信号发生电路，预充电电路，写入电路和输入/输出电路。时钟信号发生电路产生具有恒定间隔的第二状态的第二时钟信号，而与第一时钟信号的周期无关。预充电电路响应于预充电信号对数据输入/输出线进行预充电。在电源信号和预充电信号为第一状态的状态下，每当第二时钟信号为第一状态时，写入电路在写入操作期间将输入数据信号传送到数据输入/输出线。输入/输出电路将发送到数据输入/输出线的数据传送到一个单元。

25. 发明授权

US5663913A Semiconductor memory device having high speed parallel transmission line operation and a method for forming parallel transmission lines 失效
标题翻译：具有高速并行传输线操作的半导体存储器件和用于形成并行传输线的方法
公开(公告)号：US5663913A
公开(公告)日：1997-09-02
申请号：US638373
申请日：1996-04-26
申请人： Ho-Cheol Lee , Hyun-Soon Jang
发明人： Ho-Cheol Lee , Hyun-Soon Jang
IPC分类号： G11C11/41 , G11C7/22 , G11C11/407 , G11C11/409 , H01L21/8242 , H01L27/108 , G11C7/00
CPC分类号： G11C7/22
摘要： A semiconductor memory device has the skew between the individual transmission lines of a parallel transmission bus minimized by the addition of respective load transmission lines to each of the individual transmission lines in the parallel bus. A first circuit unit including a first parallel bank of internal circuits for generating internal control signals is formed adjacent to a predetermined region within a chip. A second circuit unit includes a second parallel bank of internal circuits for performing a predetermined operation in response to an output of the first circuit unit. The second circuit transmits signals to the first circuit over a parallel bus comprised of a plurality of transmission lines connected respectively between the individual internal circuits of the first and second circuit units. A plurality of load transmission lines are connected respectively to predetermined portions of the individual transmission lines to thereby equalize the loads of the transmission lines.
摘要翻译：半导体存储器件通过向并行总线中的各个传输线路中的各个传输线路添加相应的负载传输线而使并行传输总线的各个传输线之间的偏移最小化。在芯片内与预定区域相邻地形成包括用于产生内部控制信号的第一并联的内部电路组的第一电路单元。第二电路单元包括用于响应于第一电路单元的输出执行预定操作的第二并联的内部电路组。第二电路通过由分别连接在第一和第二电路单元的各个内部电路之间的多条传输线组成的并行总线向第一电路发送信号。多个负载传输线分别连接到各个传输线的预定部分，从而均衡传输线的负载。

26. 发明授权

US5590086A Semiconductor memory having a plurality of I/O buses 失效
标题翻译：具有多个I / O总线的半导体存储器
公开(公告)号：US5590086A
公开(公告)日：1996-12-31
申请号：US580481
申请日：1995-12-29
申请人： Churoo Park , Hyun-Soon Jang , Chull-Soo Kim , Myung-Ho Kim , Seung-Hun Lee , Si-Yeol Lee , Ho-Cheol Lee , Tae-Jin Kim , Yun-Ho Choi
发明人： Churoo Park , Hyun-Soon Jang , Chull-Soo Kim , Myung-Ho Kim , Seung-Hun Lee , Si-Yeol Lee , Ho-Cheol Lee , Tae-Jin Kim , Yun-Ho Choi
IPC分类号： G11C11/401 , G11C7/00 , G11C7/10 , G11C11/403 , G11C11/406 , G11C11/407 , G11C11/4076 , G11C11/408 , G11C11/409 , G11C8/00
CPC分类号： G11C7/1018 , G11C11/406 , G11C11/40618 , G11C11/4076 , G11C11/408 , G11C11/4082 , G11C11/4087 , G11C7/1045 , G11C7/1072 , G11C7/222 , G11C7/225 , G11C2207/2281
摘要： A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.
摘要翻译：能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于灭活信号在预充电循环中工作。

27. 发明授权

US09070569B2 Semiconductor memory devices and semiconductor packages 有权
标题翻译：半导体存储器件和半导体封装
公开(公告)号：US09070569B2
公开(公告)日：2015-06-30
申请号：US14450359
申请日：2014-08-04
申请人： Ho-Cheol Lee , Chi-Sung Oh , Jin-Kuk Kim
发明人： Ho-Cheol Lee , Chi-Sung Oh , Jin-Kuk Kim
IPC分类号： H01L25/065 , G11C5/02 , G11C5/06 , H01L21/66 , H01L23/00 , H01L27/02 , H01L27/108
CPC分类号： H01L25/0657 , G11C5/025 , G11C5/06 , H01L22/32 , H01L24/09 , H01L24/73 , H01L27/0255 , H01L27/108 , H01L2224/0401 , H01L2224/0912 , H01L2224/09179 , H01L2224/09515 , H01L2224/13025 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/17181 , H01L2224/32225 , H01L2224/48227 , H01L2224/73207 , H01L2224/73265 , H01L2225/06541 , H01L2924/15311 , H01L2924/00012 , H01L2924/00
摘要： A semiconductor memory device includes a semiconductor die and an input-output bump pad part. The semiconductor die includes a plurality of memory cell arrays. The input-output bump pad part is formed in a central region of the semiconductor die. The input-output bump pad part provides a plurality of channels for connecting each of the memory cell arrays independently to an external device. The semiconductor memory device may adopt the multi-channel interface, thereby having high performance with relatively low power consumption.
摘要翻译：半导体存储器件包括半导体管芯和输入 - 输出凸块焊盘部分。半导体管芯包括多个存储单元阵列。输入输出凸块焊盘部分形成在半导体管芯的中心区域。输入 - 输出凸块焊盘部件提供多个通道，用于将每个存储单元阵列独立地连接到外部设备。半导体存储器件可以采用多通道接口，从而具有相对较低功耗的高性能。

28. 发明授权

US08322922B2 Method of outputting temperature data in semiconductor device and temperature data output circuit therefor 有权
标题翻译：在半导体器件中输出温度数据的方法及其温度数据输出电路
公开(公告)号：US08322922B2
公开(公告)日：2012-12-04
申请号：US12605032
申请日：2009-10-23
申请人： Yun-Young Lee , Kyu-Chan Lee , Ho-Cheol Lee
发明人： Yun-Young Lee , Kyu-Chan Lee , Ho-Cheol Lee
IPC分类号： G01K7/01 , G01K7/14
CPC分类号： G01K7/015 , G01K2219/00
摘要： A method of outputting temperature data in a semiconductor device and a temperature data output circuit are provided. A pulse signal is generated in response to a booting enable signal activated in response to a power-up signal and the generation is inactivated in response to a mode setting signal during a power-up operation. A comparison signal is generated in response to the pulse signal by comparing a reference voltage independent of temperature with a sense voltage that varies with temperature change. The temperature data is changed in response to the comparison signal. Thus, the temperature data output circuit can rapidly output the exact temperature of the semiconductor device measured during the power-up operation.
摘要翻译：提供了一种在半导体器件和温度数据输出电路中输出温度数据的方法。响应于响应于上电信号而被激活的引导使能信号而产生脉冲信号，并且响应于上电操作期间的模式设置信号而使生成失效。通过将与温度无关的参考电压与随温度变化而变化的感测电压进行比较，响应于脉冲信号产生比较信号。响应于比较信号来改变温度数据。因此，温度数据输出电路可以快速输出在上电操作期间测量的半导体器件的精确温度。

29. 发明申请

US20120188834A1 SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME 审中-公开
标题翻译：具有它的半导体存储器件和存储器系统
公开(公告)号：US20120188834A1
公开(公告)日：2012-07-26
申请号：US13441713
申请日：2012-04-06
申请人： Ho-Young Kim , Ho-Cheol Lee , Jung-Bae Lee
发明人： Ho-Young Kim , Ho-Cheol Lee , Jung-Bae Lee
IPC分类号： G11C7/22
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C7/1078 , G11C7/1084 , G11C7/222 , G11C2207/2272
摘要： A semiconductor memory device is disclosed. The semiconductor device includes a memory cell array, a clock signal generator configured to receive an external clock signal from the outside of the memory device and output an internal clock signal, and a data output unit configured to receive an internal data signal from the memory cell array and output a read data signal in response to the internal clock signal. The semiconductor memory device also includes a read data strobe unit configured to output a read data strobe signal having a cycle time of n times (n is an integer equal to or more than 2) a cycle time of the internal clock signal, based on the internal clock signal.
摘要翻译：公开了一种半导体存储器件。半导体器件包括存储单元阵列，时钟信号发生器，被配置为从存储器件的外部接收外部时钟信号并输出内部时钟信号;以及数据输出单元，被配置为从存储器单元接收内部数据信号阵列并响应于内部时钟信号输出读取数据信号。半导体存储器件还包括读取数据选通单元，其被配置为基于内部时钟信号的周期时间，输出具有n倍（n是等于或大于2的整数）的周期时间的读取数据选通信号内部时钟信号。

30. 发明授权

US08120986B2 Multi-port semiconductor memory device having variable access paths and method therefor 有权
标题翻译：具有可变存取路径的多端口半导体存储器件及其方法
公开(公告)号：US08120986B2
公开(公告)日：2012-02-21
申请号：US12785832
申请日：2010-05-24
申请人： Nam-Jong Kim , Ho-Cheol Lee , Kyoung-Hwan Kwon , Hyong-Ryol Hwang , Hyo-Joo Ahn
发明人： Nam-Jong Kim , Ho-Cheol Lee , Kyoung-Hwan Kwon , Hyong-Ryol Hwang , Hyo-Joo Ahn
IPC分类号： G11C8/00
CPC分类号： G11C8/12 , G11C7/1075 , G11C29/1201 , G11C29/26 , G11C29/48 , G11C2029/1802
摘要： A multi-port semiconductor memory device having variable access paths and a method therefor are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports.
摘要翻译：提供一种具有可变访问路径的多端口半导体存储器件及其方法。半导体存储器件包括多个输入/输出端口; 分成多个存储区域的存储器阵列; 以及选择控制单元，用于可变地控制存储区域和输入/输出端口之间的访问路径，使得通过至少一个输入/输出端口访问每个存储器区域。

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