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21. 发明授权

US07702979B2 Semiconductor integrated circuit incorporating test configuration and test method for the same 失效
标题翻译：半导体集成电路结合测试配置和测试方法相同
公开(公告)号：US07702979B2
公开(公告)日：2010-04-20
申请号：US11397899
申请日：2006-04-05
申请人： Masayuki Arai , Kazuhiko Iwasaki , Satoshi Fukumoto , Takeshi Shoda , Junichi Nishimoto
发明人： Masayuki Arai , Kazuhiko Iwasaki , Satoshi Fukumoto , Takeshi Shoda , Junichi Nishimoto
IPC分类号： G01R31/28
CPC分类号： G01R31/318544 , G01R31/318536
摘要： An object of the invention is to drastically reduce the area overhead in a semiconductor integrated circuit incorporating a test configuration that uses a partially rotational scan circuit. To achieve this, in the semiconductor integrated circuit incorporating the test configuration that comprises a combinational circuit (3) and a scan chain (2) constructed by connecting a plurality of scan flip-flops (5) in a chain, the scan chain (2) is divided into a plurality of sub scan-chains (20a to 20n) each of which has a partially rotational scan (PRS) function and a test response compaction (MISR) function. By performing a scan test in a plurality of steps while changing the combination of the sub scan-chains to be set as PRS and the sub scan-chains to be set as MISR, the test can be performed without having to provide a test response compactor separately from the scan chain, and thus the area overhead can be reduced.
摘要翻译：本发明的一个目的是大大减少包含使用部分旋转扫描电路的测试配置的半导体集成电路中的面积开销。为了实现这一点，在包括组合电路（3）和通过连接多个扫描触发器（5）构成的扫描链（2）的测试配置的半导体集成电路中，扫描链（2））被分成多个子扫描链（20a至20n），每个子扫描链具有部分旋转扫描（PRS）功能和测试响应压缩（MISR）功能。通过在将要设置为PRS的子扫描链和将被设置为MISR的副扫描链的组合改变的同时执行多个步骤中的扫描测试，可以执行测试而不必提供测试响应压缩器与扫描链分开，因此可以减少面积开销。

22. 发明申请

US20090171123A1 Catalyst and Process for Producing Ketone Using The Same 失效
标题翻译：催化剂及其制备方法
公开(公告)号：US20090171123A1
公开(公告)日：2009-07-02
申请号：US12087312
申请日：2007-01-03
申请人： Roger Gläser , Sudhir Dapurkar , Carsten Stöcker , Junichi Nishimoto , Masayoshi Murakami
发明人： Roger Gläser , Sudhir Dapurkar , Carsten Stöcker , Junichi Nishimoto , Masayoshi Murakami
IPC分类号： C07C49/303 , C07C49/00 , B01J29/068
CPC分类号： B01J23/44 , B01J27/188 , B01J29/0308 , B01J29/041 , B01J35/0006 , C07C45/34 , C07C49/403
摘要： There are disclosed a method for producing a ketone compound, which comprises reacting an olefin compound with molecular oxygen and water in the presence of an effective amount of proton and a catalyst containing i) a chlorine-free palladium source, ii) a heteropoly acid or an acid salt of a heteropoly acid, and iii) a mesoporous silicate, and catalysts for the process.
摘要翻译：公开了一种生产酮化合物的方法，该方法包括在有效量的质子存在下使烯烃化合物与分子氧和水反应，所述催化剂含有i）无氯钯源，ii）杂多酸或杂多酸的酸性盐，和iii）介孔硅酸盐，以及该方法的催化剂。

23. 发明授权

US07468626B2 Multiple circuit blocks with interblock control and power conservation 有权
标题翻译：具有互阻控制和省电的多电路块
公开(公告)号：US07468626B2
公开(公告)日：2008-12-23
申请号：US11448739
申请日：2006-06-08
申请人： Tadashi Hoshi , Kenji Hirose , Hideaki Abe , Junichi Nishimoto , Midori Nagayama
发明人： Tadashi Hoshi , Kenji Hirose , Hideaki Abe , Junichi Nishimoto , Midori Nagayama
IPC分类号： G11C5/14
CPC分类号： G06F1/3287 , G06F1/32 , G06F1/3203 , H01L2924/0002 , Y02D10/171 , Y02D50/20 , H01L2924/00
摘要： A semiconductor integrated circuit is provided including a plurality of circuit blocks and adapted to cut off the supply of power source voltage to any one of the circuit blocks. The integrated circuit includes an interblock interface circuit provided on a signal path from the elected circuit block to other circuit blocks, wherein a single output of the interblock interface circuit is branched out to other circuit blocks. The interblock interface circuit includes a signal gate for preventing signal transmission to other circuit blocks and includes a storage unit for storing a signal right before the power cut.
摘要翻译：提供一种半导体集成电路，其包括多个电路块，并且适于切断对任何一个电路块的电源电压的供应。集成电路包括设置在从被选择的电路块到其它电路块的信号路径上的互阻止接口电路，其中，将块间接口电路的单个输出分支到其他电路块。帧间接口电路包括用于防止信号传输到其他电路块的信号门，并且包括用于在断电之前存储信号的存储单元。

24. 发明授权

US07263565B2 Bus system and integrated circuit having an address monitor unit 有权
标题翻译：总线系统和具有地址监视器单元的集成电路
公开(公告)号：US07263565B2
公开(公告)日：2007-08-28
申请号：US11213795
申请日：2005-08-30
申请人： Yasuhiro Tawara , Junichi Nishimoto
发明人： Yasuhiro Tawara , Junichi Nishimoto
IPC分类号： G06F13/00 , G06F13/36 , G06F17/00 , G06F13/40
CPC分类号： G06F13/404
摘要： A bus system for handling changes in an access address range of a subject-of-access or a bus master is disclosed. The bus system can have an address monitor unit including a table which is shared among a plurality of bus masters and stores therein access right information. By referencing the table, the presence or absence of an access right for each of the bus masters can be determined. The table may be rewritten as appropriate to handle address range changes.
摘要翻译：公开了一种用于处理访问主体或总线主机的访问地址范围的变化的总线系统。总线系统可以具有包括在多个总线主机之间共享的表的存储权限信息的地址监视器单元。通过参考该表，可以确定每个总线主机的访问权限的存在或不存在。可以适当地重写表以处理地址范围更改。

25. 发明申请

US20050152186A1 Semiconductor integrated circuit device 有权
公开(公告)号：US20050152186A1
公开(公告)日：2005-07-14
申请号：US11072309
申请日：2005-03-07
申请人： Koichiro Ishibashi , Shoji Shukuri , Kazumasa Yanagisawa , Junichi Nishimoto , Masanao Yamaoka , Masakazu Aoki
发明人： Koichiro Ishibashi , Shoji Shukuri , Kazumasa Yanagisawa , Junichi Nishimoto , Masanao Yamaoka , Masakazu Aoki
IPC分类号： H01L21/8247 , G11C16/04 , G11C29/00 , G11C29/04 , G11C29/12 , G11C29/42 , H01L21/66 , H01L23/532 , H01L23/544 , H01L27/02 , H01L27/105 , H01L27/108 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： G11C16/0441 , B82Y10/00 , C04B28/02 , C04B2103/0097 , C04B2111/00017 , C04B2111/00456 , C04B2111/00517 , C04B2111/2092 , G11C16/04 , G11C29/12 , G11C29/789 , G11C29/848 , G11C2216/10 , H01L22/22 , H01L23/53228 , H01L23/544 , H01L24/48 , H01L24/49 , H01L27/0211 , H01L27/105 , H01L27/10897 , H01L2223/5444 , H01L2223/54473 , H01L2224/05554 , H01L2224/05599 , H01L2224/48091 , H01L2224/48472 , H01L2224/49175 , H01L2224/85399 , H01L2924/00014 , H01L2924/10162 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , C04B14/04 , C04B14/06 , C04B14/14 , C04B14/16 , C04B20/008 , C04B24/00 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： To reduce cost of defect redundancy and trimming in a semiconductor integrated circuit having multiple layer wirings and copper wirings, an address for salvaging a defect of a memory cell array in a semiconductor is stored by using a nonvolatile memory element constituting a floating electrode by a first layer of polysilicon, or the nonvolatile memory element is programmed in testing the semiconductor integrated circuit. As a result, a special process is not needed in forming the nonvolatile memory element. In other words, the nonvolatile memory element can be formed in a process of forming a CMOS device and an apparatus of a laser beam for programming is not needed since the programming is carried out in testing. Thus, the time necessary for programming can be shortened, and, therefore, testing costs can be reduced.

26. 发明授权

US06601154B2 Cache memory employing dynamically controlled data array start timing and a microcomputer using the same 失效
公开(公告)号：US06601154B2
公开(公告)日：2003-07-29
申请号：US10084229
申请日：2002-02-28
申请人： Yasuhisa Shimazaki , Seiichi Nagata , Katuhiro Norisue , Koichiro Ishibashi , Junichi Nishimoto , Shinichi Yoshioka , Susumu Narita
发明人： Yasuhisa Shimazaki , Seiichi Nagata , Katuhiro Norisue , Koichiro Ishibashi , Junichi Nishimoto , Shinichi Yoshioka , Susumu Narita
IPC分类号： G06F1206
CPC分类号： G06F12/0864 , G06F2212/1028 , Y02D10/13
摘要： A comparator having a hit signal that is high, before a hit check is established in each way of an address array, and that goes low, when a mishit has been established. When a clock frequency is high, the address array is activated by the first clock signal, and thereafter, all ways of a data array are activated by the second clock signal before the hit check is established. When the hit check has been established, data read from a way which has the hit is output onto a data line and an operation in the way which has a mishit is stopped.

27. 发明申请

US20120025905A1 Multiple circuit blocks with interblock control and power conservation 有权
标题翻译：具有互阻控制和省电的多电路块
公开(公告)号：US20120025905A1
公开(公告)日：2012-02-02
申请号：US13200856
申请日：2011-10-04
申请人： Tadashi Hoshi , Kenji Hirose , Hideaki Abe , Junichi Nishimoto , Midori Nagayama
发明人： Tadashi Hoshi , Kenji Hirose , Hideaki Abe , Junichi Nishimoto , Midori Nagayama
IPC分类号： H01L25/00
CPC分类号： G06F1/3287 , G06F1/32 , G06F1/3203 , H01L2924/0002 , Y02D10/171 , Y02D50/20 , H01L2924/00
摘要： A mobile telephone is provided that includes a plurality of circuit blocks and adapted to cut off the supply of power source voltage to any one of the circuit blocks. The mobile telephone also includes an interblock interface circuit provided on a signal path between an elected circuit block and a branch point at which the signal path branches into different branch paths so as to connect to other circuit blocks. The interblock interface circuit includes a signal gate for preventing signal transmission from the elected circuit block to the other circuit blocks, and includes a storage unit for storing a signal right before the power cut-off.
摘要翻译：提供一种移动电话，其包括多个电路块，并且适于切断对任何一个电路块的电源电压的供应。移动电话还包括设置在选通的电路块和信号路径分支到不同分支路径的分支点之间的信号路径上的块间接口电路，以便连接到其他电路块。所述帧间接口电路包括用于防止从所选择的电路块到其他电路块的信号传输的信号门，并且包括用于在电源切断之前存储信号的存储单元。

28. 发明申请

US20110021842A1 METHOD FOR PRODUCING CARBONYL COMPOUND 审中-公开
标题翻译：生产碳化合物的方法
公开(公告)号：US20110021842A1
公开(公告)日：2011-01-27
申请号：US12933346
申请日：2009-03-17
申请人： Junichi Nishimoto , Masayoshi Murakami
发明人： Junichi Nishimoto , Masayoshi Murakami
IPC分类号： C07C45/34
CPC分类号： C07C45/34 , B01J23/002 , B01J23/898 , B01J23/8993 , B01J27/188 , B01J27/199 , B01J35/0006 , B01J37/04 , B01J2523/00 , C07C49/403 , B01J2523/51 , B01J2523/55 , B01J2523/68 , B01J2523/824 , B01J2523/842
摘要： A process for producing a carbonyl compound, the process comprising reacting an olefin with molecular oxygen in the presence of a heteropoly anion, a palladium catalyst, and an iron compound, in an acetonitrile-containing aqueous solution, in the presence of an effective amount of a proton under a condition that an amount of an alkali metal in a reaction system is 1 or less g-atm per 1 mol of the heteropoly anion.
摘要翻译：一种制备羰基化合物的方法，该方法包括在杂多阴离子，钯催化剂和铁化合物的存在下，在含乙腈的水溶液中，在有效量的在反应体系中的碱金属的量相对于每1mol杂多阴离子为1g以上的条件下为质子。

29. 发明申请

US20100164610A1 Multiple circuit blocks with interblock control and power conservation 有权
标题翻译：具有互阻控制和省电的多电路块
公开(公告)号：US20100164610A1
公开(公告)日：2010-07-01
申请号：US12659369
申请日：2010-03-05
申请人： Tadashi Hoshi , Kenji Hirose , Hideaki Abe , Junichi Nishimoto
发明人： Tadashi Hoshi , Kenji Hirose , Hideaki Abe , Junichi Nishimoto
IPC分类号： G05F1/10
CPC分类号： G06F1/3287 , G06F1/32 , G06F1/3203 , H01L2924/0002 , Y02D10/171 , Y02D50/20 , H01L2924/00
摘要： A mobile telephone is provided that includes a plurality of circuit blocks and adapted to cut off the supply of power source voltage to any one of the circuit blocks. The mobile telephone also includes an interblock interface circuit provided on a signal path between an elected circuit block and a branch point at which the signal path branches into different branch paths so as to connect to other circuit blocks. The interblock interface circuit includes a signal gate for preventing signal transmission from the elected circuit block to the other circuit blocks, and includes a storage unit for storing a signal right before the power cut-off.
摘要翻译：提供一种移动电话，其包括多个电路块，并且适于切断对任何一个电路块的电源电压的供应。移动电话还包括设置在选通的电路块和信号路径分支到不同分支路径的分支点之间的信号路径上的块间接口电路，以便连接到其他电路块。所述帧间接口电路包括用于防止从所选择的电路块到其他电路块的信号传输的信号门，并且包括用于在电源切断之前存储信号的存储单元。

30. 发明申请

US20060226895A1 Multiple circuit blocks with interblock control and power conservation 有权
公开(公告)号：US20060226895A1
公开(公告)日：2006-10-12
申请号：US11448743
申请日：2006-06-08
申请人： Tadashi Hoshi , Kenji Hirose , Hideaki Abe , Junichi Nishimoto , Midori Nagayama
发明人： Tadashi Hoshi , Kenji Hirose , Hideaki Abe , Junichi Nishimoto , Midori Nagayama
IPC分类号： G05F1/10
CPC分类号： G06F1/3287 , G06F1/32 , G06F1/3203 , H01L2924/0002 , Y02D10/171 , Y02D50/20 , H01L2924/00
摘要： A semiconductor integrated circuit is provided including a plurality of circuit blocks and adapted to cut off the supply of power source voltage to any one of the circuit blocks. The integrated circuit includes an interblock interface circuit provided on a signal path from the elected circuit block to other circuit blocks, wherein a single output of the interblock interface circuit is branched out to other circuit blocks. The interblock interface circuit includes a signal gate for preventing signal transmission to other circuit blocks and includes a storage unit for storing a signal right before the power cut.

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