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21. 发明授权

US5693955A Tunnel transistor 失效
标题翻译：隧道晶体管
公开(公告)号：US5693955A
公开(公告)日：1997-12-02
申请号：US625666
申请日：1996-03-29
申请人： Herbert Goronkin , Saied N. Tehrani
发明人： Herbert Goronkin , Saied N. Tehrani
IPC分类号： H01L29/06 , H01L29/772 , H01L29/78 , H01L49/02 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L29/772
摘要： A tunnel transistor including source and drain and a silicon oxide tunneling layer overlying the source. A polysilicon quantum well layer positioned on the tunneling layer and in contact with the drain. The quantum well layer having a thickness which places the ground state above the Fermi level. A silicon oxide insulating layer positioned on the quantum well layer and a gate electrode positioned on the insulating layer overlying the quantum well layer and the source terminal. The tunneling layer being thin enough to allow tunneling between the source and the quantum well layer, and the insulating layer being thick enough to prevent tunneling therethrough.
摘要翻译：包括源极和漏极的隧道晶体管和覆盖源极的氧化硅隧道层。位于隧道层上并与漏极接触的多晶硅量子阱层。量子阱层具有将基态置于费米能级之上的厚度。定位在量子阱层上的氧化硅绝缘层和位于覆盖量子阱层和源极端子的绝缘层上的栅电极。隧道层足够薄以允许源极和量子阱层之间的隧穿，并且绝缘层足够厚以防止隧道穿过其中。

22. 发明授权

US5049951A Superlattice field effect transistor with monolayer confinement 失效
标题翻译：超晶格场效应晶体管单层约束
公开(公告)号：US5049951A
公开(公告)日：1991-09-17
申请号：US630613
申请日：1990-12-20
申请人： Herbert Goronkin , Saied N. Tehrani , X. Theodore Zhu
发明人： Herbert Goronkin , Saied N. Tehrani , X. Theodore Zhu
IPC分类号： H01L21/203 , H01L21/338 , H01L29/10 , H01L29/12 , H01L29/15 , H01L29/205 , H01L29/778 , H01L29/812
CPC分类号： B82Y10/00 , H01L29/1075 , H01L29/122 , H01L29/155 , H01L29/7782
摘要： A heterojunction field effect transistor (HFET) having a source, drain, and channel, wherein the channel is a top layer of a superlattice buffer, eliminating the need for a thick buffer layer. The superlattice buffer comprises alternating barrier and quantum well layers which are thin enough to provide wide separation in energy bands within the quantum wells. In a preferred embodiment the channel comprises a quantum well and one to five monolayers having a different bandgap than the channel region and serves to modify electron wave function and conduction band energy in the channel region. Preferably, a ten period AlAs/GaAs superlattice is formed underneath the channel.
摘要翻译：具有源极，漏极和沟道的异质结场效应晶体管（HFET），其中该沟道是超晶格缓冲器的顶层，消除了对厚缓冲层的需要。超晶格缓冲器包括交替的势垒和量子阱层，它们足够薄以在量子阱内的能带中提供宽的分离。在优选实施例中，该通道包括量子阱和一至五个具有与沟道区不同的带隙的单层，并且用于修改沟道区中的电子波函数和导带能量。优选地，在通道下方形成十个周期的AlAs / GaAs超晶格。

23. 发明授权

US4987463A FET having a high trap concentration interface layer 失效
标题翻译：具有高陷阱浓度界面层的FET
公开(公告)号：US4987463A
公开(公告)日：1991-01-22
申请号：US399099
申请日：1989-08-28
申请人： Herbert Goronkin , Saied N. Tehrani
发明人： Herbert Goronkin , Saied N. Tehrani
IPC分类号： H01L29/812 , H01L21/338 , H01L29/10 , H01L29/32 , H01L29/778
CPC分类号： H01L29/1075 , H01L29/32
摘要： A FET having a high trap concentration interface layer and method of fabrication includes a semi-insulating gallium arsenide substrate having a high trap concentration interface layer formed therein. An non-intentionally doped buffer layer, also comprised of gallium arsenide, is then formed on the interface layer and is followed by the formation of a doped aluminum gallium arsenide layer thereon. A source, a gate and a drain are then formed on the FET layers. The FET and method disclosed herein are especially applicable for low current (5-1000 microamp) operation of microwave low-noise FETs.

24. 发明授权

US5482875A Method for forming a linear heterojunction field effect transistor 失效
标题翻译：用于形成线性异质结场效应晶体管的方法
公开(公告)号：US5482875A
公开(公告)日：1996-01-09
申请号：US229266
申请日：1994-04-18
申请人： Rimantas L. Vaitkus , Saied N. Tehrani , Vijay K. Nair , Herbert Goronkin
发明人： Rimantas L. Vaitkus , Saied N. Tehrani , Vijay K. Nair , Herbert Goronkin
IPC分类号： H01L29/812 , H01L21/338 , H01L29/08 , H01L29/10 , H01L29/778 , H01L29/80 , H01L21/335
CPC分类号： H01L29/7783 , H01L29/0891 , H01L29/1029 , Y10S148/072
摘要： A low power heterojunction field effect transistor (10, 30, 50, 60) capable of operating at low drain currents while having a low intermodulation distortion. A channel restriction region (9, 38, 51) is formed between the gate electrodes (24, 41, 69) and the drain electrodes (25, 46, 65). The channel restriction region (9, 38, 51) depletes the channel layer (13, 33) thereby constricting a channel and lowering a drain saturation current. The channel restriction region (9, 38, 51) may be used to set a desired drain saturation current such that a second derivative of the transconductance with respect to the gate-source voltage is approximately zero and a first derivative of the transconductance with respect to the gate-source voltage is, approximately, a relative maximum at the desired operating point.
摘要翻译：低功率异质结场效应晶体管（10,30,50,60）能够以低漏电流工作，同时具有低的互调失真。在栅极（24,41,69）和漏极（25,46,65）之间形成沟道限制区（9,38,51）。信道限制区域（9,38,51）耗尽信道层（13,33），从而限制信道并降低漏极饱和电流。通道限制区域（9,38,51）可以用于设置所需的漏极饱和电流，使得相对于栅极 - 源极电压的跨导的二次导数近似为零，并且跨导的第一导数相对于栅极源极电压大约在所需工作点处的相对最大值。

25. 发明授权

US5804458A Method of fabricating spaced apart submicron magnetic memory cells 失效
标题翻译：制造间隔亚微米磁记忆体的方法
公开(公告)号：US5804458A
公开(公告)日：1998-09-08
申请号：US766076
申请日：1996-12-16
申请人： Saied N. Tehrani , Mark Durlam , Herbert Goronkin
发明人： Saied N. Tehrani , Mark Durlam , Herbert Goronkin
IPC分类号： H01L27/115 , H01L21/70
CPC分类号： H01L27/115 , H01L27/222 , H01L43/12
摘要： A method of fabricating a plurality of spaced apart submicron memory cells is disclosed, including the steps of depositing a magnetoresistive system on a substrate formation, depositing and patterning a first layer of material to form sidewalls, and depositing a second, selectively etchable, layer of material on the first layer of material, etching the second layer of material to define spacers on the sidewalls of the first layer of material, etching the magnetoresistive system, using the spacers as a mask, to define a plurality of spaced apart submicron magnetic memory cells, and depositing electrical contacts on the plurality of spaced apart submicron magnetic memory cells.
摘要翻译：公开了一种制造多个间隔开的亚微米存储器单元的方法，包括以下步骤：在衬底形成上沉积磁阻系统，沉积和图形化第一材料层以形成侧壁，以及沉积第二层可选择的可蚀刻的材料在第一层材料上蚀刻第二层材料以在第一材料层的侧壁上限定间隔物，使用间隔物作为掩模蚀刻磁阻系统以限定多个间隔开的亚微米磁存储器单元并且在多个间隔开的亚微米磁存储器单元上沉积电触点。

26. 发明授权

US5742082A Stable FET with shielding region in the substrate 失效
标题翻译：稳定的FET，在衬底中具有屏蔽区域
公开(公告)号：US5742082A
公开(公告)日：1998-04-21
申请号：US753312
申请日：1996-11-22
申请人： Saied N. Tehrani , Jenn-Hwa Huang , Herbert Goronkin , Ernest Schirmann , Marino J. Martinez
发明人： Saied N. Tehrani , Jenn-Hwa Huang , Herbert Goronkin , Ernest Schirmann , Marino J. Martinez
IPC分类号： H01L21/338 , H01L29/10 , H01L29/812 , H01L29/80
CPC分类号： H01L29/66863 , H01L29/1075 , H01L29/8128
摘要： A stable FET including a substrate structure with a doped layer formed as a portion of the substrate structure and defining an electrically conductive shielding region adjacent a surface of the substrate structure. A channel region is positioned on the shielding region and includes a plurality of epitaxial layers grown on the surface of the substrate structure in overlying relationship to the doped layer. A drain and a source are positioned on the channel region in spaced relationship from each other with a gate positioned in overlying relationship on the channel region between the drain and source. An externally accessible electrical contact is connected to the shielding region and to the source region to provide a path for the removal of internally generated charges, such as holes.
摘要翻译：一种稳定的FET，其包括具有掺杂层的衬底结构，所述掺杂层形成为所述衬底结构的一部分并且限定邻近所述衬底结构的表面的导电屏蔽区域。通道区域位于屏蔽区域上，并且包括以与掺杂层相重叠的方式在衬底结构的表面上生长的多个外延层。漏极和源极以彼此间隔开的关系定位在沟道区上，栅极位于漏极和源极之间的沟道区上的上限关系。外部可接触的电触点连接到屏蔽区域和源极区域，以提供用于去除内部产生的电荷（例如孔）的路径。

27. 发明授权

US5732016A Memory cell structure in a magnetic random access memory and a method for fabricating thereof 失效
标题翻译：磁性随机存取存储器中的存储单元结构及其制造方法
公开(公告)号：US5732016A
公开(公告)日：1998-03-24
申请号：US674387
申请日：1996-07-02
申请人： Eugene Chen , Saied N. Tehrani , Herbert Goronkin
发明人： Eugene Chen , Saied N. Tehrani , Herbert Goronkin
IPC分类号： H01L43/08 , G11C11/14 , G11C11/15 , H01L21/8246 , H01L27/105 , G11C11/00
CPC分类号： G11C11/14 , H01L27/222 , H01L43/08
摘要： A magnetic random access memory (MRAM) cell structure (10) with a portion of giant magnetoresistive (GMR) material (11), around which single or multiple word line (12) is wound, is provided. Magnetic field generated by word current (13, 14) superimposed in portion of GMR material (11) so that a total strength of magnetic field increases proportionally. The same word current is passed through the portion of GMR material (11) multiple times, thus producing equivalent word field by many times as large word current in a conventional MRAM cell.
摘要翻译：提供具有卷绕单字或多字线（12）的巨磁阻（GMR）材料（11）的一部分的磁随机存取存储器（MRAM）单元结构（10）。由字电流（13,14）产生的磁场叠加在GMR材料（11）的一部分中，使得磁场的总强度成比例地增加。相同的字电流多次通过GMR材料（11）的部分，从而在常规MRAM单元中产生大字电流多次的等效字场。

28. 发明授权

US5304825A Linear heterojunction field effect transistor 失效
标题翻译：线性异质结场效应晶体管
公开(公告)号：US5304825A
公开(公告)日：1994-04-19
申请号：US932526
申请日：1992-08-20
申请人： Rimantas L. Vaitkus , Saied N. Tehrani , Vijay K. Nair , Herbert Goronkin
发明人： Rimantas L. Vaitkus , Saied N. Tehrani , Vijay K. Nair , Herbert Goronkin
IPC分类号： H01L29/812 , H01L21/338 , H01L29/08 , H01L29/10 , H01L29/778 , H01L29/80 , H01L31/072 , H01L31/0328 , H01L31/0336 , H01L31/109
CPC分类号： H01L29/7783 , H01L29/0891 , H01L29/1029 , Y10S148/072
摘要： A low power heterojunction field effect transistor (10, 30, 50, 60) capable of operating at low drain currents while having a low intermodulation distortion. A channel restriction region (9, 38, 51) is formed between the gate electrodes (24, 41, 69) and the drain electrodes (25, 46, 65). The channel restriction region (9, 38, 51) depletes the channel layer (13, 33) thereby constricting a channel and lowering a drain saturation current. The channel restriction region (9, 38, 51) may be used to set a desired drain saturation current such that a second derivative of the transconductance with respect to the gate-source voltage is approximately zero and a first derivative of the transconductance with respect to the gate-source voltage is, approximately, a relative maximum at the desired operating point.
摘要翻译：低功率异质结场效应晶体管（10,30,50,60）能够以低漏电流工作，同时具有低的互调失真。在栅极（24,41,69）和漏极（25,46,65）之间形成沟道限制区（9,38,51）。信道限制区域（9,38,51）耗尽信道层（13,33），从而限制信道并降低漏极饱和电流。通道限制区域（9,38,51）可以用于设置所需的漏极饱和电流，使得相对于栅极 - 源极电压的跨导的二次导数近似为零，并且跨导的第一导数相对于栅极源极电压大约在所需工作点处的相对最大值。

29. 发明授权

US5172384A Low threshold current laser 失效
标题翻译：低阈值电流激光器
公开(公告)号：US5172384A
公开(公告)日：1992-12-15
申请号：US695062
申请日：1991-05-03
申请人： Herbert Goronkin , Michael S. Lebby , Saied N. Tehrani
发明人： Herbert Goronkin , Michael S. Lebby , Saied N. Tehrani
IPC分类号： G02F1/017 , H01L33/00 , H01S5/34
CPC分类号： H01S5/34 , B82Y20/00 , G02F1/017 , H01S5/3403
摘要： A thin layer, typically a monolayer, of a small band gap material (37) is inserted into the active layer (14) of a quantum well semiconductor device (36, 51). The band gap of the thin layer (37) is smaller than the band gap of the material in the active layer (14), thereby shifting carrier concentrations in the quantum well (26d, 26e, 26h, 26n) of the active layer (14) toward the thin layer (37). This shift increases alignment between the electron wave function (42, 54) and the hole wave function (44, 57) in the quantum well (26d, 26e, 26h, 26n) which increases the probability of stimulated photon emissions thereby reducing the threshold current and threshold voltage of the quantum well semiconductor device (36, 51).
摘要翻译：将小带隙材料（37）的薄层（通常为单层）插入量子阱半导体器件（36,51）的有源层（14）中。薄层（37）的带隙比有源层（14）中的材料的带隙小，从而使有源层（14）的量子阱（26d，26e，26h，26n）中的载流子浓度移位）朝向薄层（37）。这种移动增加了量子阱（26d，26e，26h，26n）中的电子波函数（42,54）和空穴波函数（44,57）之间的对准，这增加了被激发的光子发射的概率，从而降低阈值电流和量子阱半导体器件（36,51）的阈值电压。

30. 发明授权

US5141879A Method of fabricating a FET having a high trap concentration interface layer 失效
标题翻译：制造具有高陷阱浓度界面层的FET的方法
公开(公告)号：US5141879A
公开(公告)日：1992-08-25
申请号：US563128
申请日：1990-08-06
申请人： Herbert Goronkin , Saied N. Tehrani
发明人： Herbert Goronkin , Saied N. Tehrani
IPC分类号： H01L29/10 , H01L29/32
CPC分类号： H01L29/1075 , H01L29/32 , Y10S438/904
摘要： A FET having a high trap concentration interface layer and method of fabrication includes a semi-insulating gallium arsenide substrate having a high trap concentration interface layer formed therein. An non-intentionally doped buffer layer, also comprised of gallium arsenide, is then formed on the interface layer and is followed by the formation of a doped aluminum gallium arsenide layer thereon. A source, a gate and a drain are then formed on the FET layers. The FET and method disclosed herein are especially applicable for low current (5-1000 microamp) operation of microwave low-noise FETs.
摘要翻译：具有高陷阱浓度界面层的FET和制造方法包括其中形成有高陷阱浓度界面层的半绝缘砷化镓衬底。然后在界面层上形成也由砷化镓组成的非有意掺杂的缓冲层，随后在其上形成掺杂的砷化镓铝层。然后在FET层上形成源极，栅极和漏极。本文公开的FET和方法特别适用于微波低噪声FET的低电流（5-1000微安）操作。

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